JP2811766B2 - Active matrix display device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to an active matrix type liquid crystal display device having a gate connection type opposed matrix structure, and particularly to a panel structure suitable for interlaced driving of the liquid crystal display device having the above structure. The object of the present invention is to provide an improved structure of a gate connection opposed matrix type liquid crystal display device, which makes it possible to suppress the effective value fluctuation of the liquid crystal cell voltage to a negligible level. Comprising a plurality of display electrodes, thin film transistors corresponding to the display electrodes, and a plurality of scan bus lines arranged corresponding to rows of the matrix,
In the active-matrix display configuration of a gate connection type opposed matrix system in which a gate of each thin film transistor is connected to a scan bus line corresponding to a row to which the thin film transistor belongs, and a drain is connected to a scan bus line adjacent in a scanning direction, the display electrodes and The parasitic capacitance C _GS between the corresponding scan bus line and the parasitic capacitance between each display electrode and the adjacent scan bus line in the scanning direction.
C _DS is configured to have a relationship of C _GS ≦ C _DS.

[Industrial applications]

The present invention relates to an active matrix display device having a gate connection type opposing matrix structure, and more particularly to a panel structure suitable for interlacing a liquid crystal display device having the above structure.

The active matrix type display device is provided with switching elements corresponding to a large number of pixels, so that each pixel can be controlled independently. Therefore, even if the number of lines increases with an increase in the display capacity, a problem such as a decrease in the drive duty ratio resulting in a decrease in contrast and a decrease in the viewing angle does not occur as in the simple matrix type display device. It has advantages and has been put to practical use as a display device for a portable television receiver or a small information equipment terminal device. In order to use such an active matrix display device instead of a CRT (cathode ray tube) display device, it is necessary that the display quality be further improved and interlaced driving be possible.

[Conventional technology]

An active matrix display device generally uses a liquid crystal as a display medium and a thin film transistor (hereinafter abbreviated as “TFT”) as a switching element. In addition, since the scan bus lines and the data bus lines are formed on one substrate facing each other, it is necessary to add an interlayer insulating layer for preventing a mutual short circuit at the intersection between the scan bus lines and the data bus lines. There is. Therefore, it has been difficult to improve the production yield.

Therefore, the inventors of the present application first formed a scan bus line and a data bus line on one and the other substrates facing each other to eliminate the intersection of the bus lines and eliminate the need for an interlayer insulating layer. A facing matrix type liquid crystal display device has been proposed as Japanese Patent Application No. 61-212696.

FIG. 5 is an equivalent circuit diagram of the gate connection opposed matrix type liquid crystal panel, and FIG. 6 is an exploded perspective view thereof.

The gate connection facing matrix type liquid crystal panel is composed of a TFT 31 serving as a switching element, one electrode 38 of a liquid crystal cell 35 serving as a display element, and a scan bus line on an insulating substrate 39 made of glass or the like which is opposed to one another. S _2n-1 , S _2n ,
S _{2n + 1} ,... And adjacent scan bus lines S
_2n and S _{2n + 1} , one scan bus line S _2n
Is connected to the gate 32 of the TFT 31, the other scan bus line S _{2n + 1} is connected to the drain 34, and the display electrode 3 of the liquid crystal cell 35 is connected.
8 is connected to a source 33, and the other is an insulating substrate 40 made of glass or the like.
The data bus lines D _m , D _{m + 1} ,...
Are formed, and liquid crystal is sealed between one and the other substrates 39 and 40. The V _D is the data voltage, Va is the address voltage,
Vr indicates a reference voltage, and Voff indicates an off voltage.

In this liquid crystal panel, applying an address voltage Va to a scan bus line, the reference voltage Vr is applied to scan bus line adjacent to the scanning direction, the data voltage V _D indicating the data to be displayed respectively to the data bus line By applying, one line display can be performed,
By sequentially repeating this operation in the scanning direction, it is possible to drive the gate connection opposed matrix type liquid crystal display device. The present inventors have previously proposed a driving method for interlaced driving of this gate connection opposed matrix type liquid crystal display device.

The driving method will be described with reference to FIG. It is assumed that the scan bus line _S2n-1 has been selected. An address voltage Va is applied to the selected scan bus line S _2n-1 , and simultaneously the scan bus lines S _2n ,
A reference voltage Vr and an address voltage Va are applied to S _{2n + 1} , respectively. As the reference voltage Vr, two levels of Vr + and Vr- may be used in accordance with the sign of the data voltage to be written. Here, Vr + <Vr− <Va. FIG. 7 shows an example in which these two levels of reference voltages Vr +, Vr- are used.

At time τ _A , after writing of the data voltage to the scan bus line S _2n−1 , τ _M after 1/2 frame has elapsed
At this timing, the reference voltage Vr + is applied to the scan bus line S _2n-1 to which the gate is connected in order to write the data of the previous scan bus line S _2n-2 . Here, the reference voltage is set to Vr + in order to invert the polarity of the voltage written to the liquid crystal cell 35 for each line.

High positive voltage Va is the bus line S _2n one after this
Is applied, the bias voltage to the drain of the gate becomes a negative value. However, the source potential (P _2n−1 , _m ) is the same as the reference voltage Vr + at the time of writing at τ _A , but the capacitance between the gate and the source is affected by the fall of the address pulse (Va Voff) immediately after the writing. The source potential is lowered by ΔV through the coupling. Since this voltage is maintained as it is, τ
_{At M} , the bias voltage for the source of the gate is positive.

Therefore mid TFT is turned on (half-selected), and the potential of the display electrode liquid crystal cell 35 at both ends in the tau _M as shown in FIG. (LC
_2n-1 , _m ) produces a change by _VL . Since this change continues until writing is performed in the next frame, the change in the effective value of the liquid crystal cell voltage is not negligible, and this is a problem particularly when performing gradation display.

[Problems to be solved by the invention]

As described above, the gate connection opposed matrix type liquid crystal display device can be interlaced, but the fluctuation of the effective value of the liquid crystal cell voltage is not necessarily suppressed to a negligible level, and particularly, gradation display is performed. This is a problem.

It is an object of the present invention to provide an improved structure of a gate connection opposed matrix type liquid crystal display device which makes it possible to suppress the fluctuation of the effective value of the liquid crystal cell voltage to a negligible level during interlace driving.

[Means for solving the problem]

As shown in FIG. 1 (a), the parasitic capacitance of each part in the active matrix includes the liquid crystal cell capacitance C _LC , the gate-source capacitance C _{GS of} the TFT, the drain and the scan bus line adjacent to the scan direction. 3 Tsugaaru of capacity C _DS. The invention among these, the two C _GS and C _DS, is obtained by a C _GS ≦ C _DS.

As described later, the above C _GS is represented by the sum of Cgs and Cgb,
_DS is approximately equal to Cdb.

Therefore, the present invention provides a method for controlling the gap between the two scan bus lines S _2n and S _{2n + 1} adjacent to the display electrode 38 and the two scan bus lines adjacent to the gate G and the drain D, respectively.
The length of the connection lines 21 and 22 leading to S _2n and S _{2n + 1} , that is, the distance from the TFT 31 to two adjacent scan bus lines S _2n and S _{2n + 1} and the connection lines 21 and 22 C _GS ≦ C _DS , for example, by selecting a gap with the electrode 38.

(Operation)

FIG. 1B is a diagram for explaining the parasitic capacitance of the TFT matrix in detail.

Since the capacitance Cds between the drain and the source of the TFT can be ignored, C _DS is determined by the distributed capacitance Cdb between the bus line in close proximity and in this little display electrode, a C _DS ≒ Cdb.

Meanwhile C _GS is the sum of the distributed capacitance Cgb the proximity bus line and the channel capacitance Cgs of the TFT. That is, C _GS = Cgs + Cgb Of these, Cgs is TFT according to the specification as a display device.
Is difficult to control arbitrarily, but Cdb, Cg, which is the distributed capacitance with other adjacent bus lines.
b can be controlled by the layout of the TFT matrix, and can satisfy C _GS ≦ C _DS as described above.

The operation of the present invention thus configured will be described with reference to the principle explanatory diagram of FIG.

Focusing on the _canvas line S _2n-1 , the previous line S
Timing tau _M of writing _2n-2, the address voltage pulse peak value Va applied to the next line S _2n, through the parasitic capacitance C _DS between the drain and the source, potential fluctuations in the potential P _2n-1 of the display electrode 38 ΔV ′ can be generated. The potential variation [Delta] V 'acts in a direction to cancel the voltage fluctuation [Delta] V due to the parasitic capacitance C _GS between the gate and the source immediately after writing.

As shown in FIG. 1A, the parasitic capacitance of the TFT matrix is determined by the parasitic capacitance C _GS between the gate and the source and the drain capacitance
Represented by the parasitic capacitance C _DS between the source potential V _S of the potential or source of the display electrodes, scan bus lines S adjacent selected as scan bus lines S _2n-2 in the scanning direction
_{According to} the voltage changes ΔV _G and ΔV _D of _2n , Receives the voltage fluctuation ΔV _S represented by: Accordingly, for the voltage fluctuation ΔV _S (≡ΔV) immediately after writing at τ _A , ΔV _G = −Va ΔV _D = −Vr For the voltage fluctuation ΔV _S at τ _M (≡ΔV ′), ΔV _G = + Vr ΔV _D = + Va, the difference between the display electrode potential at the time of writing and the display electrode potential at τ _M is Becomes

On the other hand, the display electrode potential at the time of writing is the reference voltage Vr,
Since this is equal to the gate voltage at τ _M , the value of the equation indicates the bias voltage of the source relative to the gate at τ _M. Therefore, if this is a positive voltage or 0V, TFT keeps the off state, so that the leakage current of the TFT in the tau _M is suppressed. Since Va> Vr, the expression is 0 or positive if C _DS ≧ C _GS .

Therefore, when writing to the previous line S _2n-2 at the time τ _M , the bias voltage of the gate with respect to the source of the TFT of the line S _2n-1 is not positive, so that the TFT of the line is kept off and the liquid crystal cell Prevents voltage leakage.

The liquid crystal cell voltage LC _2n-1 , _m decreases by ΔV ′ while the address voltage Va is applied to the next line S _2n , but since the time is short, the effective value and the fluctuation are very small, The effect on is greatly reduced compared to the past.

By thus controlling the value of the parasitic capacitance C _DS and C _GS of the TFT matrix, it is possible to prevent variation of the liquid crystal cell voltage by suppressing the leakage current of the half-selected time of the TFT in the interlace drive.

〔Example〕

3 (a), a diagram showing an example of (b) the present invention, showing the control of the C _DS and C _GS by the layout of the units of the gate connection type opposite matrix.

In the present embodiment, a redundant TFT configuration in which two FTFs are provided in one pixel is employed, but d in FIG.
And the scan bus line S _2n to which it is connected, and indicates the ratio d / p between d and the pitch p between the balances.
The magnitude of C _DS and C _GS changes.

Pixel area is 0.125 × 0.375mm ² , TFT channel area is 5
The relationship between the parasitic capacitance ratio C _DS / C _GS and d / p in the case of × 40 μm ² is shown in FIG. As shown in the figure, d / p is 0.7 or more and C
Satisfies the condition of _DS ≧ C _GS, prevents the leakage of the liquid crystal cell voltage during the writing of the previous line.

FIGS. 4 (a) and 4 (b) show another embodiment of the present invention, in which C _DS / (C _GS + C _DS ) is controlled by changing the gap between the display electrode 38 and the adjacent wiring. It is.

A gap d ₁ between adjacent wires of the gate at the same potential, by varying the gap d ₂ between the adjacent wire of the drain at the same potential,
The value of C _DS / (C _GS + C _DS ) can be controlled.

As the proximity wiring having the same potential as the gate, there are the scan bus line _S2n-1 and the connection line 21 connected to the gate. The adjacent wiring having the same potential as the drain is the scan bus line _S2n and the connection line 22 to which the drain is connected.

Reduce the C _GS by increasing the d ₁ as shown, it can be increased C _DS by decreasing the d _2.

Shows the results of varying the d ₁ and d ₂ as 10μm constant in FIG. (B). There is a limit in reducing the gap between the display electrode and the adjacent wiring.Therefore, when d ₂ is fixed at 10 μm, d ₁ is 13
By the above [mu] m, it can meet the C _DS ≧ C _GS. Therefore, also in this embodiment, it is possible to prevent leakage of the liquid crystal cell voltage at the time of writing the previous line.

As mentioned above, also possible to control the value of C _DS and C _GS by any of the methods of one embodiment and other embodiments, the case of performing the interlaced driving of the foregoing, when the half-selected TFT
Leakage can be prevented.

〔The invention's effect〕

As described above, according to the present invention, when the active matrix display device having the gate connection type opposing matrix panel configuration is interlaced, the half-selection
It is possible to realize a low-priced display device without deterioration in display quality due to TFT leakage.

[Brief description of the drawings]

FIG. 1 is an explanatory view of the configuration of the present invention, FIG. 2 is an explanatory view of the principle of the present invention, FIG. 3 is an explanatory view of one embodiment of the present invention, FIG. 4 is an explanatory view of another embodiment of the present invention, FIG. Is an equivalent circuit diagram of the gate connection type opposing matrix panel proposed earlier, FIG. 6 is an exploded perspective view of the panel, and FIG. 7 is a problem of the prior art. In the figure, 21 and 22 are connection lines, D is a drain, G is a gate, S is a source, C _GS , C _DS , C _LC , C _gs , C _gb , C _ds , C _db are parasitic capacitances, S _2n−1 , S _2n , S _{2n + 1} ... Indicate scan bus lines.

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Tomotaka Matsumoto 1015 Uedanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture, Fujitsu Limited (72) Inventor Tsutomu Tanaka 1015 Uedanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Fujitsu Limited ( 56) References JP-A-63-68884 (JP, A) JP-A-64-82558 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) G02F 1/136 500

Claims (3)

(57) [Claims] A plurality of display electrodes (38) arranged in a matrix and a thin film transistor (31) corresponding to the display electrodes.
And a plurality of scan bus lines (S) arranged corresponding to the rows of the matrix. The gate (32) of each thin film transistor is connected to the scan bus line corresponding to the row to which the thin film transistor belongs, and the drain ( 34), in a gate connection type opposed matrix type active matrix display configuration in which the scan bus lines adjacent to each other in the scanning direction are connected, a parasitic capacitance C _GS between each display electrode and a corresponding scan bus line; active matrix display device parasitic capacitance C _DS between the scan bus lines adjacent to the electrode in the scanning direction and having a relationship of C _GS ≦ C _DS. 2. The active matrix display device according to claim 1, wherein a distance between the thin film transistor and a corresponding scan bus line is smaller than a distance between the thin film transistor and a scan bus line adjacent in a scanning direction. 3. The distance between the display electrode and a corresponding scan bus line and the distance between the corresponding scan bus line lead line and the scan electrode adjacent to the display electrode in the scanning direction are different from each other. 2. The active matrix display device according to claim 1, wherein the distance is larger than the distance between the adjacent scan bus lines and the distance between the adjacent scan bus lines.