JP2808781B2 - Image defect correction device for solid-state imaging device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image defect correction device for a solid-state imaging device suitable for being applied to a solid-state imaging device.

[Summary of the Invention]

An image defect correction device for a solid-state imaging device according to the present invention includes an iris control unit that automatically closes an iris for a predetermined period when power is turned on, and an output signal output from each pixel of the solid-state imaging device with the iris closed. Comparing the level with a predetermined level, comparing means, based on the comparison result of the comparing means, position data generating means for generating position data indicating the position of a pixel outputting a signal of a unique level, and the position data A storage unit for storing position data output from the generation unit, and an output signal to be output from a pixel at a position indicated by the position data read from the storage unit at the time of imaging by interpolation from output signals of other pixels An interpolating means for generating the output signal of each pixel and an output signal of the interpolating means based on an output signal of the position data generating means. When the photographer performs photographing using the solid-state imaging device according to the present invention, the iris is automatically closed when the power is turned on, and an image defect called a white defect of the solid-state imaging device is provided. The pixel position of is detected, and the output signal to be output from the pixel of the image defect is interpolated by the output signal from another pixel, so that the operation and consideration for the white defect detection by the photographer become unnecessary, Correction of the white flaw is automatically performed.

[Conventional technology]

Of the pixels of the solid-state imaging device, pixels that do not operate normally due to lattice defects or the like are generally referred to as flaws. In addition, so-called white scratches are referred to as so-called white scratches, and scratches in which the scratched pixel produces a higher voltage than other normal pixels, and so-called black scratches in which the scratched pixel is another normal pixel. There is a flaw in which the voltage is small or almost non-existent. Figure 6 is the solid-state imaging devices r when closing the iris of the so-called 3CCD television cameras, g, b and red output from them, green and blue video signals V _r, V _g, shows a V _b ing. As is clear from FIG. 6, since the solid-state imaging devices g and b shown in FIGS. 6C and 6E have no damage, the levels of the video signals V _g and V _b from the solid-state imaging devices g and b are As shown in FIGS. 6D and 6F, all levels are at the time of no light quantity. On the other hand, the solid-state imaging device r shown in FIG. 6A has a white flaw at a position indicated by a solid line arrow. Therefore, as shown in FIG. 6B, the video signal Vr from the solid-state image pickup device r has the position of the video signal Vr corresponding to the pixel indicated by the solid arrow in FIG. Is at a high level.

FIG. 7 uses a 3CCD type television camera in the same manner as FIG. 6, and uses, for example, a white diffuser (illuminated from the opposite side of the imaging direction by illumination, hereinafter referred to as the same). The figure shows each solid-state imaging device r, g, b when projected, and red, green, and blue video signals Vr, Vg, Vb output therefrom. As is clear from FIG. 7, FIG.
Since the solid-state imaging devices g and b shown in FIGS. 7 and 8 have no scratches, the level of the imaging signals Vg and Vb from the solid-state imaging devices
As shown in FIGS. D and F, this is a level at which light of uniform brightness is incident on the entire surface of each of the solid-state imaging devices g and b. On the other hand, the solid-state imaging device r shown in FIG. 7A has a black flaw at the position indicated by the solid arrow. Therefore, as shown in FIG. 7B, the video signal Vr from the solid-state imaging device r has the same brightness as that of FIG. The position of the video signal Vr corresponding to the pixel indicated by the solid arrow in A becomes substantially zero level.

A video signal from a television camera incorporating the solid-state imaging device having the white and black flaws described with reference to FIGS. 6 and 7 is supplied to a monitor receiver and displayed on the monitor screen. Then, when the iris of the television camera is closed, a white flaw appears on the monitor screen. When, for example, a white diffuser is projected by the television camera, a black defect is projected on the monitor screen.

It is almost impossible to completely prevent the occurrence of white and black flaws in the solid-state image sensor at the manufacturing stage as described above. Even a solid-state image sensor that has no white or black flaws in the manufacturing stage may be incorporated into a housing and generate white or black flaws during use as a television camera.

Therefore, conventionally, the solid-state imaging device alone detects a flaw, further detects the position of the detected flaw in the solid-state imaging device, writes the position (address) in a ROM, and When the ROM is incorporated in the housing of the imaging device and used as a television camera, the pixels of the solid-state imaging device indicated by the address of the ROM are interpolated with data of other normal pixels and output. I was

[Problems to be solved by the invention]

By the way, in the above-described method in which the solid-state imaging device is inspected by itself and the address of the defective pixel is written in the ROM, the solid-state imaging device and the ROM must always be completely managed as a pair.

In addition, when the solid-state imaging device and its ROM are incorporated in the housing of the imaging device and a new scratch is generated after passing over to the user as a television camera, the user should return the device and return it from the housing again. The solid-state imaging device and the ROM are removed, the solid-state imaging device is inspected, and a defective pixel and its address are detected. If the ROM is a so-called one-time ROM, a new ROM is prepared. If the ROM is an EPROM, all data are erased, and then addresses of all detected defective pixels are written. Then, the solid-state imaging device and the ROM that forms a pair with the solid-state imaging device are incorporated into the housing again and returned to the user, which is very troublesome.

In view of such a point, the present invention intends to propose an image defect correction device for a solid-state imaging device that can automatically interpolate a white defect generated in the solid-state imaging device at any time even if the solid-state imaging device is damaged. It is.

[Means for solving the problem]

According to the present invention, an iris control unit that automatically closes an iris for a predetermined period when the power is turned on, and compares a level of an output signal output from each pixel of the solid-state imaging device with the iris closed with a predetermined level. A comparing unit, a position data generating unit that generates position data indicating a position of a pixel that outputs a signal of a unique level based on a comparison result of the comparing unit, and a position data output from the position data generating unit. Storage means for storing, interpolation means for generating an output signal to be output from a pixel at a position indicated by the position data read from the storage means at the time of imaging from output signals of other pixels by interpolation, and position data generation A solid-state imaging device having switching means for selectively outputting the output signal of each pixel and the output signal of the interpolation means based on the output signal of the means. It is a correction device.

[Action]

According to the present invention, under the control of the iris control means, the iris is automatically closed for a predetermined period when the power is turned on, and the output output from each pixel of the solid-state imaging device with the iris closed by the comparison means The level of the signal is compared with a predetermined level, and based on the comparison result of the comparing means, position data generating means generates position data indicating the position of a pixel outputting a signal of a unique level, and the storage means The position data output from the position data generating means is stored, and the output signal to be output from the pixel at the position indicated by the position data read from the storage means at the time of imaging is interpolated by the interpolation means. The output signal is generated by interpolation from the output signal, and the output signal of each pixel is output by the switching means based on the output signal of the interpolation means and the position data generation means. If, selectively outputs the output signal of the interpolation means.

〔Example〕

Hereinafter, an embodiment of the present invention will be described in detail with reference to FIG.

FIG. 1 shows a part of a solid-state imaging device according to the present invention and an image defect correction device thereof. Although FIG. 1 will be described below, first, description will be given of three modes and a control system which are prerequisites of the solid-state imaging device including the image defect correction device according to the present invention, and then each component will be described.

The solid-state imaging device provided with the image defect correction device according to the present invention has three modes: normal imaging, imaging for detecting a defective pixel, and designation of a defective pixel (performed by a user). A correction circuit system having a function of correcting a defective pixel operates. In addition, there is a self-diagnosis function for automatically detecting a defective pixel during a period of one frame from when the power of the solid-state imaging device is turned on. Selection of the above three modes
This is performed by the user, but when the imaging mode for detecting the defective pixel and the designation mode of the defective pixel are not selected, the mode of the solid-state imaging device is always after the self-diagnosis at power-on. The normal imaging mode is set.

Next, the control system will be described. Among the control systems, the control pulse generator (21), RAM controller (22), microcomputer (23), RAM (2
5) There are an EEPROM (24), a display unit (28), and an operation unit (29).

The EEPROM (24) stores in advance data such as the address of a flaw of the solid-state imaging device and data such as white flaw or black flaw, which have been inspected before reaching the user's hand. A microcomputer (23) having a ROM and a RAM performs normal imaging, imaging for detecting defective pixels, and imaging based on a mode selection signal from the operation unit (29) and data stored in the EEPROM (24). Control is performed on the control pulse generator (21) so that self-diagnosis is performed at the time of switching between three modes for designating a defective pixel and power-on. The control pulse generator (21) is a microcomputer (2
Under the control of 3), various control signals are generated based on address data from a line counter (19) and a cell counter (20), which will be described later.

RAM controller (22)
3) The RAM (25) is controlled by the control, and when the power is turned on,
The storage contents of the EEPROM (24) are stored, new defective pixel data is stored in the RAM (25), and the data is updated. The above-described mode switching and the like are performed by the user operating the operation unit (29) according to the display on the display unit (28).

Next, each unit will be described in order of the power-on mode and the three modes described above. The order of the description must be from the self-diagnosis at the time of power-on. However, since the imaging mode for detecting a defective pixel is the same as the circuit used and the operation thereof, the description will be omitted. Will be described in the mode for performing

First, the case of the normal imaging mode will be described.
(1) is an imaging optical system including an iris, a driving unit for driving the iris by a driving signal CP from a control pulse generator (21), a lens, a filter, and the like (all of which are not shown). (2)
Reference numeral denotes an imaging unit. An imaging optical system (1) forms a subject image in which imaging light is separated into three primary color components of red (R), green (G), and blue (B) on an imaging surface. It is composed of two solid-state image sensors (CCD etc.) Next, the driving of the imaging unit (2) will be described.

(5a) is a sync generator which generates a reference horizontal synchronization signal and a reference vertical synchronization signal based on the reference clock from the clock generation circuit (4). (5b) is a timing pulse generator which generates horizontal and vertical transfer pulses synchronized with the reference horizontal synchronization signal and reference vertical synchronization signal from the sync generator (5a). A drive circuit (3) drives each solid-state imaging device of the imaging unit (2) based on horizontal and vertical transfer pulses from the timing pulse generator (5b).

Returning to the imaging unit (2), the description will be continued. Each of the imaged video signals R, G, B from the imaging unit (2) is supplied to an A / D converter (8) through a preamplifier (6) and a video amplifier (7) for white balance adjustment, respectively. The A / D converter (8) converts each of the captured video signals R, G, and B into a digital captured video signal (hereinafter, referred to as a digital video signal). Each digital video signal R, G, B from the A / D converter (8) is supplied to a delay unit (9), (10), (11) composed of a CCD or the like, and these delay units (9) , (10), and (11) clock generation circuit (4)
After a predetermined time delay based on the clock pulse from the output terminals T ₀ , T ₁ , T ₂ through the switches SW ₂ , SW ₃ , SW ₄
And fed to a high pass filter (16) to be described later via the switch SW _5, SW _10. Incidentally, the opening and closing of the switches SW ₂ to SW ₄ is controlled by a control signal SCP from the control pulse generator (21). On the other hand, the digital video signal R from the A / D converter (8), G, B are supplied to the AND circuit A ₁ via the switch SW ₁ is switched by the R / G / B signal from the control pulse generator (21) is, from the aND circuit a ₁ in the control pulse generator (21), the power save signal COMPEN ANDed to be active only when the interpolation is taken, is supplied to the later-described interpolation circuit (12).

The interpolation circuit (12) is activated when the clock enable signal CKEN generated by the control pulse generator (21) is activated based on the address data of the RAM (25) in which the contents of the EEPROM (24) are stored at power-on. The pixel data at the upper left, right above, upper right, left, and right addresses of the defective pixel is fetched, and the fetched pixel data is supplied to a | X-Y | arithmetic unit (13) and a multiplexer (15) described later. The | X−Y | computing unit obtains the absolute value of the difference of each pixel data from the interpolation circuit (12),
4) to supply. The comparator (14) compares each difference signal from the | X−Y | arithmetic unit and supplies the comparison result signal to the multiplexer (15). The multiplexer (15)
Among the pixel data from the interpolation circuit (12), the pixel data corresponding to the comparison result signal from the comparator (14) is used as the interpolation pixel data of the defective pixel data by the switches SW ₂ , SW ₃ ,
Supply to SW ₄ . These switches SW ₂ , SW ₃ and SW ₄ are switching signals SCP from the control pulse generator (21).
The video signal in which the defective pixel has been corrected is switched by the output terminals T ₀ , T ₁ , T _{2 and the} switch SW _5.
And through the switch SW _10, it is supplied to the high-pass filter (16) to be described later.

Next, an imaging mode for detecting a defective pixel will be described. The mode of the image for detecting the defective pixel is, when the power is turned on to the solid-state imaging device, and when the user supplies a video signal from the solid-state imaging device to the monitor, for example, and the image displayed on the monitor. When a flaw is found inside, the operation unit (29) is operated according to the display on the display unit (28) to select an imaging mode for detecting a defective pixel. In this case, the detection is first performed from the detection of a white flaw. And, in any case described above, by controlling the changeover switch changeover signal HPFSELECT of the switch SW ₅ from the control pulse generator (21), the video signals from three pieces of solid-state imaging device R, G, one of B Is selected. still,
This switch switching signal HPFSELECT may be, for example, an input from a user. Then, the iris drive signal CP from the control pulse generator (21) is supplied to iris drive means (not shown) of the imaging optical system (1), and the iris is closed and the control pulse generator (21) black / white defect Generates switching signal B / W. It is generally known that scars generated after reaching the user's hand are almost white scratches. In the self-diagnosis mode when the power is turned on, the black defect is not detected.In the imaging mode for detecting the defective pixel, the detection is performed after the iris is closed, and when the white defect cannot be detected, Display (2
Through 8), the user is instructed to project, for example, a white diffuser illuminated by illumination light, and a black flaw is also detected. Now, the high-pass filter (16), clip circuit (17), and peak hold circuit (18) used in the above-described mode will be described. First, the high-pass filter (16) will be described.

The video signal in which the defective pixel portion previously stored in the EEPROM (24) is corrected is supplied when the power is turned on and the operation unit (29)
When the imaging mode for defect detection is selected by the user, the control pulse generator (21) supplied from the control pulse generator (21), for example, becomes active for one frame period under the control of the microcomputer (23). the detection enable signal HPFEN, it is supplied to the high-pass filter (16) through the switch SW ₁₀ is turned on in the meantime. The high-pass filter (16) is a digital filter including three D-type flip-flops (16a), (16b) and (16c) and two adders (16d) and (16e), and is a Laplacian filter in the horizontal direction.

The digital video signal supplied to the data input terminal D of the D-type flip-flop (16a) of the high-pass filter (16) is output from its non-inverting output terminal Q, and is output to the next-stage D-type flip-flop (hereinafter referred to as flip-flop). Is supplied to the data input terminal D of (16b), output from the non-inverted output terminal Q, and further supplied to the data input terminal of the next stage. On the other hand, flip-flops (16
The digital video signal from the inverted output terminal of a) is supplied to the adder (16d) and is added to the digital video signal from the inverted output terminal of the flip-flop (16c), and the output signal is supplied to the adder (16e). The output signal from the supplied adder (16d) and the flip-flop (1
The digital video signal from the inverted output terminal of 6b) is added and filtered with a characteristic of -z ^-1 + 2z ⁰ -z ¹ , that is, a characteristic such that a frequency corresponding to a defective pixel in the digital video signal has a peak. Thus, a digital video signal from which the DC and low frequency components have been removed is obtained.

Next, the flip circuit (17) will be described. The digital video signal from the high-pass filter (16) is supplied to a clip circuit (17). Clipping circuit (17) is a flip-flop (17a), a connection between clipper (17b) and these switches SW supplies instead enters the non-inverting and inverting outputs of the flip-flop (17a) to the clipper (17b) ₆
Consists of Digital video signal supplied to the flip-flop (17a) is, when the black / white defect switching signal B / W from the control pulse generator (21) for example, "1", the movable contact is flip-flop of the switch SW ₆ ( 17a)
Is switched to the fixed contact connected to the non-inverted output terminal Q. Digital video signal supplied to the clipper (17b) via the switch SW ₆ is supplied to a peak hold circuit which will be described later after being clipped (18).

Next, the line counter (19) and the cell counter (20), which are indispensable for describing the peak hold circuit (18), will be described with reference to the peak hold circuit (18). The 10-bit synchronous cell counter (20) counts the clock from the clock generation circuit (4) after the reference horizontal synchronization signal from the sync generator (5a) is supplied to its reset terminal and reset, The counted value is supplied to a peak hold circuit (18) and a control pulse generator (21) described later. The count value of the cell counter (20) corresponds to a horizontal address of the solid-state imaging device. Then, a carry pulse is supplied to the line counter (19) when one horizontal period of the reference horizontal synchronization signal is counted. The 9-bit synchronous line counter (19), after the reference vertical synchronizing signal from the sync generator (5a) is supplied to its reset terminal and reset, outputs the clock from the clock generating circuit (4) to the cell counter (19). The count is performed for each carry pulse from 20), and this count value is supplied to a peak hold circuit (18) and a control pulse generator (21) described later. The count value of the line counter (19) corresponds to the vertical address of the solid-state imaging device.

The description will return to the peak hold circuit (18).
A peak hold circuit (18) stores a comparator (18a) for comparing current and past digital video signals, a flip-flop (18b) for storing absolute values of past digital video signals, and stores a horizontal address of a defective pixel. 10 bits of flip-flops (18 d), composed of a flip-flop (18c) and the switch SW _7, SW _8, SW ₉ of 9 bits for storing the vertical address of the defective pixel.

Digital video signal from the clip circuit (17) is normally, i.e., when the peak level by the defective pixel is not detected, since the switches SW _7, SW _8, SW ₉ is made with the switching state shown in FIG., A comparator The signal is supplied to the non-inverting input terminal of (18a) and the input terminal D of the flip-flop (18b). Therefore, the present digital video signal is compared with the past digital video signal. And
When the comparator (18a) detects a peak level, the output signal of the comparator (18a), each switch SW _7, SW _8, SW ₉ is switched respectively to the switching state opposite to the switching state shown in FIG. Thus, the contents indicating the level of the register of the flip-flop (18b) and the contents of the horizontal address and the vertical address of each register of the flip-flops (18d) and (18c) are rewritten. The rewritten data from the flip-flops (18b), (18d), and (18c) are supplied to the microcomputer (23) through a bus (consisting of an address bus, a data bus, and a control bus) Bu. It is stored as new data in the RAM (25), and
Stored as a backup in EPROM (24). The flip-flops (18b), (18c), and (18d) are reset by a reset signal PEAKCLR supplied from the control pulse generator (21) when the power is turned on.

Next, the iris of the solid-state imaging device is closed, or a video signal obtained by imaging, for example, a white diffusion plate (assumed to be illuminated by illumination from a direction opposite to the imaging direction) is supplied to a monitor receiver. A method of projecting the video signal on the monitor screen and newly registering a position of a flaw other than a flaw registered in advance by the solid-state imaging device, that is, a mode of designating a defective pixel will be described. .

Note that the registration of the position of the defective pixel means that, for example, if the solid-state imaging device cannot detect the solid-state imaging device in the self-diagnosis mode or the imaging mode for detecting the defective pixel, the solid-state imaging device Is supplied to the monitor, and the user views the image projected on the monitor screen (a black image when the iris is closed or a white image when the white diffuser is projected), For example, a cross marker projected at an arbitrary position on the monitor screen is operated by a marker controller (27) of the solid-state imaging device, which will be described later, and the position of the cross marker is visually determined as a new scratch position. At the same time, the position is stored in the RAM (25) and the EEPROM (24) of the solid-state imaging device as the position of the defective pixel. Also, this mode allows the user to select a video signal before or after performing interpolation processing based on defective pixel data already stored in the EEPROM (24) or the RAM (25) before selecting this mode. Has been established. Hereinafter, each circuit related to the above-described mode of the defective pixel will be described.

(27) is a marker controller having, for example, a cursor key, and when the user presses the cursor key, the address data indicating the position of the cursor increases or decreases during that time. Then, the address data is always supplied to a marker generator (26) described later. The marker generator (26) converts a cross shape having a width of one pixel, for example, stored in an internal ROM, for example, into a line counter (19) and a line counter through the address data from the marker controller (27) and the bus Bu. only when the address data from the cell counter (20) coincide, the output terminal T ₀ through T through the switch SW _2, SW _3, SW ₄
Supply ₂ Then, when the user moves the cross marker to the position of the wound to be newly registered with the cursor key, and when the cross marker is at the position of the wound, for example, presses a button, the marker controller (27) transmits the cross marker to the wound marker. The address data of the current position and the write control signal are transferred to the RAM through the marker generator (26) and the bus Bu.
(25) and the microcomputer (23).
Further, the user makes a selection between a white flaw and a black flaw by using a button or the like. The microcomputer (23) controls a RAM controller (22) to be described later through the bus Bu. Thus, the address data from the marker controller (27) and the contents of the defective pixel (whether a white defect is a black defect) are written into the RAM (25).

Next, referring to the flowchart of FIG.
An imaging mode for detecting a defective pixel out of the two modes, particularly a case where the user directly designates some, will be briefly described.

First, in step ST-1, it is determined whether or not there is an input from the user indicating the occurrence of a scratch, that is, an input for selecting an imaging mode for detecting a defective pixel. The process moves to ST-2, and if NO, the input is held, that is, a normal imaging mode is set.

In the next step ST-2, the input of the channel, that is,
It is determined whether or not the digital video signals R, G, B from the three image sensors have been selected, and if YES, the next step ST-
3 and if NO, the input is held again in step ST-2. The channel input in step ST-2 may be input by the user, or may be automatically selected in the order of digital video signal R, digital video signal G, and digital video signal B. .

In the next step ST-3, it is determined whether or not there is a white flaw, and YE
If S, the process proceeds to the next step ST-4, and if NO, the process proceeds to the next step ST-5.

In the next step ST-4, the iris is closed. Then, the process proceeds to step ST-7.

In step ST-5, it is determined whether or not there is a black defect. If YES, the process proceeds to the next step ST-6. If NO, the process returns to step ST-3 to determine whether there is a white defect. . The determination of white or black flaws may be input by the user, or may be automatically detected from the output state of the high-pass filter (16).

In the next step ST-6, an instruction to display a white pattern is displayed to the user on the display section (28) described with reference to FIG. Then, the next step ST-
Move to 7.

In step ST-7, the measurement of the flaw is performed. And
The process proceeds to the next step ST-8.

In step ST-8, it is determined whether or not scanning for one frame has been completed based on the address data from the line counter (19) and the cell counter (20) described with reference to FIG. Moves to step ST-9 of N
If O, the process proceeds to step ST-7, and the measurement of the flaw is continued.

In the next step ST-9, the RAM (25) and the EEPROM (2
4) Write the scratch data. And the next step ST
Move to -10. In the next step ST-10, a confirmation is made to the user on the display unit (28) described with reference to FIG.
Move to 1.

Next, referring to the flowchart of FIG.
Of the two modes, an imaging mode for detecting a defective pixel will be briefly described, in particular, in a case where direct designation by a user is not required except for the designation of this mode, that is, the input of occurrence of a flaw.

First, in step ST-1, it is determined whether or not there is an input from the user indicating the occurrence of a scratch, that is, an input for selecting an imaging mode for detecting a defective pixel. The process proceeds to ST-2, and if NO, the input is held, that is, a normal imaging mode is set.

In step ST-2, it is determined whether or not the flaw detection of the digital video signal R has been completed. If YES, the process proceeds to step ST-4, and if NO, the process proceeds to step ST-3.

In step ST-3, the switch changeover signal HPFSELECT from the control pulse generator described for the first view (21) is supplied to the switch SW _5, the digital video signal R is selected. Then, the process proceeds to the next Step ST-8.

In step ST-4, it is determined whether or not the flaw detection of the digital video signal G has been completed. If YES, the process proceeds to step ST-6, and if NO, the process proceeds to step ST-5.

In step ST-5, switching signal HPFSELECT from the control pulse generator described for the first view (21) is supplied to the switch SW _5, the digital video signal G is selected. Then, the process proceeds to the next Step ST-8.

In step ST-6, it is determined whether or not the flaw detection of the digital video signal B has been completed.
If so, the process proceeds to step ST-7.

In step ST-7, a switch switching signal from the control pulse generator (21) described with reference to FIG.
HPFSELECT is supplied to the switch SW _5, the digital video signal B is selected. Then, the process proceeds to the next Step ST-8.

In step ST-8, the iris is closed. Then, the process proceeds to step ST-9.

In step ST-9, the measurement of the flaw is performed. Then, control goes to the next step ST-10.

In step ST-10, it is determined whether or not scanning for one frame has been completed based on the address data from the line counter (19) and the cell counter (20) described with reference to FIG. Move to step ST-11 of N
If it is O, the process proceeds to step ST-7, and the measurement of the flaw is continued.

In step ST-11, it is determined whether or not a flaw has been detected. If YES, the process proceeds to step ST-12, and if NO, the process proceeds to step ST-13.

In step ST-12, the RAM (2
5) Write the scratch data to the EEPROM (24). Then, the process proceeds to step ST-13.

In step ST-13, it is determined whether or not a black flaw has been detected. If YES, the process proceeds to step ST-2, and if NO, the process proceeds to step ST-14.

In step ST-14, an instruction is displayed to the user on the display unit (28) described with reference to FIG. 1 to project a white pattern. Then, the process proceeds to step ST-9 again, and the detection of a black flaw is performed.

Next, referring to the flowchart of FIG.
The self-diagnosis mode at power-on of the two modes will be briefly described. In this self-diagnosis mode, for example, a description will be given of the detection of a white flaw capable of automatically performing flaw detection when the power is turned on.

First, in step ST-1, the solid-state imaging device is turned on. Then, the process proceeds to the next step ST-2.

In step ST-2, it is determined whether or not the flaw detection of the digital video signal R has been completed. If YES, the process proceeds to step ST-4, and if NO, the process proceeds to step ST-3.

In step ST-3, the switch changeover signal HPFSELECT from the control pulse generator described for the first view (21) is supplied to the switch SW _5, the digital video signal R is selected. Then, the process proceeds to the next Step ST-8.

In step ST-4, it is determined whether or not the flaw detection of the digital video signal G has been completed. If YES, the process proceeds to step ST-6, and if NO, the process proceeds to step ST-5.

In step ST-5, switching signal HPFSELECT from the control pulse generator described for the first view (21) is supplied to the switch SW _5, the digital video signal G is selected. Then, control goes to the next step ST-8.

In step ST-6, it is determined whether or not the flaw detection of the digital video signal B has been completed. If YES, the process proceeds to the final step ST-13, and if NO, the process proceeds to the next step ST-7.

In step ST-7, switching signal HPFSELECT from the control pulse generator described for the first view (21) is supplied to the switch SW _5, the digital video signal B is selected. Then, the process proceeds to the next Step ST-8.

In step ST-8, the iris is closed. Then, the process proceeds to step ST-9.

In step ST-9, the measurement of the flaw is performed. Then, the process proceeds to the next Step ST-10.

In step ST-10, it is determined whether scanning for one frame has been completed based on the address data from the line counter (19) and the cell counter (20) described with reference to FIG. Move to step ST-11 of N
If it is O, the process returns to step ST-9 to read the measurement of the flaw.

In step ST-11, it is determined whether a flaw has been detected,
If YES, the process proceeds to step ST-12. If NO, the process proceeds to step ST-2 again.

In step ST-12, the data of the detected flaw is written into the EEPROM (24) described with reference to FIG. Then, the process returns to step ST-2.

In the final step ST-13, the RA described in FIG.
Load EEPROM (24) data into M (25) and finish.

Next, with reference to the flowchart of FIG. 5, a mode of designating a defective pixel among the above three modes will be briefly described.

First, in step ST-1, when the user designates this mode from the operation unit (29) described with reference to FIG. 1, an arbitrary position on the screen of the monitor to which the output video signal of the solid-state imaging device is supplied. Next, a cross marker generated by the marker generator (26) described with reference to FIG. 1 is projected. Then, the process proceeds to the next step ST-2.

In step ST-2, the user operates the marker controller (27) described with reference to FIG. 1 to determine whether there is a position command supplied from the marker controller (27), that is, whether or not there is address data.
If YES, the process proceeds to the next step ST-3, and if NO, the input is held.

In step ST-3, every time the user operates the marker controller (27), the address of the cross marker is updated by the marker generator (26), and the cross marker moves on the monitor screen. Then, control goes to the next step ST-4.

In step ST-4, for example, when the user presses a button or the like after adjusting the position of the cross marker to the position of the wound found on the monitor screen, the address data supplied from the marker controller (27) at that time is stored. It has been made to be. Then, it is determined whether or not the button has been pressed. If YES, the process proceeds to step ST-5, and N
If it is O, the process returns to step ST-2.

In step ST-5, the address data supplied from the marker controller (27) is used as the defective pixel data in the RAM (25) and the EEPROM (2) described with reference to FIG.
4) is stored. Then, the process proceeds to the next Step ST-6.

In step ST-6, a message is displayed to the user on the display unit (28) described with reference to FIG. 1 as to whether or not the mode for specifying the defective pixel may be released. If the release is indicated through ()), the process ends as YES, and if NO, the process returns to step ST-1.

The solid-state imaging device equipped with the above-described image defect correction device has three modes. In a normal imaging mode, a defective pixel is interpolated based on data stored in the EEPROM (24) in advance. In the imaging mode for detecting defective pixels, not only is it very easy for the user to inspect the flaw before the solid-state imaging device passes, but also to add data to the data stored in the EEPROM (24) in advance. In particular, in a self-diagnosis mode at the time of power-on, which does not require an input from a user, detection of a defective pixel and its interpolation can be automatically performed at power-on. In the defective pixel designation mode, the data of the flaws visually found by the user is displayed.
Since the data can be stored in the EEPROM (24), for example, subtle white or black flaws can be interpolated.

In the description of FIG. 1, the image defect correction device of the solid-state imaging device may be inside or outside the solid-state imaging device.
Also, the microcomputer (23) is replaced with, for example, a personal computer,
It may be connected via −232C interface or EE
In that case, the PROM (24) may be a floppy disk, a magneto-optical disk, or the like when an external storage device is used.
Further, the above-described image defect correction device can be easily integrated into an IC.

〔The invention's effect〕

According to the present invention described above, the iris control means for automatically closing the iris for a predetermined period when the power is turned on, and the output signal level output from each pixel of the solid-state imaging device when the iris is closed is set to a predetermined level. A position data generating unit that generates position data indicating a position of a pixel that outputs a signal of a unique level based on a comparison result of the comparing unit, and a position data output unit that outputs the position data. Storage means for storing position data, and, at the time of imaging, interpolation means for generating an output signal to be output from a pixel at a position indicated by the position data read from the storage means by interpolation from output signals of other pixels, A switching unit for selectively outputting an output signal of each pixel and an output signal of the interpolation unit based on an output signal of the position data generation unit; When a person performs photographing using the solid-state imaging device according to the present invention, the iris is automatically closed when the power is turned on, the pixel position of an image defect called a white defect of the solid-state imaging device is detected, and the pixel of the image defect is detected. Since the output signal to be output from is interpolated by the output signal from other pixels, there is no need for the photographer to perform any operation or consideration for detecting a white defect, and the solid-state imaging automatically corrects the white defect. An image defect correction device of the device can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.
3, 4, and 5 are flowcharts, FIG. 6 is a diagram showing a solid-state image sensor and a white defect, and FIG. 7 is a diagram showing a solid-state image sensor and a black defect. (2) is an imaging unit, (12) is an interpolation circuit, (13) is an | X−Y | computing unit, (14) is a comparator, (15) is a multiplexer, (16) is a high-pass filter, and (17) is a clipper. Circuit, (18) peak hold circuit, (19) line counter, (20) cell counter, (21) control pulse generator, (22) RAM controller, (23)
Is microcomputer, (24) is EEPROM, (25) is RA
M, SW ₂ , SW ₃ and SW ₄ are switches.

Claims (1)

(57) [Claims] An iris control means for automatically closing an iris for a predetermined period at the time of turning on a power supply, and controlling a level of an output signal output from each pixel of the solid-state imaging device with the iris closed to a predetermined level. Comparing means for comparing, position data generating means for generating position data indicating a position of a pixel outputting a signal of a unique level based on a comparison result of the comparing means; Storage means for storing position data, and interpolating means for generating an output signal to be output from a pixel at a position indicated by the position data read from the storage means at the time of imaging from an output signal of another pixel by interpolation Switching means for selectively outputting an output signal of each pixel and an output signal of the interpolation means based on an output signal of the position data generation means; An image defect correction device for a solid-state imaging device, comprising: