JP2806053B2 - Semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit,
In particular, a plurality of ECL circuits (Emit circuits) connected to the same high-potential-side power supply bus line of a bipolar semiconductor integrated circuit
ter Coupled Logic and output level equalization of a CML circuit (Current Mode Logic).

[0002]

2. Description of the Related Art In a bipolar semiconductor integrated circuit, a constant current control voltage (hereinafter referred to as VCS) input terminal 16 of a constant current source of an ECL circuit as shown in FIG.
A constant current (hereinafter referred to as ICS) of a constant current source circuit is controlled by supplying a VCS generated by a VCS generation circuit as shown in FIG. That is, ICS is determined by the potential difference between the constant potential power supply 12 and VCS, the base-emitter voltage of the transistor Q4, and the resistor R3.

On the other hand, the output level of the output terminal 13 is determined by the voltage determined by the ICS and the resistor R1, the potential of the high-potential power supply 11, and the voltage between the base and emitter of the transistor Q1 (hereinafter referred to as Vf). . At this time, in the conventional bipolar semiconductor integrated circuit, there is no correlation between the potential supply position of the bus line of the high potential side power supply 11 to which the plurality of ECL circuits are connected and the arrangement position of the VCS generation circuit that supplies VCS to the ECL circuit. (For example, the output part of the ECL gate array at National Semiconductor: THE ASPECT GATE ARRAY
DESIGNMANUAL (8-3, 8-12, 8-
14, 8-18)).

[0004]

In the conventional ECL circuit shown in FIG. 3A, the ICS flows from the high potential side power supply 11 to the constant potential side power supply 12 through the transistor Q4. If the rate is h,
The current of ICS / h is VC at the base of the transistor Q4.
It flows as the load current of the S generation circuit. When the VCS generation circuit supplies the VCS to a plurality of ECL circuits, the potential of the VCS becomes VCS due to the potential drop in the wiring due to the load current.
The closer to the generating circuit, the higher and the farther away, the lower.

On the other hand, since the ICS of the ECL circuit flows from the high-potential power supply 11 connected to the circuit to the constant-potential power supply 12, a plurality of ECL circuits are connected to the same high-potential power supply bus line. In this case, the potential drop of the wiring by ICS
As a result, the potential of the bus line of the high-potential-side power supply 11 increases as the position is closer to the potential supply position and decreases as the position increases.

In FIG. 3A, ICS is VC
The potential difference between S and the potential of the constant potential side power supply 12 and the resistance R3
The output level of the ECL circuit is determined by the voltage determined by the ICS and the resistor R1, the potential of the high-potential-side power supply 11, and the Vf of the transistor Q1.
Is determined by

Conventionally, VC connected to a large number of ECL circuits
Since the arrangement position of the S generating circuit and the potential supply position of the bus line of the high potential side power supply are determined without correlation, there is no correlation between the potential drop due to the VCS wiring and the potential drop due to the power supply bus line. Therefore, since the potential of the high-potential-side power supply 11 and the ICS vary depending on the position, the output level also varies depending on the location, and there is a disadvantage that the electrical characteristics of the circuit have a position dependence and are not uniform in the entire LSI.

For example, in an LSI such as an ECL gate array in which a large number of ECL output circuits are connected to the same power supply bus line, as shown in FIG. 4A, a VCS generation circuit 4b is connected to the circuit. The potential supply position 3 of the bus line 1 of the high-potential-side power supply is arranged, and the voltage drop due to the VCS wiring is set to about 20 mV, and the voltage drop due to the wiring of the power bus line 1 is set to about 30 mV. It is assumed that there is no rise in the potential of the constant potential side power supply.

At this time, the potential of the VCS and the potentials of the power supply bus lines depend on the position, as shown in FIG. 4B, and the potential difference between the VCS and the constant potential power supply 12 when there is no potential drop and potential rise due to wiring is shown. The voltage between the base and the emitter of the current supply transistor of the ECS circuit is 0.8 V.
Assuming V, the logic amplitude will vary by about 5% depending on the position. Therefore, the bus line 1 of the high potential side power supply is about 3
Considering the voltage drop of 0 mV, when the output amplitude of the ECL circuit is about 1 V, the 5% variation is about 50 m.
About 30m at high level depending on the position
A fluctuation of about 80 mV occurs at V and low levels.

[0010]

According to the present invention, there is provided a semiconductor integrated circuit comprising: a plurality of ECL circuits disposed on one main surface of a semiconductor chip; a plurality of high potential side power supply bus lines to which the ECL circuits are connected; A current control constant voltage generating circuit for generating a constant current control constant potential for driving a constant current of a constant current source of the plurality of ECL circuits; and a constant current control constant potential supply line for supplying the constant current control potential In the bipolar semiconductor integrated circuit having the above, a decrease in the output level of the ECL circuit due to a decrease in the potential of the high potential side power supply bus line is offset by a decrease in the potential of the constant current supply constant potential supply line. The arrangement position of the constant current generating constant voltage generating circuit of the constant current source is set near the potential supply position of the high potential side power supply bus line, and the constant current controlling constant voltage
The pressure generating circuit is arranged at a position where the ECL circuit sandwiches both sides.
A configuration that is.

[0011]

Next, the present invention will be described with reference to the drawings. FIG. 1A shows a first embodiment of the present invention, in which a plurality of ECL output circuits are connected to the same power supply bus line.
FIG. 1B shows the relationship between the potential supply positions of the bus lines of the high-potential-side power supply connected to the VCS generation circuit and the ECL circuit in the output section of the SI, and FIG. 3 shows the position dependence of the output level of the ECL circuit and the constant potential side power supply voltage.

The VCS generating circuit 4 is located at both ends of the bus line 1 of the high-potential-side power supply, and the bus line also supplies power at the same position 3. For this reason, the potential of VCS becomes highest near the VCS generation circuit 4 and becomes lowest at the center due to the potential drop due to the wiring. On the other hand, the potential of the bus line 1 of the high-potential-side power supply is similarly highest at both ends of the bus line due to the potential drop of the wiring, and is also low at the center. The voltage drop due to the VCS wiring is about 20 mV,
The voltage drop caused by the wiring of the power supply bus line 1 is about 30 m
Assuming that the potential of the constant-potential-side power supply connected to the ECL circuit does not increase for the sake of explanation, the logical amplitude is reduced by about 5% at the center compared to both ends of the bus line 1 of the high-potential-side power supply. The low level of the output will rise.

On the other hand, the high-potential power supply potential drops by about 30 mV at the center as compared with both ends of the bus line 1. Therefore, if the logic amplitude is 1 V, the high level drops by about 30 mV at the center compared with both ends of the bus line 1 of the high-potential power supply. The central portion only rises by about 20 mV from both ends of the bus line 1 of the high potential side power supply. Therefore,
Although the fluctuation due to the position of the high level does not change from the conventional case, the low level can be greatly reduced from 80 mV to 20 mV.

FIG. 2A shows a VC according to a second embodiment of the present invention.
FIG. 2B shows the relationship between the potential supply positions of the bus lines of the high potential side power supply connected to the S generation circuit and the ECL circuit.
This shows the VCS, the potential of the bus line, the output level of the ECL circuit, and the position dependence of the constant potential side power supply potential at this time (similar to the first embodiment, many ECL output circuits are connected to the same power supply bus line. LSI output unit is assumed). The potential of the bus line 1a of the high-potential-side power supply is supplied at two locations on the bus line, and the VCS generation circuit 4a is arranged at the same position as the potential supply position 3a.

Therefore, both the potential of the VCS and the potential of the bus line of the high potential side power supply are the highest at the bus line potential supply position 3a, and the lowest between them and at both ends of the bus line 1a. Therefore, when the output is at the low level, VC
The decrease in the logic amplitude due to the potential drop due to the S wiring and the rise in the potential of the bus line 1a cancel each other out, making it possible to reduce the position dependence of the output low level of the ECL circuit as compared with the related art. The same descent as in the first embodiment can be expected. In this embodiment, since the power supply potential supply position is closer to the ECL circuit than in the first embodiment, the potential drop is small and the position dependency of the output level is smaller.

[0016]

As described above, according to the present invention, a plurality of Es
By setting the potential supply position of the bus line of the high-potential-side power supply to which the CL circuit is connected and the connection position of the VCS generation circuit connected to the ECL circuit to the same position, the position dependence of the output low level of the ECL circuit There is an effect that can be reduced.

[Brief description of the drawings]

FIG. 1A is a layout diagram of a potential supply position of a high-potential-side power supply and a VCS generation circuit according to a first embodiment of the present invention, and FIG. 1B is a diagram showing position dependence of each potential. It is.

FIG. 2A is a layout diagram of a potential supply position of a high-potential-side power supply and a VCS generation circuit according to a second embodiment of the present invention, and FIG. 2B is a diagram showing position dependence of each potential. It is.

FIG. 3A is a circuit diagram of an ECL circuit generally used in a bipolar semiconductor integrated circuit;
FIG. 2B is a circuit diagram of a commonly used VCS generation circuit.

FIG. 4A is a layout diagram of a potential supply position of a conventional high-potential-side power supply and a VCS generation circuit, and FIG. 4B is a diagram showing position dependence of each potential.

[Explanation of symbols]

 1, 1a High-potential-side power supply bus line 2, 2a ECL circuit group 3, 3a High-potential-side power supply potential supply position 4, 4a VCS generation circuit 5 Chip outer periphery 6, 6a High-potential-side power supply bus line potential 7, 7a ECL circuit output High level 8, 8a ECL circuit output low level 9, 9a VCS potential 10 Constant potential side power supply bus line potential

Claims (1)

(57) [Claims] 1. A plurality of ECL circuits disposed on one main surface of a semiconductor chip, a plurality of high-potential-side power supply bus lines to which the ECL circuits are connected, and a constant current of a constant current source of the plurality of ECL circuits. A bipolar semiconductor integrated circuit having a constant voltage generating circuit for generating a constant current for generating a constant current for controlling the constant current, and a constant potential supply line for supplying a constant current for supplying the constant current controlling potential. A constant current generating constant voltage generating circuit for the constant current source of the ECL circuit so that a decrease in the output level of the ECL circuit due to a decrease in the potential of the potential side power supply bus line is offset by a decrease in the potential of the constant current controlling constant potential supply line. Is located near the potential supply position of the high potential side power supply bus line , and the constant current
In the control constant voltage generation circuit, the ECL circuit sandwiches both sides
A semiconductor integrated circuit which is arranged at a position .