JP2806052B2 - Track address demodulation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is used for a track address demodulation circuit of a magneto-optical disk drive for reading out information in real time.

[0002]

Conventionally, track address demodulation circuit, being played by detecting based several sectors correction code is added to the recorded track address on the disc to the marker attached to the track address portion Was.

[0003]

However, in such a conventional track address demodulation circuit, the marker detection may be erroneously performed, and if the marker detection is erroneous, reading out again may not be in time. .

The present invention solves the above problems,
An object of the present invention is to provide a track address demodulation circuit capable of accurately extracting a track address without erroneous detection of a synchronization signal.

[0005]

According to the present invention, there is provided a track address demodulation circuit having a storage means for storing a reproduced track address, wherein an edge component is obtained from a reproduction input signal of a track address of a biphase modulated serial signal. Edge detecting means for detecting and outputting an edge signal ;
And the edge component count is d to j
(D is a value obtained by subtracting 2 or 3 from N, and j is 2 or 3
If the value is between the counts of
One of the logic values is output as demodulation data, and the count
Is present between d and j, the demodulated data and
And outputs the other logical value.
Is a logic level detection means for outputting a clock signal when an edge signal is input when I is equal to or greater than I (I is j + 1), and the interval between the output clock signals is a first predetermined number a lock detection unit that outputs a lock signal when p continues, and outputs an unlock signal when the interval is equal to or greater than the count number I + 1 and continues for a second predetermined number q;
The logic level when the lock signal this is outputted
Detects that a synchronization pattern is output from the detection means.
And a synchronous detection circuit for outputting a synchronizing signal Te, the storage means includes means for storing the demodulated data and the outputted based on a write enable signal to the synchronization signal and an input which is the output as the reproduced track address It is characterized by the following.

[0006]

The edge detecting means detects an edge component from the reproduction input signal of the track address of the bi-phase modulated serial signal and outputs an edge signal. The logic level detecting means receives the output edge signal and outputs an N-bit signal.
Depending on the number of counters, width of 2 or 3 than N, eg
For example, if N = 5, is there an edge component between 2 and 7?
Whether the logic level of the demodulated data is
Outputs data, and Ru <br/> be present signal edges counted fewer than 8 outputs a clock signal. The lock detecting means determines that the interval of the output clock signal is the count number 8 (7 + 1).
, A lock signal is output when a predetermined number of times p are continued,
Interval and outputs an unlock signal when the successive number of Jo Tokoro count having 9 or more q. The synchronization detection circuit outputs a lock signal based on the output lock signal.
The synchronization pattern from the output of the logic level detection means.
And output a synchronization signal . The storage means stores the output demodulated data as a reproduced track address based on the detected synchronization signal and the input write enable signal.

As described above, there is no erroneous detection of the synchronization signal, and the track address can be taken out accurately.

[0008]

Embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of a track address demodulation circuit according to an embodiment of the present invention.

In FIG. 1, a track address demodulation circuit includes a memory 8 as storage means for storing a reproduced track address, and an error detection circuit 9 for detecting an error in the contents of the memory 8 read based on a memory read signal 29.
And a serial / parallel conversion circuit 13 for converting the read contents of the memory 8 into a parallel signal, and an output signal of the serial / parallel conversion circuit 13 based on an output signal of the error detection circuit 9 and stored based on a FIFO read signal 30. And a FIFO 10 for sequentially outputting the contents to the bus line.

A feature of the present invention is that a low-pass filter circuit is provided as edge detecting means for detecting an edge component from a reproduction input signal 21 of a track address of a biphase-modulated serial signal and outputting an edge signal. 1, the shift register 11, an edge detecting circuit 2 and the shift register 12, detects whether or not present in the number of counted edge signal outputted from the shift register 12 is Jo Tokoro D～j (e.g. 2-7) that Demodulated data 25 based on positive result
Outputs, Jo Tokoro number of counts I (e.g. 8) above when present in 5-bit counter 5 and a logic level detection means for outputting a clock signal 27 to the PLA (progr
amable logic array) the number of the circuit 4, a constant Tokoro output clock signal 27 is the number of counts I p
Outputting a lock signal 24 when the continuous, a lock detection circuit 7 as a lock detecting means for outputting an unlock signal when the interval count I + 1 (e.g., 9) consecutive number q of Jo Tokoro above the outputted lock signal Based on 24
When the lock signal 24 is output, the PLA circuit 4
From the demodulated data signal output from the
A synchronization detection circuit 6 for outputting a synchronization signal 26; and the memory 8 includes means for storing demodulated data 25 output based on the detected synchronization signal 26 and the input write enable signal 28 as the reproduced track address. Including.

The operation of the track address demodulation circuit having such a configuration will be described. FIG. 2 is a time chart of each signal at the time of writing to the memory of the track address demodulation circuit of the present invention. FIG. 3 is a flowchart for explaining the operation of the 5-bit counter of the track address demodulation circuit of the present invention. FIG. 4 shows a PLA of the track address demodulation circuit of the present invention.
4 is a flowchart illustrating an output operation of a circuit from a clock signal and a counter reset signal. FIG. 5 is a flowchart for explaining the output operation of the demodulated data of the PLA circuit of the track address demodulation circuit of the present invention. FIG. 6 is a flowchart illustrating the operation of the lock detection circuit of the track address demodulation circuit according to the present invention. FIG. 7 is a flowchart for explaining the operation of the synchronization detection circuit of the track address demodulation circuit of the present invention.

In FIG. 1 to FIG. 7, the same data is repeatedly recorded in three blocks by attaching a Reed-Solomon code to a track address signal. The bi-phase modulated reproduction input signal 21 is input to the low-pass filter circuit 1.
The low-pass filter circuit 1 converts the reproduction input signal 21 to 3 MHz
The above high frequency components are cut. Low-pass filter circuit 1
Is a digital filter composed of a three-stage shift register, an AND gate, an OR gate, and a selector. The AND gate and OR gate of the first stage and the last stage are selected by the output of the second stage, and high frequency components are removed. The signal that has passed through the low-pass filter circuit 1 is input to the edge detection circuit 2 via the shift register 11 at one stage. The edge detection circuit 2 detects an edge signal of the input signal, and supplies the edge signal to the logic level detection circuit 3.

The logic level detection circuit 3 comprises a PLA circuit 4 and a 5-bit counter 5. PLA circuit 4
Outputs an edge signal and outputs “1” as demodulated data 25 when the 5-bit counter value 22 is a value between “2” and “7”, and otherwise outputs “0”. When the 5-bit counter value 22 is 8 or more and an edge signal is input, a clock signal 27 and a counter reset signal 23 are output. The clock signal 27 output from the PLA circuit 4 is input to the lock detection circuit 7 and the synchronization detection circuit 6. The lock detection circuit 7 outputs the lock signal 24 to the synchronization detection circuit 6 when the clock signal 27 is present at least 13 times while watching the clock signal 27, and the interval of the clock signal 27 is 5 times or more, and Is detected as unlocked. 00H is output from the PLA circuit 4 to the synchronization detection circuit 6 when the lock signal 24 is being output.
Is input twice in succession, the synchronization detection circuit 6 detects the synchronization pattern and outputs a synchronization signal 26. Sync signal 26
Is output for 8 consecutive counts after 16 counts after the 00H pattern is detected twice when the lock signal 24 is output, and is effective as track address reproduction data from the demodulated data 25 after the sync signal 26 is output. become. When the synchronization signal 26 is detected, the write enable signal 28
Is output and the data is written into the memory 8. When the synchronizing signal 26 is detected three times and the data of the third block is written into the memory 8, the write enable signal 28 stops, and the writing of the data to the memory 8 ends.

FIG. 2 shows the timing of the above operation. Block 1, block 2, and block 3 indicate the reproduction data of the track address. The data written in the memory 8 is sequentially read out by the memory read signal 29 and input to the error detection circuit 9.
An error check is performed, and only data of a block without an error flag is converted from serial to parallel and written into the FIFO 10. If all three blocks are in error, the error flag is written into the FIFO 10 together with the data of the three blocks. The data written in the FIFO 10 is sequentially taken out to the bus line by the FIFO read signal 30.

[0015]

As described above, the present invention has an excellent effect that a track address can be accurately taken out without erroneous detection of a synchronization signal.

[Brief description of the drawings]

FIG. 1 is a block diagram of a track address demodulation circuit according to an embodiment of the present invention.

FIG. 2 is a time chart of each signal when writing data to a memory in the track address demodulation circuit of the present invention.

FIG. 3 is a flowchart illustrating the operation of a 5-bit counter of the track address demodulation circuit according to the present invention.

FIG. 4 is a flowchart illustrating an output operation of a clock signal and a counter reset signal of a PLA circuit of the track address demodulation circuit of the present invention.

FIG. 5 is a flowchart illustrating an output operation of demodulated data by a PLA circuit of the track address demodulation circuit according to the present invention.

FIG. 6 is a flowchart for explaining the operation of the lock detection circuit of the track address demodulation circuit of the present invention.

FIG. 7 is a flowchart for explaining the operation of the synchronization detection circuit of the track address demodulation circuit of the present invention.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 low-pass filter circuit 2 edge detection circuit 3 logic level detection circuit 4 PLA circuit 5 5-bit counter 6 synchronization detection circuit 7 lock detection circuit 8 memory 9 error detection circuit 10 FIFO 11, 12 shift register 13 serial / parallel conversion circuit 21 reproduction Input signal 22 5-bit counter value 23 Counter reset signal 24 Lock signal 25 Demodulated data 26 Synchronous signal 27 Clock signal 28 Write enable signal 29 Memory read signal 30 FIFO read signal

Claims (1)

(57) [Claims] 1. A track address demodulation circuit comprising storage means for storing a reproduced track address, wherein an edge component is detected from a reproduction input signal of a track address of a bi-phase modulated serial signal and an edge signal is output. Edge detection means, and the output edge signal is input and counted by an N-bit counter;
The component counts are predetermined d to j (d is
2 or 3 minus, j is N plus 2 or 3)
If the demodulated data exists between the counts of
And outputs one logical value, and the count number is d to j.
If there is any other than between, the other as demodulated data
And the count value of the counter is I (j
+1) a logic level detecting means for outputting a clock signal when an edge signal is input, and outputting a lock signal when the interval between the output clock signals is the first predetermined number p of counts I. a lock detecting means for outputting an unlock signal when the interval count (I + 1) successive second predetermined number q at least, this lock
The logic level detecting means when the logic signal is being output.
Detects that a synchronization pattern is being output from the
And a synchronous detection circuit for outputting a No., that is the storage means including means for storing the demodulated data and the outputted based on a write enable signal to the synchronization signal and an input which is the output as the reproduced track address Characterized track address demodulation circuit.