JP2805912B2 - Semiconductor element recognition correction method - Google Patents
Semiconductor element recognition correction methodInfo
- Publication number
- JP2805912B2 JP2805912B2 JP1298020A JP29802089A JP2805912B2 JP 2805912 B2 JP2805912 B2 JP 2805912B2 JP 1298020 A JP1298020 A JP 1298020A JP 29802089 A JP29802089 A JP 29802089A JP 2805912 B2 JP2805912 B2 JP 2805912B2
- Authority
- JP
- Japan
- Prior art keywords
- bonding
- wire
- axis
- semiconductor element
- bonding point
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/78—Apparatus for connecting with wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01039—Yttrium [Y]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01057—Lanthanum [La]
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置製造工程におけるワイヤーボンデ
ィング工程に関し、特に被ボンディング半導体素子の画
像認識後搭載ズレの補正方法に関する。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wire bonding process in a semiconductor device manufacturing process, and more particularly, to a method of correcting a mounting displacement after image recognition of a semiconductor element to be bonded.
従来のワイヤーボンディング装置では、被ボンディン
グ点が半導体チップのように搭載物上にある場合は、少
なくとも２つの被ボンディング点を画像認識した後Ｘ
軸,Y軸，θ軸の各軸での相対ズレを演算した後各軸での
位置補正してボンディングを行なっていた。In a conventional wire bonding apparatus, when a bonding point is on a mounted object like a semiconductor chip, X is recognized after image recognition of at least two bonding points.
After calculating the relative displacement in each of the axes, the Y-axis and the θ-axis, the position is corrected in each of the axes and bonding is performed.
しかしながら従来の半導体素子認識補正方法では、超
高周波素子のようにワイヤー長さの均一化が要求される
ものについては、Ｘ軸,Y軸，θ軸の３つでの搭載ズレ量
の演算値に基づいてボンディングを行なったのでは所要
の特性値が得られないという欠点がある。However, in the conventional method of recognizing and correcting a semiconductor device, for a device requiring a uniform wire length, such as an ultra-high frequency device, the calculated value of the mounting displacement amount in the three axes of the X-axis, the Y-axis, and the θ-axis is used. There is a disadvantage that the required characteristic value cannot be obtained if bonding is performed based on this.
本発明の半導体素子認識補正方法は、半導体チップ上
に設けられた第１の被ボンディング点と前記半導体チッ
プ外に設けられた第２の被ボンディング点、および前記
半導体チップ上に設けられた第３の被ボンディング点と
前記半導体チップ外に設けられた第４の被ボンディング
点をそれぞれワイヤーで接続するワイヤーボンディング
工程において、前記被ボンディング点の画像認識装置と
演算処理部とを有し、前記第１乃至第４の被ボンディン
グ点の画像認識を行なった後にこれら第１乃至第４の被
ボンディング点の所定位置からのズレ量を演算してこの
ズレ量に応じてボンディングする点の位置補正をＸ軸、
Ｙ軸およびθ軸のうちの１つまたは２つで行い、その後
ボンディングすることにより、前記第１および第２の被
ボンディング点を接続するワイヤーの長さと前記第３お
よび第４の被ボンディング点を接続するワイヤーの長さ
とを等しくすることを特徴としている。According to the semiconductor element recognition correction method of the present invention, a first bonding point provided on a semiconductor chip, a second bonding point provided outside the semiconductor chip, and a third bonding point provided on the semiconductor chip are provided. In a wire bonding step of connecting each of the bonding points to a fourth bonding point provided outside the semiconductor chip with a wire, the apparatus having an image recognition device for the bonding points and an arithmetic processing unit; After the image recognition of the first to fourth bonded points is performed, the shift amount of the first to fourth bonded points from a predetermined position is calculated, and the position correction of the point to be bonded is performed in accordance with the X-axis. ,
By performing bonding on one or two of the Y-axis and the θ-axis and then bonding, the length of the wire connecting the first and second bonded points and the third and fourth bonded points are determined. It is characterized in that the length of the connecting wire is made equal.
次に本発明について図面を参照して説明する。 Next, the present invention will be described with reference to the drawings.
第１図は本発明の一実施例のワイヤーボンディング図
である。ここでは、半導体素子１と半導体素子３の位置
を画像認識して演算処理した後、ｘ軸のズレ（Δx1,Δx
2）とθ軸のズレ（Δθ1,Δθ２）のみ補正してｙ軸は
第１のボンディング位置から所定のワイヤー長さでボン
ディングするものでこのことによりボンディングワイヤ
ー５の長さla,lb,lcはla＝lb＝lcとなりワイヤー長さの
均一化が実現できる。なお、従来方法のようにＸ−Ｙ−
θをすべての軸の位置補正した場合la≠lb≠lcとなって
しまい、ワイヤー長さの均一化が得られない。FIG. 1 is a wire bonding diagram of one embodiment of the present invention. Here, the position of the semiconductor element 1 and the position of the semiconductor element 3 are image-recognized and subjected to arithmetic processing, and then the x-axis deviation (Δx 1 , Δx
2) and θ-axis deviation ([Delta] [theta] 1, [Delta] [theta] 2) only corrected in y-axis length l a of the bonding wires 5 by the fact in which bonding at a predetermined wire length from the first bonding location, l b, l c is uniform in l a = l b = l c next wire length can be realized. In addition, XY-
If you position correction of all axes θ becomes a l a ≠ l b ≠ l c , is not uniform in the wire length is obtained.
第２図は本発明の他の実施例のワイヤーボンディング
図である。FIG. 2 is a wire bonding diagram of another embodiment of the present invention.
この場合半導体素子１をパッケージ等の突起を利用し
て搭載することによりθ軸でのズレが起こりにくい場合
の補正方法となる。ここでは、半導体素子１と半導体素
子３の位置を画像認識して演算処理した後、ｙ軸のズレ
（Δy1,Δy2）のみ補正してｘ軸，θ軸は無視してボン
ディングするもので、このことによりボンディングワイ
ヤー５の長さla,lb,lcはla＝lb＝lcとなりパッケージ内
でのワイヤー長さの均一化を実現できる。In this case, by mounting the semiconductor element 1 by using a projection such as a package, a correction method can be provided in a case where deviation in the θ axis hardly occurs. In this case, after the positions of the semiconductor elements 1 and 3 are image-recognized and subjected to arithmetic processing, bonding is performed by correcting only the deviation (Δy 1 , Δy 2 ) of the y-axis and ignoring the x-axis and θ-axis. , the length l a of the bonding wires 5 by the fact, l b, l c can realize uniformity of l a = l b = l wire length in c next in the package.
以上説明したように本発明では、半導体素子の搭載ズ
レを補正する軸（Ｘ−Ｙ−θ）の選択・命令に従って位
置補正してボンディングができることにより超高周波素
子のようにワイヤー長さの均一化が要求されるものには
ワイヤー長さ重視の為の位置補正命令を入力することに
より所要の特性値を得ることができ、ワイヤー長さの均
一化が不要な部分については、あらゆる搭載ズレも補正
してボンディングする命令を入力することにより搭載ズ
レの大きい半導体素子でもボンディングが可能となる。As described above, according to the present invention, since the position can be corrected and bonding can be performed in accordance with the selection and instruction of the axis (XY-θ) for correcting the mounting displacement of the semiconductor element, the wire length can be made uniform like an ultra-high frequency element. For those that require, the required characteristic value can be obtained by inputting a position correction command for emphasizing the wire length, and for parts where the wire length is not required to be uniform, any mounting deviation is corrected By inputting a bonding command, bonding can be performed even with a semiconductor element having a large mounting displacement.
さらにこれらの素子が混在する混成素子においても所
要に応じた補正命令を入力しボンディングすることによ
り特性をすべて満足することが可能となる効果がある。Further, even in a hybrid element in which these elements are mixed, there is an effect that all characteristics can be satisfied by inputting a necessary correction command and bonding.
第１図は本発明の一実施例による半導体素子認識補正方
法のワイヤーボンディング方法を示す図、第２図は本発
明の他の実施例でのワイヤーボンディングを示す図であ
る。 １……半導体素子、２……半導体素子の正規の位置、３
……半導体素子、４……半導体素子の正規の位置、５…
…ボンディングワイヤー。FIG. 1 is a diagram showing a wire bonding method of a semiconductor element recognition and correction method according to one embodiment of the present invention, and FIG. 2 is a diagram showing wire bonding in another embodiment of the present invention. 1 ... semiconductor element, 2 ... regular position of semiconductor element, 3
…… Semiconductor element, 4 …… Regular position of semiconductor element, 5…
... bonding wire.
Claims (1)
ディング点と前記半導体チップ外に設けられた第２の被
ボンディング点、および前記半導体チップ上に設けられ
た第３の被ボンディング点と前記半導体チップ外に設け
られた第４の被ボンディング点をそれぞれワイヤーで接
続するワイヤーボンディング工程において、前記被ボン
ディング点の画像認識装置と演算処理部とを有し、前記
第１乃至第４の被ボンディング点の画像認識を行なった
後にこれら第１乃至第４の被ボンディング点の所定位置
からのズレ量を演算してこのズレ量に応じてボンディン
グする点の位置補正をＸ軸、Ｙ軸およびθ軸のうちの１
つまたは２つで行い、その後ボンディングすることによ
り、前記第１および第２の被ボンディング点を接続する
ワイヤーの長さと前記第３および第４の被ボンディング
点を接続するワイヤーの長さとを等しくすることを特徴
とする半導体素子認識補正方法。A first bonding point provided on the semiconductor chip, a second bonding point provided outside the semiconductor chip, and a third bonding point provided on the semiconductor chip. In a wire bonding step of connecting a fourth bonding point provided outside the semiconductor chip with a wire, each of the first to fourth bonding points includes an image recognition device for the bonding point and an arithmetic processing unit. After the image recognition of the bonding point is performed, the shift amount of the first to fourth bonded points from a predetermined position is calculated, and the position correction of the bonding point is performed on the X axis, the Y axis, and θ in accordance with the shift amount. One of the axes
Or two and then bonding, so that the length of the wire connecting the first and second bonded points is equal to the length of the wire connecting the third and fourth bonded points. A semiconductor device recognition correction method characterized by the above-mentioned.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1298020A JP2805912B2 (en) | 1989-11-15 | 1989-11-15 | Semiconductor element recognition correction method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1298020A JP2805912B2 (en) | 1989-11-15 | 1989-11-15 | Semiconductor element recognition correction method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03157945A JPH03157945A (en) | 1991-07-05 |
| JP2805912B2 true JP2805912B2 (en) | 1998-09-30 |
Family
ID=17854081
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1298020A Expired - Fee Related JP2805912B2 (en) | 1989-11-15 | 1989-11-15 | Semiconductor element recognition correction method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2805912B2 (en) |
-
1989
- 1989-11-15 JP JP1298020A patent/JP2805912B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH03157945A (en) | 1991-07-05 |
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