JP2803643B2 - Successive decoding device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sequential decoding apparatus, and more particularly to a sequential decoding apparatus having a bit error rate detection circuit for detecting the bit error rate of decoded data as well as the bit error rate of received data.

[0002]

2. Description of the Related Art Sequential decoding performed by a sequential decoding apparatus is known as a decoding method for performing maximum likelihood decoding approximately with a given amount of memory and a limited amount of computation using a tree structure of a convolutional code. Have been. The sequential decoding device that performs such sequential decoding includes an encoder having the same function as the transmitting side, that is, a so-called encoder replica, and the received code sequence and the re-encoded code sequence best match. The branches of the tree structure are sequentially selected based on a predetermined algorithm and decoded by trial and error.

[0003] From such a background, in sequential decoding, the amount of calculation required for 1-bit decoding also depends on the quality of the transmission path, that is, the noise state, and it is determined whether the branch selected in sequential decoding is correct or not. The processing is performed while determining whether the path currently selected is correct or not using a likelihood value called a metric (Fano metric) as an evaluation scale.

In such a sequential decoding apparatus, in order to detect and correct a data transmission error, the data is divided into several information symbols, and an error correction encoder (hereinafter, referred to as an error correction encoder).
The resulting symbol is convolutionally encoded by a convolutional encoder into a code symbol, and the transmitted code symbol is sequentially decoded by an error correction decoder (hereinafter, simply referred to as a decoder) using a Fano algorithm.

Referring to FIG. 4, a basic configuration of such an encoder will be described. However, the length of the information symbol is (n
-1) bits, and the length of the code symbol is n bits. In FIG. 4, information bits input one bit at a time from an input terminal 201 are converted into serial / parallel converters (S / P) 20.
5, the input serial data is converted in parallel, and the bit length is (n−
1) After being converted into a bit information symbol, it is held in the state holding circuit 202, and the internal state of the state holding circuit 202 is updated by the held information symbol.

The state holding circuit 202 generally employs shift registers arranged in (n-1) stages in parallel. Each time an information symbol is input, the contents of each stage of the shift register are shifted right by one bit. The shift is performed, and a new information symbol is held at the left end of the shift register.

On the other hand, the internal state of the state holding circuit 202 is supplied to an input of a function generator 203. Each time an information symbol is input, the function generator 203 outputs a redundant bit.
A total of n bits are output as code symbols together with the information symbols, and after being parallel-serial converted by a parallel / serial converter (P / S) 206, output one bit at a time from an output terminal 204 for transmission.

FIG. 5 shows an example of a specific configuration in the case where n = 4 in the encoder of FIG. In the encoder shown in FIG. 5, the state holding circuit 302 has a three-stage parallel configuration consisting of one-stage shift registers 317, 318, and 319, in response to the serial-to-parallel converter 305 outputting a 3-bit information symbol. As a shift register.

Each time an information bit is input from the serial-to-parallel converter 305, the contents of the shift registers 317, 318 and 319 are shifted right by one bit by one bit.
, 318 and 319 hold new information symbols.

On the other hand, the internal state of the state holding circuit 302 is supplied to an input of a function generator 303, and the state holding circuit 302
Each time an information symbol is input to the function generator 303, the function generator 303 outputs a redundant bit, and outputs it together with the information symbol from the state holding circuit 302 as a 4-bit code symbol.
After the parallel / serial conversion is performed by the parallel / serial converter 306, the data is output from the output terminal 304 one bit at a time for transmission.
Note that the function generator 303 includes exclusive OR circuits 311, 312,
313, 314, 315 and 316.

The received signal sequence received by the decoder does not always match the bit sequence of the code symbol transmitted due to a transmission error. The decoder has an encoder having the same function as an encoder opposite via a transmission path (hereinafter referred to as an encoder copy). For example, if the length of an information symbol is 3 bits, 000,001,... , 111 are compared with the received signal sequence when all eight possible (information symbol) bit sequences are input to the encoder duplicate, respectively, and the code symbol closest to the received signal sequence is compared. Is estimated as the transmitted information symbol.

As an evaluation scale of proximity in this estimation,
A likelihood called Fano likelihood is used. In the Fano algorithm, basically, the information symbol sequence in which the cumulative likelihood of the Fano likelihood is the largest is determined to be the transmitted information symbol sequence. In this case, if an error occurs frequently in the received signal sequence, there is a possibility that the wrong information symbol is determined to be the transmitted information symbol. Once an erroneous decision is made, the internal state of the subsequent coder copy is very different from the internal state of the coder, after which it is difficult to find the information symbol with a large Fano likelihood. It can be detected that the judgment has been made.

When detecting that an erroneous determination has been made, the internal state of the encoder duplication is returned to the past state, and then the information symbol having the largest Fano likelihood next to the information symbol selected in the past is sent. Is determined, and decoding is performed again. Even if an attempt is made to find an information symbol having the next largest Fano likelihood, if the information symbol has already been searched and cannot be found, the operation returns to another state in the past and performs the same operation.

As described above, decoding is performed by repeating trial and error, and there is a possibility that the output result may be changed later. Therefore, the decoder needs a buffer for the input received signal sequence and a buffer for the decoding result. And

Next, the operation of the sequential decoding apparatus will be described with reference to FIG. FIG. 3 shows a conventional sequential decoding apparatus, in which a sequential decoding circuit 401 and a bit error rate detection circuit are shown.
402. In this figure, the coding rate is 3/4.
Therefore, the information rate (decoded data rate) is 300 Kbps, and the encoding rate (received data rate) is 400 K
bps. First, the operation of the sequential decoding circuit 401 will be described.

In FIG. 3, reference numeral 407 denotes a RAM serving as a buffer for storing received data, and reference numeral 408 denotes a RAM serving as a buffer for storing decoded data. These RAMs 407 and 408 are
Each has N addresses. D401 is 400 Kbps reception data input from a demodulator (not shown),
CL401 is a 400 KHz reception clock synchronized with the reception data D401. The counter 403 is an N-ary counter that counts the clock CL401 and outputs the count result as an address A401. Counter 404 is also an N-ary counter and is 10 MHz
, And outputs the counting result as an address A402. The selector 405 selects one of the addresses A401 and A402 according to the control signal B405 from the control circuit 411, and outputs it to the RAM 407 or 408.

When the received data D401 is input to the sequential decoding circuit 401, the counter 403 counts the clock CL401 and the address signal A401 increases by one. At this time, the control circuit 411
Responds to the clock CL401, and the control signals B401, B402, B4
Outputs 05. The selector 405 outputs an address signal A401 in response to the control signal B405. At this time, RAM 407
Writes the input received data D401 to the address A401 in response to the control signal B401, while the RAM 408
In response to B402, the decryption result D405 written to the address A401 is read. Therefore, address A401 is RAM
407 indicates the latest address at which the received data was written.

The decoding result D405 output from the address A401 of the RAM 408 is held in the latch circuit 409 at the timing when the control signal B405 causes the selector 405 to select the address A401. Since the decoded result output from the RAM 408 still contains redundant bits, in order to output the final decoded data to the outside of the decoder, the redundant bits are removed from the decoded result D405 and the speed conversion is performed. There is a need to.

Accordingly, the decoding result D406 output from the latch circuit 409 is subjected to a speed conversion circuit 410 in which redundant bits are removed in accordance with the redundant bit position identification signal B403 output from the control circuit 411, and further corresponds to information bits. Of frequency
The data is converted to data synchronized with the clock CL402 of 300 KHz, and this is output as decoded data D402 of 300 Kbps.

On the other hand, an address A402 indicates an address in the RAM 407 of the reception data D403 read from the RAM 407, which is currently being decoded by the decoding circuit 406. When the decoding of the received data D403 read from the RAM 407 immediately before is completed, the decoding circuit 406 outputs a control signal B404 for notifying the end of decoding to the control circuit 411 and outputs the decoding result D404 to the RAM 408.

The control circuit 411 responds to a control signal B404 for notifying the end of decoding, and outputs control signals B401, B402, B405 and
Outputs B406. The selector 405 outputs the address A402 in response to the control signal B405, and the decoded result D404 is the control signal B4
02 is stored in the address A402 of the RAM 408 in accordance with 02. The counter 404 responds to the control signal B406,
A402 is increased by one. Subsequently, the RAM 407 reads the reception data D403 stored in the address A402 (increased by one) according to the control signal B401 to the decoding circuit 406, and proceeds to the next decoding process.

Since the period of the clock CL403 used for the decoding process is much shorter than the period of the clock CL401,
If the reception data D401 has few transmission errors and decoding proceeds smoothly, the address A402 catches up with the address A401 and the RAM 407
Will decrypt the latest data written to
When the decoding of the data ends, there is no more received data D403 to be read.

In this way, the address A402 is
When the value becomes equal to A401, the control circuit 411 outputs a control signal B407, and the decoding circuit 406 suspends the decoding process in response to the control signal B407. When the decoding circuit 406 determines that the decoding is to be retracted according to the Fano algorithm, the decoding circuit 406 outputs a control signal B404 to the control circuit 411. The control circuit 411 outputs control signals B402 and B406 in response to the control signal B404. The counter 404 receives the control signal B406
, The value of the address A402 is decreased by one. RAM
408 reads the previously decoded result D405 from the address A402 (decreased by one) to the decoding circuit 406,
The decoding circuit 406 performs decoding again.

If the quality of the transmission path deteriorates and transmission errors frequently occur in the received data, re-decoding frequently occurs and decoding does not proceed. The received data D403 read from the RAM 407 to the decoding circuit 406 immediately before (the address in the RAM 407 is
A402) is written just before (the address is
A402-1) If decoding is delayed until the received data is overwritten by the newly input D401 (this write address is A401), in other words, if A402-1 = A401, then the newly input data will be newly input. The received data at the address A402 for which decoding has not been completed is rewritten by the received data.

For this reason, the control circuit 411 controls the A402
If decoding is delayed until -1 = A401, it is determined that the RAM 407 has overflowed. At this time, the control circuit 411
Causes the decoding circuit 406 to abandon decoding of n bits of the received data stored in the RAM 407. That is,
The control circuit 411 outputs an address initial value B409, a control signal B407, and a counter initial value B410 (the address value is A402 + n) which is n bits ahead of the current counter value. The counter 404 starts counting from the counter initial value B410 in response to the address initial value B409. The decoding circuit 406 receives the control signal B4
In response to 07, decoding is restarted from the received data written in A402 + n of the RAM 407. In the section where decoding is abandoned, the received data is output as decoded data as it is.

Next, the operation of the bit error rate detection circuit 402 for calculating the bit error rates of the received data and the decoded data will be described. The bit error rate of the received data is detected by comparing the received data with the decoded data.
Although the decoded data contains residual bit errors, it is negligible because it is much smaller than the number of bit errors contained in the received data.

The reception data D401 is a bit error rate detection circuit
The speed conversion circuit 412 removes the redundant bit in accordance with the redundant bit position identification signal B408 output from the control circuit 411, and further receives the received data D407 synchronized with the clock CL402 having a frequency corresponding to the information bit. Is converted to The speed-converted received data D407 is delayed by the delay circuit 413 by the decoding delay in the sequential decoding circuit 401 (N (address length of RAM) + α) in order to match the phase with the decoded data D402.

The exclusive-OR circuit 414 performs an exclusive-OR operation on the reception data D408 and the decoded data D402 whose phases match, thereby obtaining a bit error position detection signal E401 indicating the bit error position. Error rate calculation circuit 415
Calculates the received data BER bit error rate 4151 by counting the bit error position detection signal E401 for a certain fixed time.

The bit error rate of the decoded data is estimated from the bit error rate of the received data. That is, the relationship between the received data BER and the decoded data BER is determined in advance by experiments, and is input to the ROM 416 as a reference table. When the received data BER 4151 is input to the ROM 416, the corresponding decoded data BER 4161 is output.

[0030]

In the above-described conventional sequential decoding apparatus, the bit error rate of decoded data is estimated based on the bit error rate of received data. That is, the relationship between the received data BER and the decoded data BER is previously obtained by an experiment, input to the ROM as a reference table, and read the received data as an address.

However, the sequential decoding has a feature that the error correction capability changes depending on the bit rate of the received data. Therefore, it is necessary to perform a very complicated operation of obtaining a reference table for each bit rate of the received data and inputting the reference table to the ROM. In addition, since it is obtained by estimation based on the bit error rate of the received data, there is a disadvantage that the accuracy is low.

An object of the present invention is to solve the above-mentioned disadvantages,
Reference table R requiring extremely complicated work to create
An object of the present invention is to provide a sequential decoding device provided with a bit error rate detection circuit capable of obtaining a bit error rate of decoded data without requiring an OM.

[0033]

The present invention has the following means in order to achieve the above object. That is, the first configuration of the present invention relating to the sequential decoding device is to output decoded data sequentially decoded by receiving a code symbol obtained by performing convolutional coding on an information symbol, together with a reception data bit error rate and a decoded data bit error rate. A sequential decoding device having the following configurations (a) and (b). (A) The apparatus has an encoder copy having the same function as an encoder that performs convolutional coding on the transmission side, and performs sequential decoding on received data input as code symbols using Fano likelihood as an evaluation scale. A sequential decoding circuit that outputs decoded data and outputs a buffer overflow identification signal indicating an overflow occurrence section in a buffer where the decoded data is to be stored. (B) Data rate of the decoded data by inputting the received data as the code symbol After converting to the decoded data, a time error with the decoded data is secured, a bit error included in the received data is calculated based on a comparison process with the decoded data, and the calculated bit error is output as a received data bit error rate. Decoding data based on the buffer overflow identification signal output from the circuit and the received data bit error rate. Bit error rate detection circuit that calculates the bit error included in the data and outputs it as the decoded data bit error rate

Further, according to a second configuration of the present invention, in the first configuration, the sequential decoding circuit stores the received data and the decoded data in an R buffer as an independent buffer.
It has a configuration that can be stored in AM.

In a third configuration of the present invention, in the first or second configuration, the bit error rate detection circuit performs the comparison process on the output of the reception data bit error rate using an exclusive OR circuit. It has a configuration that is to be performed.

[0036]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In a conventional sequential decoding apparatus, the bit error rate of decoded data has been estimated based on the bit error rate of received data. That is, the relationship between the bit error rate of the received data and the bit error rate of the decoded data is determined in advance by experiments, and the data is input to a storage medium such as a ROM as a reference table, and the bit error rate of the received data is read out as an address. Was.

However, in sequential decoding, the error correction capability changes depending on the bit rate of the received data.
Therefore, it is necessary to assume a very complicated operation of obtaining a reference table for each bit rate of received data and inputting the reference table to a storage medium such as a ROM. In addition, there is also a disadvantage that the accuracy is low because it is obtained by estimation based on the bit error rate of the received data.

The residual error contained in the decoded data in the sequential decoding device is mainly caused by a buffer overflow in a buffer for storing processed data in the decoding process. That is, a correction error other than the buffer overflow, a so-called missed error, can be ignored compared to the error at the time of the buffer overflow. Therefore, if the section where the buffer overflow occurs can be specified for the decoded data, the bit error rate in the decoded data can be accurately estimated.

In the present invention, as shown in FIG. 1, a control circuit 111 of a sequential decoding circuit 101 outputs a buffer overflow identification signal B111 indicating an overflow section of a RAM 107 as a target buffer to a bit error rate detection circuit.
The data is supplied to an error rate calculation circuit 116 dedicated to the calculation of the decoded data bit error rate provided in 102, and based on the received data bit error rate output from the error rate calculation circuit 115 dedicated to the calculation of the received data error rate. Performing a simple and accurate bit error rate calculation is an embodiment of the present invention.

The number of bits in the bit error rate measurement period is R, the number of bits in the valid period specified by the buffer overflow identification signal B111 within the bit number R in the bit error rate measurement period is E, and the bit error of the received data (A) is Rate (BE
R) If _A , the bit error rate (BE) of the decoded data (B)
R) _B can be represented as follows: (BER) _B = E. (BER) _A / R The error rate calculation circuit 116 performs an operation according to the above-described formula to accurately calculate the bit error rate of the decoded data.

[0041]

Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of one embodiment of the present invention. The embodiment shown in FIG. 1 includes a sequential decoding circuit 101 for performing a sequential decoding process, and a bit error rate detection circuit 102 for detecting BER of received data and decoded data in the sequential decoding process.
And The sequential decoding circuit 101 includes counters 103 and 104 for outputting an address, a selector 105 for selecting the outputs of the counters 103 and 104, and a decoding circuit 106 which incorporates an encoder copy and performs a decoding process based on the Fano algorithm.
And a RAM 107 as a buffer for storing received data.
And a RAM 108 as a buffer for storing decoded data.
A latch circuit 109 for temporarily holding the decoding result read from the RAM 108, a speed conversion circuit 110 for performing data rate conversion on the decoding result output from the latch circuit 109 and sending it out as decoded data, And a buffer overflow identification signal B111 indicating an overflow occurrence section in the buffers of the RAMs 107 and 108.
Buffer overflow identification signal generation circuit 11 that outputs
And a control circuit 111 having 10.

The bit error rate detection circuit 102 converts the data rate of the received data input to the sequential decoding circuit 101 into the data rate of the decoded data and outputs the converted data rate.
2, a delay circuit 113 for providing a delay for temporally matching output data of the speed conversion circuit 112 with decoded data,
A bit error position detection signal is obtained by detecting the bit error position by taking the exclusive OR of the received data and the decoded data.
An exclusive-OR circuit 114 for outputting E101; an error rate calculation circuit 115 dedicated to reception data bit error rate detection for accumulating the bit error position detection signal E101 for each predetermined time and outputting the reception data BER 1151; An error rate calculation circuit 116 dedicated to decoding data bit error rate detection, which outputs decoded data BER 1161 based on the identification signal B111 and the received data BER 1151.

In the above configuration, the sequential decoding circuit 101
The control circuit 111 has a buffer overflow identification signal generation circuit 1110 that generates and outputs a buffer overflow identification signal B111 indicating an overflow section in the buffer of the RAM 107 or the RAM 108. The buffer overflow identification signal B111 is sent to the bit error rate detection circuit 102. ,
The bit error rate detection circuit 102 uses the ROM shown in FIG.
The only difference from the conventional sequential decoding apparatus shown in FIG. 3 is that an error rate calculation circuit 116 for calculating and outputting decoded data BER 1161 is provided in place of 416. Since these components have substantially the same function as the component having the same name, the detailed description of the individual components having these substantially identical functions will be omitted in the following description of the operation.

Next, the operation of this embodiment will be described.
First, a method of generating a buffer overflow identification signal will be described with reference to FIG. FIG. 2 shows a buffer overflow identification signal generation circuit included in the control circuit 111.
FIG. 11 is a block diagram showing a configuration of 1110. Address A101 and address A102 are buffer overflow detection circuits 11
Entered in 11. Buffer overflow detection circuit 1111
Is provided with an adder 1112 and a comparator 1113, supplies an address A101 to the adder 1112, and supplies an address A102 to the comparator 1113, and adds one bit for each input of the address A101 to compare with the address A102. When 1 = A101 holds, the buffer overflow occurrence signal B1111 is output to the J input terminal of the JK flip-flop 1116.

At this time, the JK flip-flop 1116 makes the buffer overflow identification signal B111 valid in response to the buffer overflow occurrence signal B1111 and sends it out from the Q output terminal. On the other hand, the adder 1114 adds a constant n bits to the address A102 for designating the section of the buffer overflow.
As a result, the decoding circuit 106 resumes decoding from the received data corresponding to the counter initial value B110.

In response to the occurrence of an overflow, decoding is not performed in the above-described n-bit section, and this n-bit section is a valid period of the buffer overflow identification signal B111. The JK flip-flop 1116 outputs the buffer overflow identification signal B111, which has been previously enabled, based on the buffer overflow end signal B1112 detected by the comparator 1115 and indicating when the address A101 becomes equal to the address initial value B109. Invalidate.

Returning to FIG. 1, a method of estimating the bit error rate of the decoded data will be described. In the buffer overflow occurrence section, the decoding operation is not performed, and the received data is output as decoded data as it is. Therefore, the number of bits in the bit error rate measurement period is R, and the buffer overflow identification signal B1 in R in the bit error rate measurement period is R1.
Assuming that the number of bits in the 11 valid period is E and the bit error rate of the received data (A) is (BER) _A , the bit error rate (BER) _B of the decoded data (B) is as follows, as described above. Can be expressed as (BER) _B = E · (BER) _A / R The error rate calculation circuit 116 of the bit error rate detection circuit 102
The buffer overflow identification signal B111 is sent from the buffer overflow identification signal generation circuit 1110 of the control circuit 111,
Further, the received data BER 1151 is provided from the error rate calculation circuit 115, driven by the clock CL102, performs the above-described operation, calculates the bit error rate of the decoded data, and outputs it as the decoded data BER 1161.

In this way, it is not necessary to create a complicated conversion table of received data BER / decoded data BER based on an experiment, and it is possible to accurately estimate decoded data BER with a simple configuration.

[0049]

As described above, the present invention relates to a sequential decoding apparatus provided with a sequential decoding circuit and a bit error rate detection circuit for detecting a bit error rate of received data and decoded data. Generates a buffer overflow identification signal that specifies the buffer overflow occurrence section, and calculates the bit error rate of the decoded data based on the signal and the bit error rate of the received data, thereby significantly simplifying the calculation of the bit error rate of the decoded data. And has the effect of increasing the accuracy.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a sequential decoding device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a buffer overflow identification signal generation circuit 1110 of FIG.

FIG. 3 is a block diagram showing a configuration of a conventional sequential decoding device.

FIG. 4 is a block diagram illustrating a basic configuration of an error correction encoder.

FIG. 5 is a block diagram showing a specific configuration of an error correction encoder.

[Explanation of symbols]

 101,401 successive decoding circuit 102,402 bit error rate detection circuit 103,403 counter 104,404 counter 105,405 selector 106,406 decoding circuit 107,407 RAM 108,408 RAM 109,409 latch circuit 110,410 speed conversion circuit 111,411 control circuit 112,412 speed conversion circuit 113,413 delay circuit 114,414 exclusive OR circuit 115,415 error rate calculation Circuit 116 Error rate calculation circuit 416 ROM 1110 Buffer overflow identification signal generation circuit 1111 Buffer overflow detection circuit 1112,1114 Adder 1113,1115 Comparator 1116 J-K flip-flop

Claims (3)

(57) [Claims] The present invention is characterized in that it comprises the following components, and outputs decoded data sequentially decoded by receiving a code symbol obtained by performing convolutional coding on an information symbol, together with a received data bit error rate and a decoded data bit error rate. An iterative decoding device. (A) A coder replica having the same function as a coder performing convolutional coding on the transmission side is provided, and sequential decoding is performed on received data input as code symbols using Fano likelihood as an evaluation scale. A sequential decoding circuit that outputs decoded data and outputs a buffer overflow identification signal indicating an overflow occurrence section in a buffer where the decoded data is to be stored. (B) Data rate of the decoded data by inputting received data as the code symbol After converting to the decoded data, a time error with the decoded data is secured, a bit error included in the received data is calculated based on a comparison process with the decoded data, and the calculated bit error is output as a received data bit error rate. Decoding data based on the buffer overflow identification signal output from the circuit and the received data bit error rate. Bit error rate detection circuit that calculates the bit error included in the data and outputs it as the decoded data bit error rate 2. The sequential decoding circuit according to claim 1, wherein said reception data and said decoded data are stored in an independent buffer, respectively.
2. The sequential decoding device according to claim 1, wherein the sequential decoding device has a configuration in which the data is stored in an AM. 3. The bit error rate detection circuit according to claim 1, wherein said comparison processing on the output of said reception data bit error rate is performed by an exclusive OR circuit. Sequential decoding device.