JP2803389B2 - Timer device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a timer device for counting an external event or an internal clock and outputting a signal based on a coincidence with a predetermined set value.

[0002]

2. Description of the Related Art A conventional example will be described with reference to FIG.

The timer device 400 includes an event counter 401 for counting an external event input, a timer 402 for counting an internal clock, and an event counter 401.
Comparison registers 102 and 103 for setting the coincidence timing between the counter 401 and the timer 402;
Comparator 104,1 which detects the coincidence of the contents with 2,103
05 and a timer output register 106 set and reset by the coincidence output from the comparators 104 and 105,
It is configured.

The comparators 104 and 105 output a set signal 104-1 and a reset signal 105-1 for the timer output register 106.

Hereinafter, a case will be described in which a timer output register 106 outputs a waveform that is set after a predetermined number of external event counts are input and reset after a predetermined number of internal clock counts are input.

The external event count until set is stored in a comparison register 102, and the internal clock count from set to reset is stored in a comparison register 103.
And the event counter 401 is started.

When the contents of the event counter 401 and the contents of the comparison register 102 match, a set signal 104-1 is output from the comparator 104, the output of the timer output register 106 is set, and the contents of the timer 402 are set to "0". And start counting. Timer 4
02 and the contents of the comparison register 103 match,
A reset signal 105-1 is output from the comparator 105,
The output of the timer output register 106 is reset.

By repeating the above operation, a timer output in which a high width and a low width of a waveform are designated by different clock sources is realized.

[0009]

In the above-described conventional timer device, when the output waveform set / reset timing is controlled based on the counting results counted by different counting sources, two timers / counters are used. Timer /
This is realized by synchronizing the counters, and has a drawback that the burden on hardware is large and the timer configuration is not versatile.

[0010]

SUMMARY OF THE INVENTION A timer device according to the present invention comprises a counting means for counting an external event or an internal clock, a storage means for designating a coincidence timing with the counting result of the counting means, and a storage means for storing the counting means. Comparing means for comparing the contents with the means, output means for changing the output level based on the comparison result from the comparing means, and control means for controlling the count input signal of the counting means based on the comparison result from the comparing means. Have.

[0011]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows an embodiment of a timer device according to the present invention. The timer device 100 includes a timer / event counter 101 for counting an internal clock or an event input from the outside, and a timer / event counter 1
Comparison register 10 for setting the coincidence timing with 01
2 and 103, comparators 104 and 105 for detecting a match between the value of the timer / event counter 101 and the contents of the comparison registers 102 and 103, and a timer set and reset by the match output from the comparators 104 and 105 It comprises an output register 106 and a timer input control unit 107 for controlling the count input source of the timer / event counter 101 based on coincidence outputs from the comparators 104 and 105.

The comparators 104 and 105 output a set signal 104-1 and a reset signal 105-1 for the timer output register 106.

The set signal 104-1 and the reset signal 105-1 are input to the timer input control unit 107, and the internal clock input 107-1 and the external event input 1 are input to the timer input control unit 107.
07-2 is input as a count input source to the timer / event counter 101, and the timer / event counter 101
Clock 107-3 and clear signal 107-
4 is output.

Hereinafter, a case will be described in which a timer output register 106 outputs a waveform that is set after a predetermined number of external event counts are input and reset after a predetermined number of internal clock counts are input.

The number of external event counts before being set is stored in a comparison register 102, and the number of internal clock counts from being set until reset is stored in a comparison register 103.
And the timer / event counter 101 is started by the event counting operation.

When the contents of the timer / event counter 101 and the comparison register 102 match, a set signal 104-1 is output from the comparator 104, the output of the timer output register 106 is set, and the timer input control unit 107 Then, the contents of the timer / event counter 101 are cleared to "0" and the input clock source is switched to the internal clock. As a result, the timer / event counter 101 starts counting the internal clock, and when the count matches the content of the comparison register 103, the comparator 105 outputs the reset signal 105-1 and the output of the timer output register 106 is reset. At the same time, the timer input control unit 107 clears the content of the timer / event counter 101 to “0” and switches the input clock source to the event input.

By repeating the above operation, a timer output in which the high width and the low width of the waveform are designated by different clock sources is realized.

FIG. 2 shows another embodiment of the timer device according to the present invention.

The timer device 200 includes a timer / event counter 101 for counting an internal clock or an event input from the outside, and a comparison register 1 for setting coincidence timing between the timer / event counter 101 and the timer / event counter 101.
02, 103, comparators 104, 105 for detecting a match between the value of the timer / event counter 101 and the contents of the comparison registers 102, 103, and a timer set and reset by the match output from the comparators 104, 105 It comprises an output register 106 and a timer input control unit 201 for controlling the count input source of the timer / event counter 101 based on coincidence outputs from the comparators 104 and 105.

The comparators 104 and 105 output a set signal 104-1 and a reset signal 105-1 for the timer output register 106.

The set signal 104-1 and the reset signal 105-1 are input to the timer input control unit 201, and the internal clock input 201-1 and the external event input 2 are input to the timer input control unit 201.
0-1 is input as a count input source to the timer / event counter 101, and the timer / event counter 101
Clock 201-3 and clear signal 201-
4 is output.

The timer input control unit 201 comprises a set timing / clock source designation register 201-5 and a reset timing / clock source designation register 201-
6.

By setting an event input in the set timing / clock source designation register 201-5 and setting an internal clock in the reset timing / clock source designation register 201-6, the timer output register 1 is set.
Reference numeral 06 denotes a waveform which is set after the input of the predetermined number of external event counts and reset after the input of the predetermined number of internal clocks described in the first embodiment.

The operation when the same clock source, for example, an internal clock is set in the set timing / clock source designation register 201-5 and the reset timing / clock source designation register 201-6 will be described below.

The internal clock count until set is set in the comparison register 102, and the internal clock count until reset corresponding to the cycle of the output waveform is set in the comparison register 103.
1 is started by a timer operation.

When the contents of the timer / event counter 101 and the comparison register 102 match, the set signal 104-1 is output from the comparator 104, and the output of the timer output register 106 is set. In this case, the value of the timer / event counter 101 is not cleared. Timer /
When the event counter 101 matches the content of the comparison register 103, the comparator 105 outputs a reset signal 105-
1 is output, the output of the timer output register 106 is reset, and the timer input control unit 201 clears the content of the timer / event counter 101 to “0”.

By repeating the above operation, a PWM waveform is realized with the same clock source.

FIG. 3 shows "A" in the comparison register 102,
Embodiment 1 when “B” is set in the comparison register 103
And the waveforms described in the second embodiment.

[0030]

As described above, the present invention relates to a timer device for controlling an output based on a match with a comparison register.
When outputting a waveform in which the set timing and the reset timing are controlled by the counting results counted by different counting sources, the clock input source of one timer / event counter is synchronized with the set and reset timing of the timer output. The present invention provides a highly versatile timer device that can reduce the amount of hardware compared to the related art and can also handle ordinary PWM output.

[Brief description of the drawings]

FIG. 1 is a block diagram of a first embodiment of the present invention.

FIG. 2 is a block diagram of a second embodiment of the present invention.

FIG. 3 is a waveform output diagram of the first embodiment and the second embodiment of the present invention.

FIG. 4 is a block diagram of a conventional example.

[Explanation of symbols]

201-6 Reset timing / clock source specification register 400 Timer device 401 Event counter 402 Timer

Claims (1)

(57) [Claims] 1. A counting means for counting an external event or an internal clock, a storage means for designating a coincidence timing with a counting result of the counting means, and a comparison for comparing the contents of the counting means and the storage means. Means, and a timer device having an output means for changing an output level based on a comparison result from the comparison means, wherein the control means controls a count input signal of the counting means based on the comparison result from the comparison means. The control means switches the count input signal of the counting means based on the comparison result from the comparison means, thereby controlling the output waveform of the output means according to the counting results of different count inputs. And a timer device.