JP2800722B2 - Terminal current calculation error evaluation method in semiconductor simulation - Google Patents

Terminal current calculation error evaluation method in semiconductor simulation

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Publication number
JP2800722B2
JP2800722B2 JP7171658A JP17165895A JP2800722B2 JP 2800722 B2 JP2800722 B2 JP 2800722B2 JP 7171658 A JP7171658 A JP 7171658A JP 17165895 A JP17165895 A JP 17165895A JP 2800722 B2 JP2800722 B2 JP 2800722B2
Authority
JP
Japan
Prior art keywords
error
current
terminal current
electrode
terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP7171658A
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Japanese (ja)
Other versions
JPH096832A (en
Inventor
克彦 田中
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NEC Corp
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NEC Corp
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Filing date
Publication date
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Publication of JPH096832A publication Critical patent/JPH096832A/en
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Publication of JP2800722B2 publication Critical patent/JP2800722B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は半導体素子内部の物理状
態を数値的に求めることにより、端子電流値を予測し、
端子電流の計算誤差を求めてその評価を行う方法に関す
る。
BACKGROUND OF THE INVENTION The present invention predicts a terminal current value by numerically obtaining a physical state inside a semiconductor device,
The present invention relates to a method of obtaining a calculation error of a terminal current and evaluating the same.

【0002】[0002]

【従来の技術】半導体素子の開発においては、素子内部
の物理状態を数値的に求めることにより素子動作を予測
できる半導体デバイスシミュレータが頻繁に利用され
る。例えば、半導体素子の動作を記述する偏微分方程式
に有限差分法(controlvolume法)による
空間的な離散化を施して半導体素子内部の物理状態を数
値的に求め、素子動作を予測する方法がある。しかしな
がら、この方法においては、解析時の離散化誤差に関し
てシミュレーションが情報を利用者に提示することはな
く、利用者は自身の経験に基づいて離散化格子の作成,
最適化を行っている。
2. Description of the Related Art In the development of semiconductor devices, semiconductor device simulators capable of predicting device operation by numerically obtaining the physical state inside the device are frequently used. For example, there is a method of performing a spatial discretization by a finite difference method (control volume method) on a partial differential equation describing an operation of a semiconductor element, numerically obtaining a physical state inside the semiconductor element, and predicting an element operation. However, in this method, the simulation does not present information to the user regarding the discretization error at the time of analysis, and the user creates a discretization grid based on his own experience.
Optimization has been performed.

【0003】この最適化作業を支援するための誤差情報
を作成する方法として種々のものが考案されている。例
えば、半導体素子内部の不純物濃度分布を利用するもの
(特開平3−101150号公報)、電界や電流密度の
誤差分布を数学的に推定する方法(サイアム・ジャーナ
ル・オン・ニューメリカル・アナリシス(SIAMj.
Numer.Anal.),Vol.15,No.4,
pp.736−754,1978)等が知られている。
[0003] Various methods have been devised as a method for creating error information for supporting this optimization work. For example, a method using an impurity concentration distribution inside a semiconductor element (Japanese Patent Laid-Open No. 3-101150), a method of mathematically estimating an error distribution of an electric field or a current density (Siam Journal on Numerical Analysis (SIAMj)) .
Numer. Anal. ), Vol. 15, No. 4,
pp. 736-754, 1978).

【0004】[0004]

【発明が解決しようとする課題】通常、シミュレータを
利用する目的は多くの場合、端子電流値の予測であり、
したがって利用者は端子電流値に含まれる誤差が小さく
なるような離散化格子を作成する。したがって、誤差情
報としては、端子電流誤差がどの程度なのかを示すもの
であることが望ましい。しかし、従来の誤差情報生成手
法では、電流密度等の誤差分布を知ることは可能である
が、端子電流に含まれる誤差を評価することはできない
という問題がある。
Usually, the purpose of using a simulator is to predict a terminal current value in many cases.
Therefore, the user creates a discretized grid in which the error included in the terminal current value is reduced. Therefore, it is desirable that the error information indicates how much the terminal current error is. However, in the conventional error information generation method, it is possible to know an error distribution such as a current density, but there is a problem that an error included in a terminal current cannot be evaluated.

【0005】[0005]

【発明の目的】本発明の目的は、電流密度等の誤差分布
に基づいて端子電流値に含まれる誤差を評価する方法を
与えることにある。
SUMMARY OF THE INVENTION It is an object of the present invention to provide a method for evaluating an error contained in a terminal current value based on an error distribution such as a current density.

【0006】[0006]

【課題を解決するための手段】本発明の端子電流計算誤
差の評価方法は、図1にそのフローチャートを示すよう
に、先ず、素子内部の電流密度分布素子特性計算を行
う(ステップS1)。次いで、電流密度の誤差分布と、
キャリアの生成再結合率から求められる単位正電荷の生
成率の誤差分布とを求める(ステップS2)。次に、誤
差を求めたい端子の電極と素子との界面を含む閉領域を
定め、この閉領域内部において単位正電荷の生成率の誤
差を積分した量と、閉領域表面の電極界面を除いた部分
において表面に垂直で外向きの電流密度の誤差を積分
た量との差から端子電流値の誤差を推定する(ステップ
S3)。
In the method of evaluating a terminal current calculation error according to the present invention, first, as shown in the flowchart of FIG. 1, element characteristics of a current density distribution inside the element are calculated (step S1). Then, the error distribution of the current density,
An error distribution of the unit positive charge generation rate obtained from the carrier generation and recombination rate is obtained (step S2). Next, a closed region including the interface between the electrode of the terminal and the element whose error is to be obtained is defined, and an amount obtained by integrating the error of the unit positive charge generation rate inside the closed region and the electrode interface on the surface of the closed region are removed. An error in the terminal current value is estimated from the difference from the amount obtained by integrating the error of the current density perpendicular to the surface and outward in the portion (step S3).

【0007】[0007]

【作用】すなわち、図2に示すように、電極と素子との
界面を含む閉領域Ωを定義した時、Ωの境界Γ、及び電
極界面から流れ出る電荷量とΩ内で生成される電荷量は
等しいので、電極から流れ出る電流Iは次式を満たすこ
とがわかる。
In other words, as shown in FIG. 2, when a closed region Ω including the interface between the electrode and the element is defined, the boundary の of Ω, the amount of charge flowing out from the electrode interface and the amount of charge generated in Ω are Since they are equal, it can be seen that the current I flowing out of the electrode satisfies the following equation.

【数2】 但し、Jは電流密度,nはΓに垂直で外向きの単位方向
ベクトル,Gは単位正電荷の生成率である。電子の生成
によって負の電荷を生じる場合はGは負の値となる。
(Equation 2) Here, J is a current density, n is a unit direction vector perpendicular to Γ and outward, and G is a unit positive charge generation rate. When a negative charge is generated by the generation of electrons, G has a negative value.

【0008】この式から、電流の誤差,電流密度の誤
差,電荷生成率の誤差をそれぞれδI,δJ,δGと書
けば、
From this equation, if the error of the current, the error of the current density, and the error of the charge generation rate are written as δI, δJ, δG, respectively,

【数3】 となることがわかる。(Equation 3) It turns out that it becomes.

【0009】δIを求めるには電流密度も電荷生成率の
誤差を知る必要があるが、精度の高い解法ないしは細か
い格子を使って、局所的に解き直すという方法(例え
ば、アイ・トリプル・イー・トランザクションズ・オン
・コンピュータ・エイディッド・デザイン(IEEE
Trans.CAD),Vol.10,No.10,p
p.1251−1257,1991)や、得られている
電流分布等の補間によって近似解を構成し、それとの誤
差と見なす方法(アイ・イー・アイ・シー・イー・トラ
ンザクションズ・オン・エレクトロニクス(IEICE
Trans.Electron.),Vol.E77
−C,No.2,pp.214−217,1994)等
を用いることができる。閉領域Ωは原理的には任意に選
ぶことができるが、実用上は電気特性の解析に用いたメ
ッシュとの整合性や、誤差の検出容易性を考慮すること
が望ましい。
In order to obtain δI, it is necessary to know the error in the current density and the charge generation rate. Transactions on Computer Aided Design (IEEE
Trans. CAD), Vol. 10, No. 10, p
p. 1251-1257, 1991) or a method of constructing an approximate solution by interpolation of the obtained current distribution or the like and treating it as an error therefrom (IEICE Transactions on Electronics (IEICE)
Trans. Electron. ), Vol. E77
-C, No. 2, pp. 214-217, 1994). The closed region Ω can be arbitrarily selected in principle, but in practical use, it is desirable to consider the consistency with the mesh used for the analysis of the electrical characteristics and the ease of detecting an error.

【0010】半導体デバイスシミュレーションでは解析
メッシュのメッシュ辺の中点における電流密度を近似的
に求め、メッシュ辺の垂直二等分面上の電流密度がこの
値で一定であるとしてメッシュ点間の電流量を近似して
いる。したがって、境界Γはメッシュ辺の垂直二等分面
をつないで構成し、垂直方向の電流密度が容易に計算で
きるようにするのが得策である。また、電流密度誤差が
正確に求まっていればΩのとり方に依らず端子電流誤差
を見積ることができるが、一般的には電流密度誤差の信
頼性は場所によって異なるため、電流密度誤差が観測し
易い領域をΓが横切るように設定することも電流誤差の
推定精度を上げる上で大切である。
In the semiconductor device simulation, the current density at the midpoint of the mesh side of the analysis mesh is approximately determined, and the current density on the vertical bisecting plane of the mesh side is assumed to be constant at this value, and the current amount between the mesh points is determined. Is approximated. Therefore, it is advisable to form the boundary で by connecting the perpendicular bisectors of the mesh sides so that the current density in the vertical direction can be easily calculated. In addition, if the current density error is accurately obtained, the terminal current error can be estimated irrespective of how to select Ω.However, since the reliability of the current density error generally differs depending on the location, the current density error should be observed. It is also important to set a region that is easy to cross by Γ in order to increase the accuracy of current error estimation.

【0011】[0011]

【実施例】次に、本発明について図面を参照して説明す
る。図3に示すMIS構造を例にとって説明する。この
MIS構造素子は、半導体基板9上にゲート絶縁膜5と
ゲート電極4を有し、かつ半導体基板9の主面にソース
・ドレインの各拡散層8を有する。そして、これらの拡
散層8上にソース電極6とドレイン電極7が形成された
一般的に知られている構成である。ここで、ドレイン電
極7と拡散層8との界面(線分AE)と、折れ線ABC
DEで表される境界Γで囲まれる閉領域をΩとする。解
析格子が直交格子の場合には、このように境界Γを水平
及び垂直辺のみで構成することにより、境界Γに直交す
る電流密度を評価することが容易になる。
Next, the present invention will be described with reference to the drawings. This will be described by taking the MIS structure shown in FIG. 3 as an example. This MIS structure element has a gate insulating film 5 and a gate electrode 4 on a semiconductor substrate 9, and has a source / drain diffusion layer 8 on the main surface of the semiconductor substrate 9. The source electrode 6 and the drain electrode 7 are formed on these diffusion layers 8 in a generally known configuration. Here, the interface (line segment AE) between the drain electrode 7 and the diffusion layer 8 and the broken line ABC
A closed region surrounded by a boundary さ れ る represented by DE is defined as Ω. When the analysis grid is an orthogonal grid, by forming the boundary Γ with only the horizontal and vertical sides in this way, it becomes easy to evaluate the current density orthogonal to the boundary Γ.

【0012】閉領域Ω内部の単位正電荷の生成率の誤差
分布と、境界Γ上での境界Γに直交する電流密度誤差を
公知の手法により推定すれば、(1)式をそのまま用い
てドレイン電流誤差を求めることができる。しかし、よ
り簡略化した表式を用いることも可能である。境界Γの
うち、AB間に関しては、ゲート絶縁膜5を通過する電
流が通常はドレイン電流よりもはるかに小さくデバイス
シミュレータではこの電流成分を通常考慮しないこと、
DE間はデバインスシミュレータでは反射型境界を用い
るため、計算上キャリアの流出がないことから、電流密
度誤差の評価をする必要はなく、
If the error distribution of the unit positive charge generation rate inside the closed region Ω and the current density error orthogonal to the boundary Γ on the boundary Γ are estimated by a known method, the drainage can be obtained by using the equation (1) as it is. The current error can be determined. However, it is also possible to use a more simplified expression. Of the boundary Γ, between AB, the current passing through the gate insulating film 5 is usually much smaller than the drain current, and the device simulator does not usually consider this current component;
Since the reflection type boundary is used in the device simulator between DEs, there is no outflow of carriers in the calculation, so there is no need to evaluate the current density error.

【数4】 となる。(Equation 4) Becomes

【0013】さらに、δGがドレイン電流に与える影響
は極めて小さいこと、CD間はドレイン空乏層内での電
子正孔対の発生やインパクトイオン化現象で生成された
正孔による電流が主であるが、ドレイン電流に比べて極
めて小さいことから、現実的には、
Further, the influence of δG on the drain current is extremely small, and between CDs, the current is mainly caused by the generation of electron-hole pairs in the drain depletion layer and the holes generated by the impact ionization phenomenon. Since it is extremely small compared to the drain current, in reality,

【数5】 によってδIを見積ることが可能である。(Equation 5) Makes it possible to estimate δI.

【0014】[0014]

【発明の効果】以上説明したように本発明は、誤差を求
める端子電極と素子との界面を含む閉領域を定め、この
閉領域内部において単位正電荷の生成率の誤差を積分し
た量と、閉領域表面の電極界面を除いた部分において表
面に垂直で外向きの電流密度の誤差を積分した領域との
差から端子電流誤差を求めることができるので、シミュ
レータの利用者は十分な精度で解析が行えたか否かが明
確に判断できる。また、多少粗い格子であっても、本発
明方法を用いて端子電流値を補正することにより、精度
の高い値にすることも可能である。
As described above, according to the present invention, a closed region including an interface between a terminal electrode for which an error is to be determined and an element is determined, and an amount obtained by integrating the error of the unit positive charge generation rate within the closed region, Since the terminal current error can be obtained from the difference between the area of the closed area surface excluding the electrode interface and the area in which the current density error perpendicular to the surface and outward is integrated, the simulator user can analyze with sufficient accuracy It can be clearly determined whether or not was performed. Even if the grid is slightly coarse, it is possible to obtain a highly accurate value by correcting the terminal current value using the method of the present invention.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の端子電流誤差評価方法の処理工程を示
すフローチャートである。
FIG. 1 is a flowchart showing processing steps of a terminal current error evaluation method of the present invention.

【図2】電極表面を含む閉領域、及び電極表面を除いた
閉領域の表面を例示するためのの模式図である。
FIG. 2 is a schematic diagram for illustrating a closed region including an electrode surface and a surface of a closed region excluding the electrode surface.

【図3】MIS構造素子とドレイン電流誤差を評価する
ための閉領域を示す模式図である。
FIG. 3 is a schematic diagram showing a MIS structure element and a closed region for evaluating a drain current error.

【符号の説明】[Explanation of symbols]

1 電極 2 閉領域Ω 3 電極表面を除く閉領域表面Γ 4 ゲート電極 5 ゲート絶縁膜 6 ソース電極 7 ドレイン電極 8 拡散層(ソース・ドレイン) 9 半導体基板 Reference Signs List 1 electrode 2 closed region Ω 3 closed region surface excluding electrode surfaceΓ 4 gate electrode 5 gate insulating film 6 source electrode 7 drain electrode 8 diffusion layer (source / drain) 9 semiconductor substrate

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 半導体素子の動作を記述する偏微分方程
式に有限差分法による空間的な離散化を施して半導体素
子内部の物理状態を数値的に求め、素子動作を予測する
半導体シミュレーションにおいて、電流誤差を求めたい
端子の電極と素子との界面を含む閉領域を定め、この閉
領域内部において単位正電荷の生成率の誤差を積分した
量と、閉領域表面の電極界面を除いた部分において表面
に垂直で外向きの電流密度の誤差を積分した量との差か
ら端子電流値の誤差を求める工程とを含むことを特徴と
する半導体シミュレーションにおける端子電流計算誤差
評価方法。
1. A numerically determine the physical state of the semiconductor device by performing spatial discretization by the finite difference method the partial differential equations describing the operation of the semiconductor device, the semiconductor simulation to predict device operation, current A closed area including the interface between the terminal electrode and the element for which an error is to be determined is defined, and the amount obtained by integrating the error of the unit positive charge generation rate inside this closed area and the surface of the closed area surface excluding the electrode interface are determined. Calculating a terminal current value error from a difference between an amount of integration of a current density error in a vertical direction and a terminal current error in a semiconductor simulation.
JP7171658A 1995-06-15 1995-06-15 Terminal current calculation error evaluation method in semiconductor simulation Expired - Lifetime JP2800722B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7171658A JP2800722B2 (en) 1995-06-15 1995-06-15 Terminal current calculation error evaluation method in semiconductor simulation

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7171658A JP2800722B2 (en) 1995-06-15 1995-06-15 Terminal current calculation error evaluation method in semiconductor simulation

Publications (2)

Publication Number Publication Date
JPH096832A JPH096832A (en) 1997-01-10
JP2800722B2 true JP2800722B2 (en) 1998-09-21

Family

ID=15927304

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
JP (1) JP2800722B2 (en)

Also Published As

Publication number Publication date
JPH096832A (en) 1997-01-10

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