JP2800272B2 - Data display control device - Google Patents

Description

Description TECHNICAL FIELD [0001] The present invention relates to a data display control device.

BACKGROUND OF THE INVENTION Conventionally, in a data display control device, particularly in a display device having a small display space and a small display digit, for example, a display device of an electronic timepiece with a data bank, the number of characters of display data exceeds the number of display digits of the display portion. In many cases, a moving display, that is, a sweep display in which the number of characters to be displayed is sequentially moved to one side, that is, a sweep display is performed.

By the way, in this type of device, the sweep speed at the time of the sweep display is not limited to the data type, that is, the data that is likely to be misread and the data that is unlikely to be generated.
It is always constant, so misreading may occur frequently depending on the data type.

[Object of the Invention] The present invention has been made in view of the above-described circumstances,
It is an object of the present invention to provide a data display control device capable of displaying data that is relatively easy to read in a sweep display in a manner in which misreading does not frequently occur.

[Summary of the Invention] In order to achieve the above-mentioned object, the present invention enables a sweep display to be stopped and changed to a fixed display by operating only a display control key.
The gist of the present invention is that display data can be sequentially displayed by moving the display data forward or backward by one character.

EXAMPLES Hereinafter, the present invention will be specifically described based on an example shown in the drawings. In the present embodiment, the present invention is applied to an electronic wristwatch having a data bank function which includes a liquid crystal display panel and displays various data thereon.

Configuration FIG. 1 shows the appearance of this embodiment. FIG. 2A shows a state in which the lid 1 is closed on the switch device portion 7, and FIG. 2B shows the lid 1 which is attached to the switch device portion 7 by pins 6 so as to be openable and closable. Indicates an open state. That is, a hand indicator 3 provided with an hour hand 3 and a minute hand 4 is arranged on the front side of the lid 1, and a liquid crystal display panel 5 is arranged on the back side of the lid 1. And the liquid crystal display panel 5
A first display unit 5a in which dot displays are arranged in a matrix of 5 rows and 35 columns to display characters and the like, and a time, telephone number and the like in which a 7-segment display is arranged in two columns by 12 digits. And a second display section 5b for displaying. On the upper surface of the switch device 7, a sheet switch 8 in which a number of key switches are arranged in a matrix is arranged.

FIG. 2 shows a circuit configuration of the present embodiment. An oscillation circuit 11 is a circuit that constantly sends out a signal of a constant frequency, and a frequency dividing circuit 12 divides the above signal to a predetermined frequency. The above is a circuit for sending it to the motor drive circuit 13 and the time counting circuit 18. The motor drive circuit 13 is a circuit that drives the step motor 14 in response to the transmitted signal, and the step motor 14 is driven by the motor drive circuit 13 to drive the wheel train mechanism.
The pointer 16 is moved via 15. The time adjustment mechanism 17
This is a mechanism that corrects the position of the pointer 16 via the wheel train mechanism 15.

The time counting circuit 18 counts the signal from the frequency dividing circuit 12 to obtain the current time, sends it to the CPU 20, and
This is a circuit for sending a day carry signal to the date counting circuit 19 every time 2 o'clock is counted. The date counting circuit 19 is a circuit that counts the date carry signal from the time counting circuit 18 to obtain a date and sends it to the CPU 20.

The CPU 20 is a circuit unit that sends control signals to each circuit unit to control them, and also processes and sends data from each circuit unit. The RAM 21 is a storage circuit that has a configuration described below and that exchanges data with the RAM 21 under the control of the CPU 20. The key input unit 22 is a circuit unit that includes the various key switches described above and other switches, and sends a corresponding key input signal to the CPU 20 when any one of them is operated. The power supply control circuit 24 is a circuit unit that receives a control signal from the CPU 20 and controls power supply to the display unit 25. The display buffer 26 stores the time sent from the CPU 20,
This is a buffer memory in which display pattern data related to a telephone number or the like is set. The display drive circuit 27 includes a display buffer
A circuit for selectively lighting a 7-segment display of the second display section 5b of the liquid crystal display panel 5 based on the display pattern data set in 26 to display time, telephone number, and the like. The display buffer 28 is composed of memory cells arranged in a matrix of 5 rows and 35 columns as shown in FIG.
Column X _1, X ₂ as shown in FIG each hole of the 35 columns, ...... X ₃₅
), Each memory cell is in the fifth row 35 of the first display section 5a.
It corresponds to each dot display in the column. In this display buffer 28, display pattern data relating to character data sent from the CPU 20 is set with five columns per character. The display drive circuit 29 is a circuit unit that displays the character data on the first display unit 5a based on the display pattern data set in the display buffer.

FIG. 4 shows the configuration of the RAM 21 described above. That is, RAM
21 is composed of a register unit R _E and the data bank storage unit M _D,
The register unit R _E and various registers are provided, also consists of a number of rows where the row address starting from the data bank storage unit M _D row address 1 are given respectively, each row character data storage section M _L And a numerical data storage unit _MN . Data bank storage unit M _D of each row 1 of the data, for example, the first telephone number data or the first schedule data is stored, the character data portion of the data in the character data storage section M _L up to 12 characters, for example, the name Etc. are stored (hereinafter,
The 12 letters from the direction the head of the sequentially first character, the second character, third character, ... hereinafter), the numerical data storage unit M _N
A numeric data portion of the data in the line, for example, a telephone number or the like, is stored with up to 12 numbers. In the register section _RE , a mode register M is a register for specifying a mode. When 0 is set, a data bank mode for displaying schedule data, telephone number data, etc. on the liquid crystal display panel 5 is specified, and 1 is set for the mode. When the time is set, a clock mode for displaying the current time and date on the liquid crystal display panel 5 is designated. Pointer P is a pointer for specifying by its row address each row of data bank memory unit M _D. Number register A is a register number of character data stored in the character data storage section M _L of the row that is specified by the pointer P is set. Register C
The number of characters in the character data stored in the character data storage section M _L of the row that is specified by the pointer P 6
At this time, the register is set to a value five times the number of characters (the value set in the character number register A). Storing data number register AT, in number of data or data bank information memory M _D stored in the data bank storage unit M _D, is already registers the number of rows that data is stored is set. The character pattern memory B is composed of memory cells arranged in a matrix of 5 rows and 60 columns as shown in FIG. 5 (hereinafter, the above 60 columns are arranged in columns B ₁ , B ₂ ... ... that B _60), a memory for storing a character pattern in a character per five rows of the character data of the character data storage section M _L of lines specified by the pointer P. Incidentally, as described above, since the following character pattern 12 characters in the character data storage section M _L of each row of data bank memory unit M _D is stored, 1-line database storage unit M _D is a character pattern memory B Thus, the character pattern data stored in the character pattern memory B is sent to the display buffer 28 in units of columns (that is, as 5-bit parallel data), and the third character pattern is stored in the character buffer. is set to one of the columns X ₁ to X ₃₅ as shown in FIG. (ie the line of the character pattern memory B display buffer 28
Line). The register N is a register which indicates in which column of the character pattern memory B the 5-bit parallel data set in the column X ₃₅ of the display buffer 28 as described above, for example, the character pattern memory When the 5-bit parallel data of column B ₆₀ of B is set in X _{35 of} display buffer 28, 60 is set in register N.

The register _{O P, Q, R, S} , T is the working register used in sweeping display of later.

Operation FIG. 6 is a general flowchart showing an outline of the operation of the present embodiment, and FIG. 7 is a data bank mode display process (step S
FIG. 8 is a flowchart showing in detail 5). FIG. 8 is a flowchart showing in detail the data bank mode key processing (step S15) in the above general flowchart. FIGS. 9 and 10 are accompanied by various key operations. This shows how the display of the liquid crystal display panel 5 changes. Hereinafter, operations in various states will be described with reference to these drawings.

(1) Operation Following First Key Operation When a predetermined time has elapsed after any key operation, power supply to the display unit 25 is stopped (see FIG. 2). Is stopped (see FIG. 9 (a)). That is, in this case, it is in a state of waiting for a key input (step S1). If there is any key input from any key, the process proceeds from step S1 to step S2, in which power supply to the display unit 25 is started, the data bank mode is set (step S3), and then the data bank mode is set. Is confirmed (step S4), and the process proceeds to the data bank mode display process of step S5, that is, the flow chart of FIG. And step
In S20, the line database storage unit M _D that is specified by the value of the pointer P (hereinafter, referred to as memory M _P) numerical data storage unit M _N numeric data stored in, for example, displays the telephone number buffer 26 And causes the second display section 5b to display it. Then, the memory M _P character data storage unit M _L number the number of character data stored in the register A
(Step S21), and it is determined whether the set value, that is, the number of characters is 6 or less (step S22). And
When the set value is 6 or less, sets each character pattern data of the character data stored in the character data storage section M _L of the memory M _P in the character pattern memory B, the character pattern thereon Each column data of memory B is 5
The data is sent to the display buffer 28 as bit parallel data, and is set in each column X ₁ , X ₂ ... Of the display buffer 28, and the character data is displayed on the first display unit 5a (step S23).
At this time, in the display buffer 28, 5 characters are required to display one character.
Since columns are used, and one character interval is given between characters, the first display section 5a displays, for example, as shown in FIG. 10 (a). After the above processing, the process proceeds to step S7 in FIG. 6, and it is determined whether or not a key operation is performed. If no key operation is performed, step S8 is performed.
Then, it is confirmed that a predetermined time has not yet elapsed since the data being displayed is displayed, and the process returns to step S4. Then, the same operation as described above is repeated (steps S5, S7, S
8, S4), if the above-mentioned fixed time has elapsed, step S8
From step S9 to stop the power supply to the display unit 25,
The display on the liquid crystal display panel 5 is no longer performed.
The process returns to step S1 to wait for the next key input (see FIG. 9).

Also, determining that at FIG. 7 step S22 described above, the number of characters in the data or message in the memory M _P is not below 6 characters, the set value of the number register A is 7,8, is either ...... 12 Then, the sweep display is started. That is, first, the process proceeds to step S24, and the character pattern related to the character data is set in the character pattern memory B. In this case, no space is provided between characters as shown in FIG. Then set to indicate whether the previously used which columns from the column B ₁ in 5 times the value or character pattern memory B values of characters register A into the register C (step S25), and the further step S26 the memory
Transferred to M _P message i.e. the character pattern memory B first column of the character pattern is set to B ₁ .about.B ₃₀ those are set to i.e. the first six characters of the character pattern data display buffer 28, the The columns are set in columns X _{1 to} X _35, and at this time, one column interval is provided between the characters. As a result, the first display section 5a has, for example, FIG.
The character data of six characters is displayed as shown in FIG. Next, in this state, the elapse of a predetermined time is waited, and it is confirmed that there is no key input during that time (steps S27, S28, S29), and 30 is set in the register N (step S30). the pattern data set in the column X ₃₅ stores the fact that what is set in the column B ₃₀ character pattern memory B. Then, the pattern data set in each column X _n (n is an integer of 1 to 35) in the display buffer 28 is shifted by one column to the left column, that is, the column X _n−1 (step S31). As a result, the first display unit 5a displays a state shifted leftward by one column from the previous display, and does not display the rightmost column (see FIG. 10 (b)). Next, it is confirmed that the set value of the register N, that is, 30 is divisible by 5, and the pattern data set in each column _Xn of the display buffer 28 is shifted one column to the left again (step S1).
S33). As a result, the first display unit 5a also performs the display shifted by one column to the left, and does not perform the display in the two rightmost columns. Next, an increment process for incrementing the register N by +1 is executed to set the value to 31 (step S3).
4), and displays a pattern corresponding to the right-most column of the register N is set to the column X ₃₅ of the display buffer 28 to the pattern data of the columns i.e. column B ₃₁ of the designated character pattern memory B by the first display unit 5a (Step S35). That is, on the right side of the first display section 5a, an interval is provided by one line between the first character and the sixth character, and the left fifth of the seventh character is displayed. After that, if a certain period of time has passed without any key input, step
The process proceeds to step S38 via S36, S37, and S36, and confirms that all characters to be displayed have not been completely displayed this time (step S38), and returns to step S31. Then, in step S31, the pattern data of each column _Xn of the display buffer 28 is shifted by one column in the same manner as described above.
In step 2, it is confirmed that the value of the register N, that is, 31 is not divisible by 5, and the process proceeds to step S34. Thereafter, the same operation as described above is performed (steps S35 to S38), and the process returns to step S31. The above operation is repeated, and the seventh, eighth,
,... Are displayed and the first, second, third,... Characters are not displayed, and a sweep display is performed. The rightmost column of each character is the rightmost column of the first display portion 5a. when displayed in the column with (that is, when the pattern data of the rightmost column of each character is set in the column X ₃₅ character pattern memory B), the step S31 the value of the register N is divisible by 5 S33 and Shifts to the left,
For this reason, in the first display section 5a, an interval is opened by one column between characters. As described above, when all the characters of the character data to be displayed this time are displayed, it is detected in step S38, and the process proceeds to step S7 in FIG.
After a certain period of time, the display stops, and the system enters a standby state waiting for the next key operation (steps S8, S9, S1).

(2) Operation for Changing Display Data As described above, when any key of the switch device section 7 is operated in a state where no display is made on the first display section 5a, the data bank mode is entered. in that data for the memory M _P that is indicated by the pointer P is to be displayed on the liquid crystal display panel 5, to display data other than the data being displayed on the liquid crystal display panel 5, the memory M _P While the data is being displayed, the up arrow mark key (key marked with ▲) or the down arrow mark key (key marked with ▼) of the switch device section 7 is operated. At this time, the operation is detected in step S7, and step S1
After 0 and S14, the process proceeds to the data bank mode key process of step S15, that is, the flow chart of FIG. And when the down arrow mark key is operated, the pointer to the increment processing of +1 P, if the pointer when led to the pointer P by the process instructs the unstored line database storage unit M _D P Is performed (steps S71 to S74), and when the up arrow mark key is operated, the pointer P is decremented by -1. If the value of the pointer P becomes 0 by this processing. sometimes, already row address of those row addresses largest of the rows storing data in the data bank storage unit M _D pointer P
(Steps S75 to S78).

After the above processing, the flow returns to step S4, the data in the memory M _P which is to be indicated by the new pointer P in the same manner as described above is displayed on the liquid crystal display panel 5 (step S5 to S8). Note the first display unit when the number of characters of the character data of the character data storage section M _L of the memory M _P In this case is 6 or less
The display of 5a is a fixed display, and a display of 7 or more is a sweep display (steps S20 to S38). Further, when the down arrow mark key and the up arrow mark key are further operated during the display, the data newly designated by the pointer P is displayed as described above, but the operation is not performed for a predetermined time. At this time, nothing is displayed on the liquid crystal display panel 5 (steps S7 to S9, S1).

(3) As operation of the aforementioned case of stopping the sweep display, when the number of characters of the character data of the character data storage section M _L of the designated memory M _P is 7 or more by the pointer P, the the first display unit 5a Each character data is sequentially displayed in a sweep manner. During the sweep display, when it is desired to fix the display and check the character data, the right arrow mark key of the switch device section 7 (the key marked with). Or, continue to operate the left arrow mark key (the key with the mark). At this time, the operation is detected in step S37 during the sweep display process, and the process waits until the operation is not performed in step S41 via step S39.
At this time, the sweep display is interrupted on the first display unit 5a, and the one displayed at that time is fixedly displayed. In order to end the fixed display and return to the sweep display, the operation of the right arrow mark key or the left arrow mark key during operation is stopped. At this time, the operation is detected in step S41 and the elapse of one second is waited. (Steps S42, S43), and then
Returning to step S38, the sweep display is performed again (steps S31 to S38).

(4) Operation at the time of sequential progress display As described above, the fixed display is performed during the display, and thereafter, the sweep display which is the continuous progress display is not performed. In order to successively display the characters on the left side sequentially, the left arrow mark key ヲ is operated one second after the stop of the operation of the right arrow mark key or the left arrow mark key in the above-mentioned fixed display. In this case, the process proceeds to steps S43 and S44, and in step S45, it is detected that the left arrow mark key has been operated.
In S46, the whole of the last character still to be displayed is the first
Detecting that it is not displayed on the display section 5a (i.e. detects that no as yet in the column X ₃₅ of the display buffer 28 at the end of the right end pattern data set of characters), the next step S47 move on. And this step S
In 47, it sets the integer part of the quotient obtained by dividing the value of the register N in 5 to register O _P. The integer is the first display unit
In 5a, the character displayed at the rightmost position is the number of the character data in which the entire character is displayed (only part of the character may be displayed at the left and right ends). Is a value indicating whether the characters are After processing in step S47, the set of those five-fold the value obtained by adding 1 to the value set in the register O _P in the processing in the register Q (step S48). In this case, the value set in the register Q is set in the column of the character pattern memory B in the rightmost end pattern of the character next to the character whose entire character is displayed on the first display unit 5a. Is a value indicating whether the Next, in step S49, it is determined whether the value obtained by dividing the value of the register N by 5 is an integer.
That is, in the first display unit 5a, it is determined whether the entire right or a part of the single character is displayed at the right end. When the entire character is displayed, only one line of pattern data of each column _Xn of the display buffer 28 is provided in the display buffer 28 and the first display unit 5a in order to provide an interval of one line after the character. After shifting to the left, the process proceeds to the next step S51. If the entire character is not displayed, the process directly proceeds from step S49 to step S51. In step S51, an increment process for incrementing the register N by +1 is performed, and then the column number in the character pattern memory B of the pattern data to be set in the column X ₃₅ of the display buffer 28 is specified, and each column X _{n of the} display buffer 28 is specified. Is shifted by one column to the left column (step S52), and then the column of the character pattern memory B specified in step S51, that is, the column of the character pattern memory B specified by the register N set the pattern data to the register X ₃₅ in the display buffer 28, displaying a pattern according to the pattern data in the rightmost column of the first display section 5a (step S53). Next, whether the value of the register N has become equal to the value of the register Q, that is, the entire character (left arrow mark) next to the character displayed on the right end of the first display section 5a before the operation of the above-mentioned left arrow mark key If a part of one character is displayed on the right end of the first display section 5a before the key operation, the entire character is displayed on the right end of the first display section 5a. If the above state has not been reached, the above steps are taken until the state is reached.
The processing of S49 to S54 is repeated. Then, when the value of the register N becomes equal to the value of the register Q and the state described above is reached,
The process proceeds from step S54 to steps S42 and S43, and enters a standby state for one second. By the above processing, the display of the first display unit 5a advances to the left by one character, and a new character is additionally displayed at the right end (however, a part of one character is already displayed at the right end). If so, the entire character is displayed.) For example, when the left arrow mark key is operated in the state of FIG. 10 (e), the state becomes as shown in FIG. 10 (f), and FIG.
(D) when the left arrow mark key is operated in the state of
It becomes like.

When the left arrow mark key is further operated in the standby state for one second, the steps S43 to S4 are performed.
The process proceeds to steps S45 and S45, and the display of the first display unit 5a further advances to the left by one character, and another new character is additionally displayed at the right end (steps S46 to S54). Hereinafter, when the left arrow mark key is sequentially operated within one second, the display of the first display unit 5a sequentially advances to the left by one character in the same manner as described above.

In the above display state, when the operation of the left arrow mark key is stopped for one second or more, the process proceeds from step S42 to step S38, and returns to the above-described sweep display.

(5) Operation at the time of sequential backward display The standby state for one second after the above-mentioned fixed display (step S4
If the right arrow mark key is operated in the one-second standby state (steps S42 and S43) during the above-described sequential forward display, the process proceeds to step S55 via steps S43, S44 and S45, and the operation proceeds to step S55. Is detected, and the process proceeds to step S56. In this step, it is checked whether the value of the register N is 30 or less. If the value is 30 or less, the first to sixth characters are displayed on the first display portion 5a. Since a new character is not displayed on the left end of the first display section 5a, the step S42 is performed without performing the backward display.
When the value of the register N is more than 30 and equal to or more than 31, the process proceeds to step S57, and it is determined whether the value obtained by dividing the value of the register N by 5 is an integer (that is, the right end of the first display unit 5a). Check if the characters displayed in are displayed as one character.) If the value is an integer, a value obtained by subtracting 29 from the value of the register N is set in the register R (step S58). If the value is not an integer, a value obtained by subtracting 28 from the value of the register N is set in the register R. (Step S59). That is, the number of columns in the character pattern memory B where the pattern data displayed on the leftmost side is set in the first display unit 5a (that is, the display buffer
The number of columns in the character pattern memory B in which the pattern data set in the 28 columns X ₁ or X ₂ are set is set in the register B. When the processing in step S58 or S59 is completed, the integer part of the value obtained by subtracting 1 from the value of the register N and dividing it by 5, that is, the character (one character displayed at the right end of the first display unit 5a) The character number of the character displayed to the left of one character (including the character not displayed in its entirety) (that is, the character displayed second from the right) (the number of the character from the beginning of the character data being displayed) Number)
Is set in the register S (step S60). Next, a value obtained by multiplying the value of the register S by five, that is, the number of columns in the character pattern memory B in which the pattern data at the right end of the character whose character number is set in the register S is set in the register T (step S61). ). Thereafter, in step S62, as in step S57, it is determined whether the quotient obtained by dividing the value of the register N by 5 is an integer, and it is determined whether the entire right is displayed at the right end of the first display unit 5a. If the whole is not displayed, go directly to step S65, but
When the entire character is displayed, each column of the display buffer 28 is provided so as to provide a space between the character displayed on the left end of the first display portion 5a and the character newly displayed on the left side thereof. shifting the pattern data X _n to the right by each one column (step S63), the pattern data set in the wake no row X ₃₅ in this shift, changed to column number is smaller by one in the character pattern memory B This is set in the register N (step S64), and then the process proceeds to step S65. In this step S65, the pattern data of each column _Xn of the display buffer 28 is shifted by one column to the right column, and the display of the first display unit 5a is shifted by one column to the right. Thereafter, it is set in the register N that the pattern data of the column X ₃₅ has been changed to that of the column having the column number smaller by 1 in the character pattern memory B due to the shift, and set at the leftmost position of the column X. The pattern data to be performed is a character pattern memory B
The fact column number is of small columns only one set in the register R in (step S67), the sequence X ₁ column number of the pattern data display buffer 28 in the character pattern memory B designated by the register R It is set (step S68). Thus, the pattern specified by the register R is displayed in the rightmost column of the first display section 5a. Thereafter, in step S69, it is determined whether the value of the register N has become equal to the value of the register T, that is, the character (one character displayed from the right end on the first display unit 5a before the operation of the right arrow mark key). Is counted at the right end of the first display unit 5a. (This is because whether a new character is displayed at the left end of the first display unit 5a or This is equivalent to checking whether characters that have been partially displayed have been entirely displayed), and if such a state has not yet been reached, the process returns to step S62.

Hereinafter, the same processing (steps S62 to S69) is repeated, and when the value of the register N becomes equal to the value of the register T and the first display unit 5a reaches the above-described display state, the process proceeds to step S6.
Proceed from step 9 to step S42 and wait for one second to elapse (step
S42, S43). By the above processing, the display of the first display unit 5a is retreated to the right by one character, and one new character is additionally displayed at the left end (however, a part of one character is displayed at the left end). If so, the entire character is displayed). For example, when the right arrow mark key is operated in the state of FIG. 10D, the state becomes as shown in FIG. 10E, and when the right arrow mark key is operated in the state of FIG. ).

If the right arrow mark key is further operated before the elapse of one second, the steps S43 to S44, S4
Proceeding to 5, S55, the display of the first display unit 5a is further retreated to the right by one character, and a new character is additionally displayed at the left end by one more character (steps S56 to S69). When the right arrow mark keys are sequentially operated within one second thereafter, the display on the first display unit 5a is sequentially moved to the right by one character in the same manner as described above. When the operation of the right arrow mark key is stopped for one second or more in the above display state, the process proceeds from step S42 to step S38 to return to the above-described sweep display.

When the right arrow mark key is operated during the one-second standby during the sequential progress display, the sequential reverse display is performed (steps S43, S44, S45, S55 to S69), and conversely, during the sequential reverse display. When the left arrow mark key is operated during the one second standby, the progressive display is performed (step S4).
3, S44, S45-S54).

(6) Other operations When the mode key is operated to change the mode during the execution of the data bank mode display process (step S5), these are detected in steps S29, S39, S44, etc.
At 10, it is confirmed that the mode key has been operated, and the mode is switched to the clock mode (steps S11, S13). Thereafter, as shown in FIG. 9 (c), the liquid crystal display panel 5
Displays the current time and date (steps S6 to S8, S
4) After a certain period of time, the display is stopped as shown in FIG. 9 (a) (step S9) and a standby state is set (step S9).
S1). When the right arrow mark key or the like is operated during the clock mode display processing, the process proceeds to steps S7, S10, and S14, where time mode key processing such as clock correction is performed, and when the mode key is operated. Are steps S7, S10, S11
The mode is switched to the data bank mode (step S12).

The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the present invention.

[Effects of the Invention] As described in detail above, the present invention allows the sweep display to be stopped and changed to the fixed display by operating only the display control key, and in the fixed display, only one character is sequentially displayed. Since the present invention relates to a data display control device capable of displaying display data in a state where the movement of display data is advanced or retracted, even if the data is relatively easy to read in the sweep display, it may be misread. It is possible to provide a data display control device capable of displaying data in a manner that does not frequently occur.

[Brief description of the drawings]

FIG. 1 is a diagram showing the appearance of one embodiment of the present invention, FIG. 2 is a diagram showing the circuit configuration of the embodiment, FIG. 3 is a diagram showing the configuration of the display buffer 28 in FIG. 5 is a diagram showing the configuration of the RAM in FIG. 2, and FIG. 5 is a character pattern memory B in FIG.
FIG. 6 is a general flowchart showing an outline of the operation of this embodiment, FIG. 7 is a flowchart showing the data bank mode display processing in FIG. 6 in detail, and FIG. 8 is a flowchart in FIG. FIG. 9 and FIG. 10 are flowcharts showing the details of the data bank mode key processing, and FIG. 9 and FIG. DESCRIPTION OF SYMBOLS 1 ... lid body, 2 ... pointer display part, 3 ... hour hand, 4 ... minute hand, 5 ... liquid crystal display panel, 5a ... 1st display part, 5b ...
Second display unit, 7: switch device unit, 11: oscillation circuit,
12 …… Dividing circuit, 13 …… Motor drive circuit, 14 …… Step motor, 15 …… wheel train mechanism, 16 …… Pointer, 17 …… Time correction mechanism, 18 …… Time counting circuit, 19 …… Date Counting circuit, 20
... CPU, 21 ... RAM, 22 ... key input unit, 24 ... power supply control circuit, 25 ... display unit, 26, 28 ... display buffer,
27, 29 ... display drive circuit, M ... mode register, A ...
… Character number register, AT …… Storage data number register, P…
... Pointer, B ... Character pattern memory, M _D ... Data bank storage, M _L ... Character data storage, M _N ... Numeric data storage, R _E ... Register, M _P ... Memory.

Claims (1)

(57) [Claims] A data storage means for storing data consisting of a plurality of characters; a reading means for reading data from the data storage means; and a plurality of characters of the data read by the reading means from one of a display device. Moving display control means for continuously moving and displaying to the other, a display control key, and during moving display of data by the moving display control means, when the display control key is operated, the moving display is stopped and data is displayed. A stop display control means for stopping and displaying the data, and after the stop display control means displays the stop data, each time the display control key is operated, the stopped display data is moved and displayed by one character, and then the one character movement for stop display is performed. Display control means; and restart means for restarting the continuous movement display when the control display key is not operated for a certain period of time in a state where data is stopped and displayed. And a data display control device.