JP2798990B2 - Non-volatile memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial application field) The present invention relates to a nonvolatile memory device having a gate electrode structure of two or more layers.

(Prior Art) Conventionally, a one-transistor, one-cell rewritable nonvolatile memory is an ultraviolet erasable EPROM (Erasable Programmable).
Read Only Memory).

Hereinafter, the structure of the ultraviolet erasing EPROM will be described with reference to the drawings.

4 (a) and 4 (b) show a conventional ultraviolet erasing type EPRO.
FIG. 4 is a cross-sectional view showing the structure of M.

As shown in FIG. 4A, a P-type silicon substrate (40
1) Drain diffusion layer (402) and source diffusion layer (403)
Are formed. A gate insulating film (404) is formed on a P-type silicon substrate (401) between the drain diffusion layer (402) and the source diffusion layer (403), and a floating gate is formed on the gate insulating film (404). An electrode (405) is formed. Furthermore, an insulating film (4) is formed on the floating gate electrode (405).
A control gate electrode (407) is formed through the layer (06). An interlayer insulating film (408) is formed so as to cover these, and a bit line (409) connected to the drain diffusion layer (402) via a contact hole is formed thereon.

The operation mechanism of this ultraviolet erasing EPROM is as follows. Writing of information is performed by the control gate electrode (407).
By applying a high voltage to the gate electrode and the drain diffusion layer (402), thermal electrons are generated in the channel, injected and accumulated in the floating gate electrode (405), and set to the "0" state. Information is erased by irradiating the device with ultraviolet light.
5) Apply energy to the electrons inside and release them to the substrate or control gate to set them to the "1" state.

As the miniaturization of the element progresses, the distance between the source and the drain becomes shorter and the channel is shortened. Therefore, when a high voltage is applied to the drain diffusion layer during the writing operation of the cell, punch-through easily occurs. When a high voltage is applied to the drain diffusion layer during a write operation, the floating gate
Even if the control gate voltage is zero, the floating gate voltage rises with the drain voltage due to the capacitive coupling with the drain diffusion layer, causing problems such as leakage current flowing to unselected cells.

Further, an EPROM having an offset gate electrode structure is conventionally known as a structure for preventing these problems.

This structure is shown in FIG. 4 (a) as shown in FIG. 4 (b).
Similarly, a drain diffusion layer (402) and a source diffusion layer (403) are formed in a P-type silicon substrate (401), and a P between the drain diffusion layer (402) and the source diffusion layer (403) is formed.
Gate oxide film (404a) (404
b) is formed. A floating gate insulating film (405) is formed on the oxide film (40b), and an insulating film (406) is formed on the floating gate electrode (405). It is formed to cover from (406) to the gate oxide film (404a). An interlayer insulating film (408) is formed on these entire surfaces, and the interlayer insulating film (408) has a structure in which a contact hole is provided on a drain diffusion layer (402) and a bit line (409) is connected. .

In such a structure, since there is a channel portion controlled only by the control gate, it is possible to prevent punch-through, leak current from flowing to unselected cells, and the like.

However, in the structure described above, the element size is inevitably increased, and there is a problem in miniaturization.

(Problems to be Solved by the Invention) The above-described conventional nonvolatile memory device has a problem that a punch-through phenomenon, a malfunction due to a leak current of an unselected cell occurs, or a difficulty in miniaturization.

SUMMARY OF THE INVENTION The present invention has been made in consideration of the above-described problem, and an object of the present invention is to provide a miniaturized nonvolatile memory device having a high punch-through withstand voltage, a small leakage current at the junction surface, and a miniaturized structure.

[Means for Solving the Problems] To achieve the above object, in the present invention, a first impurity region formed on a surface of a semiconductor substrate, a groove provided on the semiconductor substrate, A second impurity region formed at a groove bottom of the groove; and a first impurity region formed on a region between the side end of the first impurity region and the side end of the groove in the semiconductor substrate. An insulating film, a first gate electrode formed on the first insulating film, a second insulating film provided on the first gate electrode, and a second insulating film provided on at least a surface of the groove. 3 is a non-volatile memory device comprising: an insulating film of No. 3; and a second gate electrode formed from the second insulating film to a surface on the third insulating film.

(Operation) According to the nonvolatile memory device of the present invention, the groove is provided in the semiconductor device, and the offset gate electrode portion is formed in the groove.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is an ultraviolet erasing type EP according to a first embodiment of the present invention.
FIG. 2 is a cross-sectional view showing a cell structure of a ROM.

As shown in FIG. 1, a drain diffusion layer (102) of a memory cell, a groove (103) and a source diffusion layer (104) formed in the groove bottom are provided on the surface of a P-type silicon substrate (101). . A first gate oxide film (105) is formed on the surface of the silicon substrate from the end of the drain diffusion layer (102) to the top of the groove, and the floating gate electrode (106) is formed via the first gate oxide film (105). Are formed. A second gate insulating film (107) is formed on the floating gate electrode (106), and a third gate insulating film (117) is formed on the side wall of the trench, and the second and third gate insulating films (107) are formed. A control gate electrode (108) is formed via (107) and (117). A CVD oxide film (109) is formed to cover them and BPSG
A film (110) is formed, and a contact hole is provided in the BPSG film (110) on the drain diffusion layer (102), and the bit line (111) is connected to the drain diffusion layer (102).

In such an EPROM device, since there is a channel portion controlled only by the control gate electrode in the offset gate electrode, it is possible to prevent a leak current of an unselected cell. At this time, since the offset gate electrode portion is formed in the groove provided in the substrate in the vertical direction, the length of the channel portion controlled only by the control gate electrode can be set independently of the element area. In addition, the length of the channel can be made sufficiently long, and cell leakage can be further prevented.

Further, in this structure, even if the floating gate length is shortened in order to increase the element density, the offset gate length can be set to any length in the depth direction of the groove, so that it does not become a short channel and cell leak can be completely prevented. .

As described above, a highly reliable nonvolatile memory device which can be miniaturized can be obtained.

FIG. 2 is a sectional view showing an EPROM cell structure according to a second embodiment of the present invention.

This EPROM cell has the same structure as that of the first embodiment, and as shown in FIG. 2, a drain diffusion layer (202), grooves (203a), (203) are formed on the surface of a P-type silicon substrate (201).
b), the source diffusion layers (204a) and (204b) are provided in the groove, and the groove (203) extends from the end of the drain diffusion layer (202).
First gate oxide films (205a) and (205b) are formed over the upper ends of (a) and (203b), and the floating gate electrode (206) is formed through the first gate oxide films (205a) and (205b).
a) and (206b) are formed. Further, a second gate insulating film (207a) is formed on the floating gate electrodes (206a) and (206b).
(207b) is formed and a third gate insulating film (21
7a) (217b) This second gate insulating film (207a) (207b)
Control gate electrodes (208a) and (208b) are formed thereon. Here, the drain diffusion layer (202) is shared by two adjacent floating gate electrodes (206a) and (206b),
In addition, the source diffusion layers (204a) and (204b) in the trench have a structure shared by different control gate electrodes different from each other adjacent to the floating gate electrodes (206a) and (206b). A CVD oxide film (2) covers these floating gate electrodes (206a) and (206b) and the control gate electrodes (208a) and (208b).
09) is formed, and a BPSG film (210) is further formed on the entire surface. In the BPSG film (210), a contact hole is provided on the drain diffusion layer (202) and a bit line (21) is formed.
1) is connected to the drain diffusion layer (202).

In the EPROM device according to the second embodiment, in addition to the effect of the first embodiment, the source and drain diffusion layers have a structure shared by two different gate electrodes adjacent to each other. An effect that can increase the capacity can be obtained.

FIG. 3 shows an electrically erasable EEPROM (Electro-Erasable Memory).
FIG. 3 is a cross-sectional view showing a cell structure when used in an ectrically erasable PROM).

A source diffusion layer (30) is formed on the surface of a P-type silicon substrate (301).
2), the trenches (320a) and (320b), the drain diffusion layers (303a) and (303b) are provided in the grooves, and the source diffusion layers (30
First gate oxide films (304a) and (304b) are formed from the end of 2) to the upper ends of the grooves (320a) and (320b), and the first gate oxide films (304a) and (304b) Thus, floating gate electrodes (305a) and (305b) are formed. Further, a second gate insulating film (308a) (308b) is formed on the floating gate electrodes (305a) (305b), and a third gate insulating film (315a) (315b) on the groove side wall and the second gate insulating film (308a)
Control gate electrodes (309a) and (309b) are formed on (308b). Tunnel oxide films (306a) (306b) are formed on the side of the source diffusion layer (302) on the side walls of the floating gate electrodes (305a) (305b). This tunnel oxide film (306a) (306b) is connected to the floating gate (305a) (305
An erase gate electrode (307) is formed so as to be sandwiched between b) and b). The erase gate electrode (307) is common to the memory cells in the array, and is electrically connected to the source diffusion layer (302) so as to function also as a source electrode. Further, a bit line (312) is formed on the erase gate electrode (307).
And a CVD oxide film (310a) (310b) is formed to cover the floating gate electrodes (305a) (305b) and the control gate electrodes (309a) (309b), and the entire surface except for the bit line (312) is formed. A BPSG film (311) is formed.

In such a "non-volatile memory device", a necessary potential is applied to the erase gate electrode, and charges can be extracted from the floating gate to the erase gate through the tunnel oxide film, so that the data can be electrically rewritten. .

[Effects of the Invention] As described above in detail, according to the offset gate electrode cell structure of the present invention, a highly reliable nonvolatile memory device that can be miniaturized can be obtained.

[Brief description of the drawings]

FIG. 1 is a sectional view showing an EPROM cell structure according to a first embodiment of the present invention. FIGS. 2 and 3 are sectional views showing EPROM cell structures according to a second and a third embodiment of the present invention, respectively. FIG. 3 is a sectional view showing an EEPROM cell structure according to a third embodiment of the present invention, and FIGS. 4A and 4B are sectional views showing a conventional EPROM cell structure. 101,201,301,401 ... P-type silicon substrate, 102,202,302,402 ... Drain diffusion layer (first impurity region), 103,203a, 203b, 320a, 320b ... Groove, 104,204a, 204b, 303a, 303b, 403 ... Source diffusion layer ( Second
, 105, 205a, 205b, 304a, 304b, 404a, 404b... First gate oxide film (first insulating film), 107, 207a, 207b, 308a, 308b, 406. Films (second insulating films), 106, 206a, 206b, 305a, 305b, 405... Floating gate electrodes (first gate electrodes), 117, 217a, 217b, 315a, 315b. a, 208b, 309a, 309b, 407 ... Control gate electrodes (second gate electrodes).

Claims (1)

(57) [Claims] A first impurity region formed on a surface of the semiconductor substrate; a groove provided on the semiconductor substrate; a second impurity region formed on a groove bottom of the groove; A first insulating film formed on a region between a side end of the first impurity region and a side end of the trench, and a first gate electrode formed on the first insulating film And a second insulating film provided on the first gate electrode;
A third insulating film provided on at least a surface of the groove;
A second gate electrode formed from the second insulating film to a surface on the third insulating film.