JP2798154B2 - System control unit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a system control device, and more particularly to a system control device that outputs a high-speed or low-speed system clock and a mode signal according to the system clock. BACKGROUND ART As a system control device for controlling a system such as a personal computer, there is a system control device that controls a circuit in a system by switching between a low-speed mode based on a low-speed clock and a high-speed mode based on a high-speed clock. According to this system controller,
Even if a peripheral circuit for low-speed operation is included in the system, it can be operated by switching the mode to the low-speed mode. [Problems to be Solved by the Invention] However, according to this system controller, when a transition from the high-speed mode to the low-speed mode is required, if there is a mistake in the program or an erroneous reading of the program, the high-speed mode is continued as it is. Therefore, there is a disadvantage that data read from the high-speed peripheral circuit and data read from the low-speed peripheral circuit compete on the bus. SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a system control device in which data does not conflict on a bus even if a program is erroneously read or a program is erroneously read. Means for Solving the Problems In order to achieve the above object, the present invention provides a system control for controlling a system including a system controller and a peripheral circuit connected to a bus based on a clock signal of a predetermined frequency. In the apparatus, a system clock generating means for generating a high-speed or low-speed system clock by dividing an external clock, and the system clock generating means based on a clock speed change instruction in a program read from an external program memory. Control means for generating a high-speed or low-speed system clock and outputting a high-speed or low-speed mode signal corresponding to the high-speed or low-speed system clock from an independent mode signal output terminal to the peripheral circuit. To provide a system control device. [Operation] When a clock is inputted from the outside, the control means decodes the program in the storage means and determines the speed of the system clock. When the clock speed is determined, the system clock generation means is controlled to generate a high-speed or low-speed system clock according to the determined speed. A mode signal representing the currently executed mode in the high-speed mode or the low-speed mode is output. By outputting this mode signal,
Since the hardware can know the mode currently being executed, even if a low-speed peripheral circuit is operated due to, for example, an error in a program or an erroneous read of the program, the high-speed mode signal stops the operation, and as a result, bus contention occurs. Can be avoided. Embodiment Hereinafter, a system control device of the present invention will be described in detail. FIG. 1 shows an image display device to which a system control device (CPU) 1 of the present invention is applied, and mainly controls a video display controller 2, a video color encoder 3, and a programmable sound generator 4. CPU1 is RO
Predetermined control is performed based on the program of M5, and data and calculation results are temporarily stored in the RAM 6 accordingly. The video display controller 2 reads out image data according to the story from the video RAM 7 and supplies it to the video color encoder 3 under the control of the CPU 1 which decodes a program such as a video game stored in the ROM 5. The video color encoder 3 to which the image data has been input outputs an RGB analog signal or a video color signal (including a luminance signal and a color difference signal) created by matrix conversion of the RGB analog signal based on the internal color data. Also, the programmable sound generator 4 receives an input via the CPU 1.
Outputs analog sound signals as left and right stereo sounds based on the contents of ROM5. The video color signal output by the video color encoder 3 is supplied to the television 9 as a composite signal via the interface 8, and the RGB analog signal is directly transmitted to the CRT of the television 9 used as a dedicated monitor device via the interface 10. Given. On the other hand, the left and right analog sound signals are supplied to the speakers 12a and 12b via the amplifiers 11a and 11b to generate sound. FIG. 2 shows the CPU 1 and the programmable sound generator 4. The CPU 1 has an instruction register 20,
Instruction decoder 21, bus interface register 22, arithmetic logic unit (ALU) 23, register set 24, mapping register 25, chip enable decoder 26, timing / control unit 27, input / output port 28, timer 29, interrupt request register 3
0, an interrupt disable register 31, and the like. Hereinafter, each will be described. (1) Instruction register 20 The instruction register 20 fetches the instruction code read in the instruction fetch cycle. (2) Instruction decoder 21 Executes a sequence determined according to the output of the instruction register 20, an interrupt input from a peripheral circuit, or a reset input. Also, it controls a branch instruction that changes the flow of the program based on information in a status register described later. (3) Bus interface register 22 B-bus 32 and U-bus 33 and external data buses D0 to D7
Control the mutual data transfer. The B-bus 32 connects the ALU 33 to the register set 24, and the U-bus 33 connects to internal peripheral circuits. In addition, an L-bus 34 for transferring the lower 8 bits of the logical address and an H-bus 35 for transferring the upper 8 bits of the logical address are provided. L-bus 34
Is connected to a logical address low register 48, and the H-bus 35 is connected to a logical address high register 49. (4) ALU23 A register 36 and B register which are temporary registers
37 and perform all arithmetic and logical operations. One or two pieces of data are taken into registers 36 and 37 of A and B, operated by a control signal of the instruction decoder 21, and the result is sent to one of the B-bus 32, L-bus 34 and H-bus 35. Output. (5) Register set 24 The register set has the following 8-bit registers (ten). (A) Accumulator 38 When the memory operation flag T of the status register described later is 1, the accumulator 38 is a general-purpose register that is the center of arithmetic and logical operations. The data here is input to the ALU 23, and the operation result is stored here. It is also used for data transfer between memories and between memory and peripheral circuits.When executing the block transfer instruction described in the following operation, the data at that point is saved to the stack of RAM6 and the length lower-order data is fetched to obtain the block length. Used for counting. (B) X register 39 and Y register 40 These are general-purpose registers mainly used for index addressing. When the memory operation flag T is "1", the X register 39 is used to designate the address of the zero page of the memory which is the operation destination. When the block transfer instruction is executed, the data at that time is stored in the RAM6. After saving to the stack, the lower data of the source address is stored. On the other hand, the Y register 40 stores the lower address of the destination address after saving the data at that time to the stack of the RAM 6 when executing the block transfer instruction. (C) Program counters 41 and 42 A 16-bit up counter is constituted by the upper 8-bit program counter 41 and the lower 8-bit program counter 42. It is automatically incremented by the execution of an instruction, and specifies the address of the next instruction or operand to be executed. This content is saved to the stack of the RAM 6 when executing a subroutine instruction, when an interrupt occurs, or after executing a software interrupt instruction. (D) Stack pointer 43 Designates the lower 8 bits of the highest address of the empty area of the stack of RAM6, decrements after pushing data on the stack, and is incremented before pulling. If the upper byte is, for example, 21H, the stack area is
This is a logical address, which is 256 bytes from address 21FF to address 2100. (E) Source high register 45, destination high register 46, length high register 47 Functions when a block transfer instruction is issued. Source high register 45 specifies the source address along with the contents of X register 39 and provides the upper byte. Destination high register 46 specifies the destination address along with the contents of Y register 49 and provides the upper byte. Length high register 47 is accumulator 38
Is provided as the lower 8 bits, and the upper 8 bits of the down count are provided, and the transfer block length is counted in byte units. (6) Mapping register 25 This is composed of eight registers each having an 8-bit configuration.
Converts a logical address of bits to a physical address of 21 bits. It is selected by the upper three bits of the H-bus 35. (7) Chip enable decoder 26 decodes the upper 11 bits of the physical address and outputs a chip enable to the following peripheral circuits. Chip enable for RAM 6 ▲ チ ッ プ Chip enable for video display controller 2 ▲ ▲ イ ネ ー ブ ル Chip enable for video color encoder 3… ▲ チ ッ プ Chip enable for programmable sound generator 4… ▲ チ ッ プ Chip enable for timer 29… ▲ ▼ Chip enable for input / output port 28 …… ▲
▼ Chip enable for interrupt request register 30 and interrupt disable register 31... (8) Timing / control section 27 Connected to the following terminals. (A) ▲ ▼ terminal Outputs the read timing signal in the read cycle. (B) ▲ ▼ terminal Outputs a write timing signal in a write cycle. (C) ▲ ▼ terminal Outputs a synchronization signal of “H” during the instruction fetch cycle and “L” during system setting. (D) ▲ ▼ terminal When the NMI input changes from “H” to “L”, a non-maskable interrupt occurs. When the program terminates the instruction being executed, it reads the lower address from the FFFC address and the upper address from the FFFD address with a logical address and makes a subroutine call. (E) ▲ ▼ terminal and ▲ ▼ terminal The corresponding bit of the instant destination register 31 is “0” and the status register 44
When the corresponding bit of “” is “0” and the input of “▲” becomes “L” level, the lower address is read from the address FFF8 and the upper address is read from the address FFF9 as a logical address, and a subroutine call is performed. At this time, the corresponding bit of the status register is set, and the other corresponding bits are reset. The other corresponding bits of the interrupt destination register 31 are "0" and the status register
When the corresponding bit of 44 is “0” and the input of ▼ becomes “L” level, a lower address is read from address FFF6 and an upper address is read from address FFF7 as a logical address, and a subroutine call is performed. At this time, the corresponding bit of the status register 44 is set, and the other corresponding bits are reset. (F) ▲▲ terminal When the RESE input becomes “L” level, the program starts by reading the lower address from the address 001FFE and the upper address from the address 001FFF as the physical address. (G) RDY terminal When the RDY input changes from “L” to “H”, the CPU 1 starts operating. (H) SX terminal This is the system clock terminal, which outputs the complementary signal of the system clock. (Iii) OSC1 pin Input an external clock. (V) BA1 to EA3 terminals These are the input terminals for testing CPU1. (R) HSM terminal "H" in high-speed mode (21.47727MHz / 3)
Outputs "L" in low-speed mode (21.47727MHz / 12). (9) I / O port 28 Connected to terminals below. (B) K0 to K7 pins These are input ports, and addresses 1FF000 to 1FF3 in physical addresses
When a read cycle is executed for address FF, the data at this pin is read. (B) 0-7 This is an output port with a latch.
When a write cycle is executed for addresses 1FF3FF, data is output to this terminal. (10) Timer 29 Connected to test input terminal ▲ ▼ of CPU1 and
The timer signal is output via the bus 33. (11) Interrupt request register 30 When "1", the input of the ▲ ▼ and ▲ ▼ terminals is “L”, two bits, and when “1”, one bit for generating a timer interrupt request, a total of three bits, It has five unused bits and can only be read. (12) Interrupt disable register 31 When "1", 2 bits for disabling the interrupt request of the ▲ ▼ and ▲ ▼ terminals, and when “1”, 1 bit for disabling the interrupt request by the timer interrupt, a total of 3 Bits and five unused bits. Hereinafter, the operation of the present invention will be described. (1) High-speed mode When an external clock of 21.47727 MHz is input from the OSCI terminal connected to the timing / control unit 27 shown in FIG. 2, the program stored in the ROM 5 is decoded and the high-speed mode is determined. Based on this judgment, CSH (Chang
e Speed High) instruction is executed and the high-speed mode is set. In high-speed mode, an external clock of 21.47727 MHz
The frequency is divided and the system clocks S ₁ , S ₂ , S ₃ shown in FIG. ₃ (7.
16MHz). At the same time, the high-speed mode signal “1” is output from the timing / control unit 27 via the HSM terminal. As a result, the video display controller 2, the video color encoder 3, the programmable sound generator 4, and the like connected to the CPU 1 are controlled for high-speed operation. The system clocks S ₁ , S ₂ , and S ₃ are output from terminals SX as complementary signals. From the rise of the system clock S ₁ to the next rising becomes the one bus cycle, the instruction execution cycle is defined for each instruction of this one bus cycle as a basic bus cycle. (2) Low speed mode 21. From the OSCI pin by the CSL (Change Speed Low) instruction.
When an external clock of 47727MHz is input, the frequency is divided by 1/12.
As a result, the system clocks S ₁ , S ₂ , S ₃ (1.
79MHz) is created and output as a complementary signal from terminal SX. At the same time, a low-speed mode signal “0” is output from the HSM terminal. (3) Mode switching FIG. 5 shows switching between the high-speed mode and the low-speed mode.
It is assumed that an instruction CSH for setting the processing speed of the CPU 1 to the high-speed mode, an instruction NOP for no operation, and an instruction CSL for setting the processing degree of the CPU 1 to the low-speed mode are generated at the illustrated timing. At the start of the generation of the instruction CSH, the operation mode is the low-speed mode. The system clocks S ₁ , S ₂ , and S ₃ have a frequency of 1.79 MHz based on the 1/12 frequency division described above, and a complementary signal is output from the terminal SX. I have. At the same time, the mode signal
HSM is “0”. After one bus cycle has elapsed, the high-speed mode is set based on the instruction CSH, and the system clocks S ₁ , S ₂ , and S ₃ have a frequency of 7.16 MHz based on the し た frequency division described above. At this time, the mode signal HSM becomes “1”. Next, when the instruction CSL is generated, one bus cycle elapses and the mode is changed to the low-speed mode. "1" for ▲ ▼ for one bicycle immediately after switching between low speed mode and high speed mode
To make it inactive. In the figure, PC indicates a program counter. [Effects of the Invention] As described above, according to the system control device of the present invention, the system clock is switched by the program and the mode signal is output according to the clock speed. Even so, the hardware can know the mode currently being executed, so that bus contention can be avoided.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an image display device, FIG. 2 is a block diagram showing one embodiment of the present invention, and FIGS. 3 to 5 are timing charts showing the operation of the present invention. Description of the code 1 CPU (system control device) 2 video display controller 3 video color encoder 4 programmable sound generator 5 ROM, 6 RAM 7 video RAM 8, 10 interface 9 TV 11a, 11b Amplifier 12a, 12b Speaker 20 Instruction register 21 Instruction decoder 22 Bus interface register 23 Arithmetic and logic operation unit 24 Register set 25 Mapping register 26 ... Chip enable decoder 27 ... Timing / control unit 28 ... I / O port 29 ... Timer 30 ... Interrupt request register 31 ... Interrupt disable registers 32 to 35 ... Bus, 36 ... A register 37 ... B register 38 accumulator 39 X register 40 Y register Registers 41 and 42 Program counter 43 Stack pointer 44 Status register 45 Source high register 46 Destination high register 47 Logical address low register 48 Logical address high register

Claims (1)

(57) [Claims] A system control device for controlling a system including a system control device connected to a bus and peripheral circuits based on a clock signal of a predetermined frequency, wherein a system clock generation for generating a high-speed or low-speed system clock by dividing an external clock Means for generating a high-speed or low-speed system clock in the system clock generating means based on a clock speed change command in a program read from an external program memory; and a high-speed or low-speed system clock corresponding to the high-speed or low-speed system clock. Alternatively, there is provided a system control device including control means for outputting a low-speed mode signal from an independent mode signal output terminal to the peripheral circuit.