JP2797325B2 - Decoder circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a decoder circuit for converting a binary n-bit code input signal into a thermometer code having "1" according to the magnitude of the n-bit code input signal. It is about.

[Summary of the Invention]

According to the present invention, when a binary n-bit code input signal is supplied, a first logic level signal is generated in order to generate a signal (Therometer Code) having a number of "1" corresponding to the input signal. An ECL (Emitter Coupled Logic) having an input terminal and a terminal for inputting a second logic level signal which is substantially half the potential difference of the first logic level signal.
MEL (Multi Level Emitter Cou) formed by the circuit
pled Logic) A plurality of (2 ⁿ -1) unit circuits are provided, and the ME
The first and second logic level signals formed from the binary n-bit code are supplied to the L unit circuit in a predetermined combination, so that each of the MEL unit circuits receives 2 ⁿ -1 thermocouples. A meter code is obtained.

[Conventional technology]

The same number of output terminals as the number obtained by converting the binary input code to decimal is the output of "1", and as the input code increases,
The code that switches each output terminal from “0” to “1” in order is
It is generally called a thermometer and is used for D / A converters and the like.

As an example of such a decoder circuit for converting into a thermometer code, the one shown in FIG. 7 is known.

The one shown in FIG. 7 converts a 3-bit input code into a 7-bit thermometer code. Binary input data A, B, and C are supplied to input terminals.

Input data A, B, C are either directly or NOT circuits NOT _{1 to} NOT
₃ is inverted by and be combined is supplied to the NAND gate N ₁ to N _7.

NAND gate N ₁ outputs a low level signal only when the input data is "001", which drives the transistor T _11.

NAND gate N ₂ outputs a low level signal only when the input data is "010", which drives the transistor T _12, T _21.

NAND gate N ₃ outputs a low level signal only when the input data is "011", which drives the transistor _{T 31, T 22, T 13} .

NAND gate N ₄ outputs a low level signal only when the input data is "100", which drives the transistor _{T 41, T 32, T 23} , T 14.

NAND gate N ₅ outputs a low-level signal only when the input data is "101", which drives the transistor _{T 51, T 42, T 33} , T 24, T 15.

NAND gate N ₆ outputs a low level signal only when the input data is "110", the transistors _{T 61, T 52, T 43} , T 34, T 25,
To drive the T _16.

NAND gate N ₇ outputs a low-level signal only when the input data is "111", the transistors _{T 71, T 62, T 53} , T 44, T 35,
Driving the T _26, T _17.

NAND gate in such a decoder circuit, the input data A, B, C is Figure 8 (a), by the as shown in (b) changes at each time point X ₁ to X _8, the point X ₁ code [111] N
₇ output level is "0", the level of the output terminal K ₁ ~K ₇ is FIG. 8 (c), the "1" level as shown in (d).

Also, the point X ₂ code [110], and the NAND gate N
_When only the output level of ₆ drops to “0”, the levels of the output terminals K _{1 to} K ₆ become “1”.

Hereinafter, similarly input data A, B, the number of "1" of the output terminal K ₁ ~K ₇ by the size of the C code also increases or decreases, the thermometer code as shown in FIG. 8 (c) is output Will be done.

[Problems to be solved by the invention]

In such a conventional decoder circuit, since the NAND gates are vertically stacked, the response is slow,
Also, the number of transistors T that output the thermometer code increases exponentially with the number of bits of the conversion code. For example, in the case of n bits, (2 ⁿ −1)! There is a drawback that the circuit configuration is complicated and the power consumption is increased because of the necessity.

Further, there is a problem that the operation speed is reduced due to an increase in the number of transistors T connected in parallel.

The present invention has been made in view of such a point,
By simplifying the circuit configuration of the logic circuit and simplifying the entire decoder circuit, high-speed operation and low power consumption can be achieved.

[Means for solving the problem]

By adopting a MEL (Multi-level Emitter Coupled Logic) circuit operating at the first and second logic levels as a logic circuit, a simplified logic circuit is obtained.
The configuration of the decoder circuit is simplified by increasing the priority of the upper bits of the input data input to the circuit.

[Action]

Since the logic circuit and its configuration are simplified, high-speed operation is possible and power consumption can be reduced.

〔Example〕

In describing the embodiment, the ME used in the embodiment
First, the L circuit will be described.

FIG. 6 (a) shows a basic gate of the MEL, wherein transistors Q ₁ and Q _{2 form} a differential pair. Transistors Q _1, Q is the _second base Ru different logic level, as described below the first and second input signals A, B ^* are supplied, an emitter of the transistor Q _1, Q ₂ are combined constant A current source _IO is provided.

The load resistors R ₁ and R ₂ are connected to the collectors of the transistors Q ₁ and Q ₂ , and the bases of the transistors Q ₃ and Q ₄ are connected respectively.

The transistors Q ₃ and Q ₄ are emitter followers. The emitters are connected to resistors R ₃ and R ₄ , respectively, and are connected to constant current sources I ₁ and I ₁ , respectively.

An output signal X from between the terminals of the resistors R ₃ and R ₄ ,
An output signal with a different logic level from this output signal Can be taken out.

As can be understood from FIG. 6A, the MEL circuit corresponds to a circuit obtained by removing the reference voltage of the ECL (Emitter Coupled Logic) circuit.

The logic levels of the first and second input signals A and B ^* are (b)
The settings are as shown in the figure. That is, as compared with the logic level of the input signal A, the logic level of the input signal B ^* is VV
_L lower.

Incidentally, V _L represents the difference between the level of the logic level of the H and L.

1 / 2V to the logic level of the first and second input signals A and B ^*
_{The L} level difference is to prevent the output level from becoming unstable when both the input signals A and B ^* are at the H level or the L level.

Since two logic levels (multi-level) are employed as the logic levels of the input signal, two logic levels are output as the output signal levels.

 Next, the operation of such a MEL unit circuit will be described.

When the input signal A is at the “H” level and the input signal B ^* is also at the H level, since the base of the transistor Q ₁ is higher, the resistance R ₁
Many current flow, the emitter potential of the transistor Q ₃ are reduced. Conversely, since less current to the resistor R ₂ flows, the emitter potential of the transistor Q ₄ are increased. Therefore, the output terminal X becomes "H" level. (An output signal of 1/2 V _L lower “H” level is obtained at the output terminal X ^*. ) When the input signal A is at “H” level and the input signal B ^* is at “L” level, the base of the transistor Q ₁ Since the potential is high, the result is the same as in the above case, and the output signal of the output terminal X becomes "H" level.

Next, the input signal A is at the “L” level and the input signal B ^* is at the “H” level.
When level, the base potential of the transistor Q ₂ is high, a large current flows through the resistor R _2, the emitter potential of the transistor Q ₄ is lowered. Reverse to the emitter of the transistor Q ₃ is increased. Therefore, the output signal of the output terminal X becomes “L” level.

When the input signal A is "L" level of the input signal B ^* is also "L" level, the base potential of the transistor Q ₁ is high, the resistance
Many current R ₁ flows. Therefore, the output signal of the output terminal X becomes "H" level.

Therefore, the MEL circuit in FIG. 6A is represented by the logical symbol in FIG. 6C, and its input / output logical value changes as shown in FIG. 6D.

Further, as shown in FIG. 6 (e), the transistors Q ₅ and Q _{5
When 6} is added to expand to multiple inputs A, B, C ^* , D ^* , the logic circuit becomes as shown in FIG. It can be.

 FIG. 2 shows an embodiment of the decoder circuit of the present invention.

FIG. 2 is a block diagram of a decoder for converting a 4-bit (D ₄ , D ₅ , D ₆ , D ₇ ) binary code. The decoder circuit 3 is composed of the basic MEL circuit described above. .

The input signals D _{4i to} D _7i are converted into first and second logic level signals and specific AND signals by the level shift circuits 1 and 2, and are supplied to the decoder circuit 3. In the decoder circuit 3, the binary input codes D ₄ , ₄ , D ₅ · D ₄ ,
_{5 · 4, D 5, 5} , D 6M, 6M, and converts D _{6, 6,} D _7M, a _7M to output code E ₁ to E ₁₅ of the thermometer code.

FIG. 3 (a) shows the details of the level shift circuit 1, FIG. 3 (b) shows the details of the level shift circuit 2, and FIG. 4 shows the details of the decoder circuit 3.

In FIGS. 2 to 5, signals with a subscript M, such as D _6M and D _7M , indicate the higher one of the first and second logic levels input to the MEL circuit. Is shown.

A specific circuit example of the level shift circuit 1 will be described with reference to FIG.

In a third diagram (a), the input signal D _4i is LSB and an inverted signal ▲ ▼ includes the transistors AQ ₁₂ AQ
Supplied to ₁₇ bases. The emitter of the transistor AQ ₁₂ and AQ ₁₇ are coupled, is connected to the low current source transistor AQ _15.

Further, a series connection circuit of two resistors R = 5 KΩ (hereinafter, R ₁ = 6 KΩ and R ₂ = 8 KΩ) is connected to the collectors of the transistors AQ ₁₂ and AQ ₁₇ , respectively. And resistance 2R
, The level of the signal output from the collectors of the transistors Q ₁₂ and Q ₁₇ becomes the lower logical level of the MEL circuit.

The output of this low logic level is taken out as D ₄ , ▲ ▼ at the output terminal via the emitter follower transistors AQ ₂₄ , AQ ₂₉ .

Formed by another circuit logic talk signal (D ₄ + D _{5) i} is one transistor AQ ₁₈ of the transistor AQ _18, AQ ₂₀ differential pairs
Supplied to the base. The base of the other transistor AQ _20, reference voltage supplied from the transistor AQ ₃ is applied.

Therefore, the output from the collector of the transistor AQ ₁₈ via the emitter follower transistor AQ ₃₁ is inverted. Becomes The logic level of this output is lower due to the parallel load resistance of the resistor R.

Also, the input signal Is one transistor A of the differential pair transistors AQ ₅ and AQ ₇
It is supplied to the base of Q _5. The base of the other transistor AQ _7, reference voltage supplied from the transistor AQ ₃ is applied.

Therefore, the signal output through the emitter follower transistor AQ ₁₀ from the collector of the transistor AQ ₅ becomes is inverted D ₅ · D _4. The logic level of this output is also a low logic level due to the parallel load resistance R.

Input signal D _5i and an inverted signal ▲ ▼ the input signal D _4i described above, ▲ ▼ and the level shift circuit similar to the same configuration, the output signal D ₅ of each low logic level, ▲
▼ is level-shifted and output.

In FIG. 3A, the bias voltage BIASD is
Transistor _{AQ 15, AQ 23, AQ 28} , AQ 1, AQ 2, AQ 4, AQ 6, AQ 9, AQ
₁₄ , AQ ₁₉ , AQ ₃₀ , AQ ₁₃ , AQ ₂₁ , and a voltage for flowing a constant current through AQ ₂₆ .

Next, a specific circuit example of the level shift circuit 2 will be described with reference to FIG.

FIG. 3 (b) outputs a particularly high logic level signal. The input signal _D6i and its inverted signal ▲ ▼ are converted into high logic level signals _D6M , ▲ ▼ and a low logic level signal D6. ₆ and ▲ ▼, and an input signal D _7i and its inverted signal ▲ ▼ which are level-shifted to higher logic levels D _7M and ▲ ▼ are output.

That is, the input signals D _6i and ▲ ▼ are supplied to the bases of the differential pair transistors BQ ₁ and BQ ₅ , respectively, and the output signals whose level is shifted from the collectors thereof through the emitter followers BQ ₈ and BQ ₁₄ have high logic levels. It is output as a level output signal D _6M , ▲ ▼.

Since the collector load resistance of the transistors BQ ₁ and BQ ₅ is only the resistance R, the level is shifted to a high logic level and output from the collector. Note that the emitters of the differential pair transistors BQ ₁ and BQ ₅ are connected to the constant current transistor BQ ₃ .

The input signals D _6i and ▼ are also applied to the bases of the differential pair transistors BQ ₁₉ and BQ ₂₁ . Transistor BQ
₁₉ and BQ ₂₁ are omitted because they have the same configuration as above, but the emitter follower transistors BQ ₂₃ and BQ ₂₁
The output signal D ₆ of the low logic level from the Q _25, ▲ ▼ is output.

And its inverted signal ▲ ▼ input signal D _7i is MSB, a differential pair is supplied to the base of the transistor BQ _2, BQ _6, the output signals respectively level shifted from collector emitter follower transistor BQ _10, BQ ₁₂ , BQ ₁₆ , and BQ _18, which are taken out as high logic level output signals D _7M , ▲ ▼.

Also in this level shift circuit, the transistors BQ ₂ ,
The collector load resistance of BQ ₆ is level-shifted to a higher logic level since each is only resistance R.

Also, the emitter follower transistors are BQ ₁₀ , BQ ₁₂ and BQ
_16, the BQ ₁₈ and has in parallel, the output signal D _7M ▲
This is for driving a lot of loads with and. Further, the bias voltage BIASD is determined by the transistors BQ ₃ , BQ ₇ , BQ ₁₃ , BQ ₂₀ , B
Q _22, a _{BQ 24, BQ 4, BQ 9} , BQ 11, BQ 15, the voltage for the BQ ₁₇ to a constant current driving.

Input code of 4 bits in FIG. 1 is a decoder circuit, D ₇ to D ₄
When shows the correspondence between the output symbols E ₁ to E _15. In the figure, X ₁
To X ₁₆ denotes a point indicating the input code of FIG. 1, the relationship between the logical value of the thermometer code in Table 1.

As shown in this table, a 4-bit input code D ₇
To D ₄ it is is being converted into thermometer output code E ₁ to E ₁₅ of 15 bits, consider the logical expression for obtaining the output code E ₁ to E _15.

The following logical expression gives priority to the upper bit and converts it to a higher logical level, and also converts the basic MEL shown in FIG.
This is an equation created by modifying the logic level of one input signal to be different from the logic level of the other input signal so that the circuit can be used.

A circuit in which the logical expressions of the above expressions (1) to (15) are combined by a logical circuit is the decoder circuit shown in FIG.

Figure 5 and respectively extract the MEL unit circuit to obtain an output code E ₁ to E ₁₅ in the circuit from the decoder circuit of FIG. 4 (a) ~
5 (a) are denoted by the same reference numerals, and the circuits of FIGS. 5 (a) to 5 (o) will be sequentially described.

Figure 5 (a) is a circuit for obtaining an output code E _1, it is a circuit which satisfies the logical expression (1) below. Input code D ₅
D ₄ is supplied to the base of one transistor Q ₇ of the differential pair transistors of the _{MEL Q 1, Q 2, Q} 7, input code ▲ ▼ the base of the other transistor Q _2, the input code ▲ ▼ the other It is supplied to the bases of the transistors Q _1.

Since the transistors Q ₁ and Q ₂ are connected in parallel, The logic of transistor Q ₇ and transistors Q ₁ and Q ₂
Since operates differentially, the output code from the load resistor R ₁ is D ₅
・ D ₄ and AND with

That is, the logical expression of Expression (1) is satisfied in the circuit of FIG. From the other of the load resistor is output inversion code ▲ ▼ of E _1.

Figure 5 (b) is a circuit for obtaining an output code E _2.

In FIG. 5 (b), the input code D ₅ to the base of the transistor Q ₁₇ of one of the differential pair Toranjita of MEL, input to the base of the other transistor Q _11, Q ₁₂ symbols ▲ ▼,
▲ ▼ is supplied. Since a differential operation transistors Q ₁₇ and the transistor Q _11, Q _12, the input code D ₅ appears without being inverted to the load resistor R ₆ of the transistors Q _11, Q _12. Also, input symbols ▲ ▼ and ▲ ▼
Since the transistor Q ₁₁ and Q ₁₂ are in parallel, the load resistor R ₆ is The inverted sign of the logical OR appears.

Thus, the D ₅ from the load resistor R ₆ Logical product, or sign E ₂ of the equation (2) is taken out. Incidentally, the inversion code ▲ ▼ is obtained from the load resistor R ₉ of the transistor Q _17.

Figure 5 (c) is a circuit for obtaining an output code E _3.

In FIG. 5 (c), the input code D ₅ and D ₄ is the logical sum is taken by the transistor Q _27, Q ₂₈ connected in parallel, the input code ▲ ▼ and ▲ ▼ parallel connected transistors Q _21, Q _The logical sum is obtained by ₂₂ .

Then, the transistors Q ₂₇ and Q _{28 of} the MEL and the transistor Q
_21, since a differential operation and Q _22, the load resistor R _11, Code ie E ₃ made is obtained.

Hereinafter, the circuit of FIG. 5 in the same manner (d) ~ (o), that the output code E ₄ to E ₁₅ obtained will be readily understood.

As apparent from FIGS. 5 (a) to 5 (o), ME
The logic level of one input code of L has a high logic level, and the logic level of the other input code has a low logic level. Therefore, even if the reference level is not set, the output signals E _{1 to} E ₁₅ do not become unstable values.

FIG. 4 shows an example in which 15 such MEL circuits are integrated, and the same parts in FIGS. 5 (a) to 5 (o) are denoted by the same reference numerals.

In FIG. 4, the bias voltage BIASD is for driving a constant current source for supplying a constant current to each part of the decoder circuit.

The clocks CLK2 and ▲ ▼ are for operating the decoder circuit by the clock, and the output symbols E _{1 to} E
₁₅ (▲ ▼ ~ ▲ ▼) on the output portions of the transistors (Q ₅ and Q _9), (Q ₁₅ and Q _19), (Q ₂₅ and Q ₃₀₎ (hereinafter, not shown) flip-flop consisting of These flip-flops operate on the logical output of the MEL circuit at the timing of the clock ▼ and then latch at the timing of CLK2. As a result, the thermometer code is obtained for 4-bit code binary from the terminal E ₁ to E _15.

In the above embodiment, the 4-bit decoder circuit is a MEL
When forming in circuit units, the higher-order bits with relatively little change are preferentially converted to higher logic levels, and each MEL
The logic signals input to the circuit are shared as much as possible, the number is reduced, the number of transistors constituting the MEL circuit is reduced as much as possible, and high speed and low power consumption (low voltage ratio) are aimed at. . Therefore, it is possible for a person skilled in the art to modify and implement a level shift circuit for forming a logic signal to be supplied to the MEL circuit, in addition to the embodiment, and to implement the present invention. it can.

〔The invention's effect〕

As described above, according to the present invention, since the decoder circuit is configured using the MEL circuit, the level shift circuit and one stage of the MEL gate can convert the binary n-bit code into the thermometer code. As a result, there is an effect that high-speed operation can be achieved and power consumption can be reduced.

[Brief description of the drawings]

FIG. 1 is a diagram showing the correspondence between input codes and output codes of the decoder of the present invention, FIG. 2 is a block diagram of an embodiment of the present invention, and FIGS. 3 (a) and 3 (b) are embodiments of the present invention. FIG. 4 is a circuit diagram of a decoder circuit according to an embodiment of the present invention, FIGS. 5 (a) to 5 (o) are circuit diagrams of respective parts of the decoder circuit of the present invention, and FIG. (A), (b), (c),
(D), (e) and (f) show the basic circuit diagram of MEL, FIG. 7 shows a conventional decoder circuit diagram, and FIGS. 8 (a), (b) and
(C) and (d) are diagrams showing the correspondence between input codes and output codes of a conventional decoder circuit. In the figure, 1 and 2 are level shift circuits, 3 is a decoder circuit, and D _4i
To D _7i input code, E ₁ to E ₁₅ is a thermometer output code.

Continuation of the front page (72) Inventor Masato Kawada 6-35, Kita-Shinagawa, Shinagawa-ku, Tokyo Inside Sony Corporation (56) References JP-B Hei 7-58913 (JP, B2) (58) Survey Field (Int.Cl. ⁶ , DB name) H03M 7/00

Claims (1)

(57) [Claims] 1. A binary code signal to be converted is converted into a first logic level signal and a second logic level signal in which an intermediate level of the first logic level signal is set to one of logic levels. A logic circuit comprising at least 2 ⁿ -1 MEL unit circuits for comparing the first logic level signal output from the level shift circuit with the second logic level signal. In a decoder circuit comprising a comparison circuit, wherein the thermometer code is output from the logical comparison circuit, the level shift circuit gives priority to the upper bits of the input binary code signal to be converted to a specific number of bits. A first conversion circuit that converts the signal into the second logic level signal including an inverted signal and outputs the converted signal, and includes an inverted signal of a lower bit of the input binary code signal to be converted. A second conversion circuit that outputs the first logic level signal as a first logic level signal, wherein the first logic level signal output from the level shift circuit is supplied to one transistor of a differential pair constituting the MEL unit circuit by a predetermined signal. The second logic level signal supplied in combination and output from the level shift circuit is connected to be supplied in a predetermined combination to the other transistor of the differential pair of the MEL unit circuit, and A signal having the same logic level of the same bit output from the level shift circuit is configured to be supplied to a transistor arranged on the same row line every time the MEL is performed. Decoder circuit.