KR930001748B1 - Logic circuitry - Google Patents

Abstract

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Description

Logic circuit

1 is an equivalent circuit diagram of one embodiment of a logic circuit according to the present invention.

2 is a diagram showing the input-output relationship in the above-described circuit in a comprehensive manner.

3 to 8 are circuit diagrams showing the detailed configurations of the respective circuit portions of the embodiment circuit, respectively.

9 shows a conventional logic circuit.

10 is a waveform diagram for explaining the operation of the conventional circuit.

* Explanation of symbols for main parts of the drawings

11: first composite gate circuit, 12, 13, 17, 19: OR logic section

14: OR gate circuit 15: second composite gate circuit

16, 20, 23, 24: AND logic unit 18: third composite gate circuit

21 AND gate circuit 22 fourth composite gate circuit

31, 32, 35, 36, 42-46, 51, 52, 61, 62, 65, 66, 71: NPN transistor

33, 34, 63, 64: load resistance 37, 38, 47, 48, 53, 67, 68, 73: constant current source

39, 40, 49, 50, 69, 70: emitter follower circuit

81: reference voltage generator 82: step voltage generator

83: voltage comparison unit

[Industrial use]

The present invention relates to a logic circuit that outputs seven status signals based on a 3-bit digital signal.

[Traditional Technology and Problems]

In the D / A converter, when converting an n-bit digital signal, the low-bit m-bit digital signal is used to control the D / A converter by the resistance ladder circuit, and the digital signal of the upper (nm) bit is used to control the D / A converter. D / A conversion is performed by controlling the operation of a current source for supplying current to the resistance ladder circuit. In this case, the digital signals of the upper (n-m) bits are supplied to the logic circuit to generate 2 (n-m) -1 status signals.

FIG. 9 is a diagram showing the configuration of a conventional logic circuit which generates seven status signals from a 3-bit digital signal. In such a logic circuit, a reference composed of a transistor Q1, a plurality of resistors and a constant current source I is shown. The voltage generator 81 forms three reference voltages V1, V2, and V3 as shown in the waveform diagram of FIG. In addition, in step voltage generator 82 composed of transistors Q2 and Q3, switches S1 to S3, a plurality of resistors and constant current sources I and 2I, the switches S1 to S3 according to a 3-bit digital signal. By selectively operating, the stepped voltage VA of which the value gradually decreases in steps and the stepped voltage VB of the stepwise increasing values are generated as shown in the waveform diagram of FIG. 10. .

In the voltage comparator 83 composed of seven comparators C1 to C7, the seven state output signals (7) are compared by comparing each of the voltages VA and VB with the reference voltages V1, V2 and V3 and the voltages VA and VB. OUT1 to OUT7) are output. In FIG. 10, an input code consisting of a 3-bit digital signal corresponding to the voltages VA and VB is added.

In the circuit configured as described above, when the three-bit digital signal is all zero level, that is, the input code is 000, the voltage VA generated by the step voltage generator 82 is three values as shown in FIG. Is higher than any of the reference voltages V1, V2 and V3, and the voltage VB is lower than any of the three reference voltages V1, V2 and V3. At this time, all output signals OUT1 to OUT7 of the seven comparators C1 to C7 in the voltage comparator 83 become zero level, and then the least significant bit of the three-bit digital signal becomes one level so that the input code becomes 001. As shown in FIG. 10, the voltage VA becomes lower than the reference voltage V1 so that only the output signal OUT1 of the comparator C1 of the voltage comparator 83 is inverted to one level. Three bits of digital signal are then inputted from 001 to 010, 011,... By changing regularly, the output signals of the comparators C2, C3, ... of the voltage comparator 83 are sequentially inverted to one level. Here, since the relationship between the three-bit digital input and the seven state outputs is one-to-one, a state output signal corresponding to the input is always output even if the three-bit digital signal does not change regularly.

However, in the conventional circuit, seven state output signals are obtained by comparing the analog voltages obtained by resistance division, so that if the error occurs in the values of each resistor and each constant current source, conversion accuracy may be degraded. do.

That is, in the conventional circuit, the analog output voltage is compared to obtain a state output, so that the accuracy of conversion may be lowered due to an error in device characteristics.

[Purpose of invention]

Accordingly, the present invention has been made in consideration of the above circumstances, and an object thereof is to provide a logic circuit capable of always outputting a state output signal corresponding to a digital signal with high conversion accuracy without being affected by device characteristic errors. There is this.

[Configuration of Invention]

A logic circuit according to the present invention for achieving the above object includes an ECL type first composite gate circuit for outputting an OR logic output of the first, second and third digital signals as a first status signal, and a second digital. An ECL type first gate circuit which outputs the OR logic output of the signal and the third digital signal as the second state signal, and obtains the AND logic output of the first digital signal and the second digital signal, and the AND logic output and the third digital signal. A second ECL type composite gate circuit which outputs the OR logic output of the signal as a third status signal, obtains the OR logic output of the first digital signal and the second digital signal, and obtains the OR logic output and the AND logic of the third digital signal. An ECL type third composite gate circuit that outputs an output as a fifth state signal, an ECL type second gate circuit that outputs an AND logic output of a second digital signal and a third digital signal as a sixth state signal, and a first The AND logic outputs of the digital signal and the second digital signal are obtained. Hagoseo having an ECL-type fourth composite gate circuit which outputs the logical AND output and the output of the third digital signal as the status signal of claim 7 is characterized in that is configured to output a third digital signal as the status signal of the fourth.

[Action]

In the logic circuit according to the present invention configured as described above, an OR logic or AND logic of a 3-bit digital signal using an ECL type gate circuit and a composite gate circuit to output seven status signals from a 3-bit digital signal. Will be available. In addition, since the input / output signals of the respective gate circuits or the composite gate circuits are treated as the state of the digital signals of the 1 level or the 0 level, the error of the device characteristics constituting these gate circuits or the composite gate circuit does not affect the output.

EXAMPLE

Hereinafter, each embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is an equivalent circuit diagram showing the configuration when the logic circuit according to the present invention is configured to output seven status output signals OUT1 to OUT7 from 3-bit digital signals IN1, IN2, and IN3. Among the three-bit digital signals IN1, IN2, and IN3, IN1 represents the least significant bit signal and IN3 represents the most significant bit signal.

The digital signals IN1 and IN2 are supplied to the OR logic unit 12 of the first composite gate circuit 11 configured to output the first state output signal OUT1, and the outputs of the OR logic unit 12 and the digital signals are output. IN3 is supplied to the OR logic unit 13 of the first composite gate circuit 11. The digital signals IN2 and IN3 are supplied to the OR gate circuit 14 which outputs the second state output signal OUT2.

The digital signals IN2 and IN3 are supplied to the AND logic section 16 of the second composite gate circuit 15 configured to output the third state output signal OUT3, and the outputs of the AND logic section 16 and the digital signals are output. IN3 is supplied to the OR logic unit 17 of the second composite gate circuit 15. The digital signal IN3 is output as it is as the status output signal OUT4.

The digital signals IN1 and IN2 are supplied to the OR logic unit 19 of the third composite gate circuit 18 configured to output the fifth state output signal OUT5, and the output of the OR logic unit 19 and the digital signal are provided. IN3 is supplied to the AND logic unit 20 of the third composite gate circuit 18. The digital signals IN2 and IN3 are supplied to the AND gate circuit 21 which outputs the sixth state output signal OUT6.

The digital signals IN1 and IN2 are supplied to the AND logic unit 23 of the fourth composite gate circuit 22 configured to output the seventh state output signal OUT7, and the outputs of the AND logic unit 23 and the digital signals are output. IN3 is supplied to the AND logic section 24 of the fourth composite gate circuit 22.

Here, the first to fourth composite gate circuits 11, 15, 18, and 22, the OR gate circuits 14, and the AND gate circuits 21 are coupled to emitters and are supplied with complementary signals to respective bases. It is composed of an ECL circuit having a pair of transistors as a basic configuration.

Next, the operation of the circuit configured as described above will be described.

First, when the 3-bit digital signals IN1, IN2, and IN3 are all at zero level, the first to fourth composite gate circuits 11, 15, 18, and 22, the OR gate circuit 14, and the AND gate circuit 21 ) When the respective outputs OUT1 to OUT3 and OUT5 to OUT7 and OUT4 are all at zero level, and the digital signals IN2 and IN3 are at zero level and IN1 is at one level, only the output OUT1 of the first composite gate circuit 11 is one. When the digital signals IN1 and IN3 are at the 0 level and IN2 is at the 1 level, the output OUT1 of the first composite gate circuit 11 and the output OUT2 of the OR gate circuit 14 become 1 level. Similarly, as the 3-bit digital signals IN1, IN2, IN3 sequentially increase, OUT3, OUT4,... The seven status output signals change to one level in the order of. Therefore, when the input and output relations in the circuit shown in FIG. 1 are combined, the result is as shown in FIG. As can be seen from the figure, the 3-bit digital signal is converted into four state signals.

In this embodiment circuit, the OR logic or AND logic of the 3-bit digital signal is obtained by using the ECL gate circuit and the composite gate circuit to output the 3-bit digital signal to the 7 status signals. Since the input / output signal of the gate circuit or the composite gate circuit is treated as the state of the digital signal of the 1 level or the 0 level, the error of the device characteristics constituting the gate circuit or the composite gate circuit does not affect the output.

3 to 8 are circuit diagrams showing the detailed configuration of an ECL gate circuit or a composite gate circuit in the above embodiment circuit.

가 공급되는 한쌍의 NPN형 트랜지스터(31, 32)와, 상기 양 트랜지스터(31, 32)의 부하저항(33, 34), NPN형 트랜지스터(35, 36) 각각과 정전류원(37, 38) 각각으로 이루어지며 디지탈신호

가 공급되는 에미터플로워회로(39, 40), 베이스에 상기 에미터플로워회로(39)의 출력이 공급되고 콜렉터가 상기 양 트랜지스터(31, 32)의 공통에미터에 접속된 NPN형 트랜지스터(41), 베이스에 상기 에미터플로워회로(40)의 출력이 공급되고 콜렉터가 상기 트랜지스터(32)의 콜렉터에 접속되며 에미터가 상기 트랜지스터(41)의 에미터와 공통접속된 NPN형 트랜지스터(42), NPN형 트랜지스터(43, 44) 각각과 NPN형 트랜지스터(45, 46) 각각 및 정전류원(47, 48) 각각으로 이루어지며 디지탈신호

가 공급되는 에미터플로워회로(49, 50), 떼이스에 상기 에미터플로워회로(49)의 출력이 공급되고 콜렉터가 상기 양 트랜지스터(41, 42)의 공통에미터에 접속된 NPN형 트랜지스터(51), 베이스에 상기 에미터플로워회로(50)의 출력이 공급되고 콜렉터가 상기 트랜지스터(32)의 콜렉터에 접속되며 에미터가 상기 트랜지스터(51)의 에미터와 공통접속된 NPN형 트랜지스터(52) 및, 상기 양 트랜지스터(51, 52)의 공통 에미터에 접속된 정전류원(53)으로 구성되는 바, 상기 양 트랜지스터(31, 32)의 콜렉터에서 상태출력신호

가 각각 출력되도록 되어 있다. 여기서, 상기 에미터플로워회로(49, 50)에 설치된 트랜지스터(45, 46)는 출력레벨조정용 트랜지스터이다.FIG. 3 shows a first composite gate circuit 11 adapted to output a first state output signal OUT1, in which emitters are interconnected and a digital signal at each base.

Is supplied with a pair of NPN transistors 31 and 32, load resistors 33 and 34, NPN transistors 35 and 36, and constant current sources 37 and 38 of both transistors 31 and 32, respectively. Digital signal

Emitter follower (39, 40) supplied with the output of the emitter follower (39) to the base, the collector is connected to the NPN type transistor 41 connected to the common emitter of the transistors (31, 32) NPN-type transistor 42 having an output of the emitter follower 40 supplied to a base, a collector connected to a collector of the transistor 32, and an emitter connected in common with an emitter of the transistor 41. And NPN transistors 43 and 44, NPN transistors 45 and 46, and constant current sources 47 and 48, respectively.

Emitter follower circuits 49 and 50, to which the output of the emitter follower circuit 49 is supplied, and the collector is connected to a common emitter of the transistors 41 and 42. 51, an NPN transistor 52 in which an output of the emitter follower 50 is supplied to a base, a collector is connected to a collector of the transistor 32, and an emitter is commonly connected to an emitter of the transistor 51; And a constant current source 53 connected to a common emitter of both transistors 51 and 52, and a state output signal from the collector of both transistors 31 and 32.

Are outputted respectively. Here, the transistors 45 and 46 provided in the emitter follower circuits 49 and 50 are output level adjusting transistors.

가 공급되는 한쌍의 NPN형 트랜지스터(61, 62)와, 상기 양 트랜지스터(61, 62)의 부하저항(63, 64), NPN형 트랜지스터(65, 66) 각각과 정전류원(67, 68) 각각으로 이루어지며 디지탈신호

가 공급되는 에미터플로워회로(69, 70), 베이스에 상기 에미터플로워회로(69)의 출력이 공급되고 콜렉터가 상기 양 트랜지스터(61, 62)의 공통에미터에 접속된 NPN형 트랜지스터(71), 베이스에 상기 에미터플로워회로(70)의 출력이 공급되고 콜렉터가 상기 트랜지스터(62)의 콜렉터에 접속되며 에미터가 상기 트랜지스터(61)의 에미터와 공통접속된 NPN형 트랜지스터(72) 및, 상기 양 트랜지스터(71, 72) 공통에 미터에 접속된 정전류원(73)으로 구성되는 바, 상기 양 트랜지스터(61, 62)의 콜렉터에서 상태 출력신호

가 각각 출력되도록 되어 있다.4 shows an OR gate circuit 14 configured to output the status output signal OUT2, which emitters are interconnected and have a digital signal at each base.

A pair of NPN transistors 61 and 62 to which the transistors are supplied, the load resistors 63 and 64 of the transistors 61 and 62, the NPN transistors 65 and 66, and the constant current sources 67 and 68, respectively. Digital signal

Emitter follower (69, 70) supplied with the output of the emitter follower (69) to the base, the collector is connected to the NPN type transistor 71 connected to the common emitter of the transistors (61, 62) NPN transistor 72 having an output of the emitter follower circuit 70 supplied to a base, a collector connected to a collector of the transistor 62, and an emitter connected in common to the emitter of the transistor 61. And a constant current source 73 connected to a meter in common to both of the transistors 71 and 72, wherein a state output signal is generated by the collectors of both transistors 61 and 62.

Are outputted respectively.

과 IN1의 입력을 교환하고 디지탈신호

와 IN2의 입력을 교환함으로써 구성되는 바, 상기 트랜지스터(31, 32)의 콜렉터에서 상태출력신호

, OUT3가 각각 출력되도록 되어 있다.FIG. 5 shows a second composite gate circuit 15 which is configured to output the state output signal OUT3, which in the circuit shown in FIG. 3 is connected to the collector of the transistor 32 in the collector of the transistor 52. FIG. Instead of the connection, the digital signal is connected to the collector of the transistor 31.

And input of IN1 are exchanged

And a state output signal from the collectors of the transistors 31 and 32.

And OUT3 are outputted respectively.

과 IN1의 입력을 교환하고 디지탈신호

와 IN2의 입력을 교환하며 디지탈신호

과 IN3의 입력을 교환함으로써 구성되는 바, 상기 트랜지스터(31, 32)의 콜렉터에서 상태출력신호

가 각각 출력되도록 되어 있다.FIG. 6 shows a third composite gate circuit 18 adapted to output the status output signal OUT5, which is a digital signal in the circuit shown in FIG.

And input of IN1 are exchanged

Digital signal exchange between input and IN2

And a state output signal from the collectors of the transistors 31 and 32.

Are outputted respectively.

과 IN1의 입력을 교환하고 디지탈신호

와 IN2의 입력을 교환함으로써 구성되는 바, 트랜지스터(61, 62)의 콜렉터에서 상태출력신호

가 각각 출력되도록 되어 있다.FIG. 7 shows an AND gate circuit 21 for outputting the status output signal OUT6, which is a digital signal in the OR gate circuit 14 shown in FIG.

And input of IN1 are exchanged

And a state output signal from the collectors of transistors 61 and 62.

Are outputted respectively.

과 IN1의 입력을 교환하고 디지탈신호

와 IN2의 입력을 교환하며 디지탈신호

와 IN3의 입력을 교환함으로써 구성되는 바, 트랜지스터(31, 32)의 콜렉터에서 상태출력신호

이 각자 출력되도록 되어 있다.FIG. 8 shows a fourth composite gate circuit 22 adapted to output the state output signal OUT7, which is a digital signal in the first composite gate circuit 11 of FIG.

And input of IN1 are exchanged

Digital signal exchange between input and IN2

And the state output signal from the collectors of transistors 31 and 32.

Each of these is to be output.

In this way, when each gate circuit has an ECL configuration, the signal delay time for the input can be shortened, so that an output signal can be obtained at high speed.

[Effects of the Invention]

As described above, according to the present invention, it is possible to provide a logic circuit capable of always outputting a state output signal corresponding to a digital signal with a high conversion accuracy without being affected by an error in device characteristics.

Claims (1)

A logic circuit for outputting seven status signals OUT1 to OUT7 based on first, second and third digital signals IN1, IN2, and IN3, wherein the first, second and third digital signals IN1 Of the ECL type first composite gate circuit 11 for outputting the OR logical output of IN2 and IN3 as the first state signal OUT1, and the second digital signal IN2 and the third digital signal IN3. The AND logic output of the ECL type first gate circuit 14 which outputs the OR logic output as the second state signal OUT2, the first digital signal IN1 and the second digital signal IN2 is obtained, and the AND logic is obtained. An ECL type second composite gate circuit 15 which outputs an output and an OR logic output of the third digital signal IN3 as a third state signal OUT3, and the first digital signal IN1 and the second digital signal. An ECL type third composite gate circuit 18 for obtaining an OR logic output of (IN2) and outputting the OR logic output and the AND logic output of the third digital signal IN3 as a fifth state signal OUT5; Second digital signal IN2 and second Of the ECL type second gate circuit 21 for outputting the AND logic output of the three digital signals IN3 as the sixth state signal OUT6, and the first digital signals IN1 and the second digital signals IN2. An ECL-type fourth composite gate circuit 22 for obtaining an AND logic output and outputting the AND logic output and the AND logic output of the third digital signal IN3 as a seventh state signal OUT7; And output a digital signal (IN3) as a fourth state signal (OUT4).

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