JP2789689B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JP2789689B2 JP2789689B2 JP18098689A JP18098689A JP2789689B2 JP 2789689 B2 JP2789689 B2 JP 2789689B2 JP 18098689 A JP18098689 A JP 18098689A JP 18098689 A JP18098689 A JP 18098689A JP 2789689 B2 JP2789689 B2 JP 2789689B2
- Authority
- JP
- Japan
- Prior art keywords
- inp
- atomic layer
- schottky junction
- gaas
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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- Electrodes Of Semiconductors (AREA)
Description
【発明の詳細な説明】 〔概要〕 半導体装置の製造方法に係り，特に,InPのショットキ
ー接合を含む半導体装置の製造方法に関し， InPのショットキー接合を実効的に実現する方法を目
的とし， 一導電型のInP結晶上に一導電型のGaAsエピタキシャ
ル原子層を原子層エピタキシーにより形成した後，該Ga
Asエピタキシャル原子層に接して金属電極を形成するこ
とにより，実効的にInPのショットキー接合を形成する
工程を含む半導体装置の製造方法により構成する。DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device including a Schottky junction of InP. After forming a GaAs epitaxial atomic layer of one conductivity type on an InP crystal of one conductivity type by atomic layer epitaxy,
A method for manufacturing a semiconductor device including a step of forming a Schottky junction of InP effectively by forming a metal electrode in contact with an As epitaxial atomic layer.
本発明は半導体装置の製造方法に係り，特に,InPのシ
ョットキー接合を含む半導体装置の製造方法に関する。The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device including a Schottky junction of InP.
近年めざましい発展を続けている光通信技術の一つと
して，光電子集積回路（OEIC）がある。これは，一チッ
プ内に光電変換部と増幅部を有することを一つの特徴と
している。特に,1μｍ帯のOEICでは,InGaAs/InPまたはI
nGaAsP/InPヘテロ接合素子を受光部とし,InP電界効果ト
ランジスタ（InP FET）を増幅部とするのが一般的であ
る。Optoelectronic integrated circuits (OEICs) are one of the optical communication technologies that have been developing remarkably in recent years. This is one feature of having a photoelectric conversion unit and an amplification unit in one chip. In particular, for OEICs in the 1 μm band, InGaAs / InP or I
Generally, an nGaAsP / InP heterojunction element is used as a light receiving unit, and an InP field effect transistor (InP FET) is used as an amplifying unit.
従って,InP結晶を基板として，その上に各種の半導体
装置を集積する技術が必要とされる。Therefore, a technique of using an InP crystal as a substrate and integrating various semiconductor devices thereon is required.
従来,InP FETでは,n型の導電性をもつInPにアクセプ
タ不純物を熱拡散させて,p−ｎ接合と空乏層を形成する
ことが行われてきた。Conventionally, in an InP FET, a pn junction and a depletion layer have been formed by thermally diffusing an acceptor impurity into InP having n-type conductivity.
しかし，このような不純物拡散を用いる方法では約60
0℃の高温プロセスを必要とするのでInP結晶がダメージ
を受けやすく，また，拡散深さの制御が難しいなどの難
点があった。製造工程も複雑で，コスト高となってい
た。However, in the method using such impurity diffusion, about 60
Since a high temperature process of 0 ° C. is required, the InP crystal is easily damaged, and the control of the diffusion depth is difficult. The manufacturing process was complicated and the cost was high.
一方，空乏層を簡単に形成する方法としてショットキ
ー接合があるが,InPのショットキー接合は現在のところ
実現が難しい。On the other hand, there is a Schottky junction as a simple method of forming a depletion layer, but it is difficult to realize an InP Schottky junction at present.
本発明は,InP結晶の上に極く薄いGaAsエピタキシャル
原子層を形成して，実効的にInPのショットキー接合の
機能を有する空乏層接合部を実現する低温プロセスを提
供し，素子特性の向上を図るとともに、製造工程を簡単
にしてコスト低下を図ることを目的とする。The present invention provides a low-temperature process for forming an extremely thin GaAs epitaxial atomic layer on an InP crystal to effectively realize a depletion layer junction having a Schottky junction function of InP, thereby improving device characteristics. It is another object of the present invention to simplify manufacturing processes and reduce costs.
上記課題は，一導電型のInP結晶２上に一導電型のGaA
sエピタキシャル原子層３を原子層エピタキシーにより
形成した後，該GaAsエピタキシャル原子層３に接して金
属電極４を形成することにより，実効的にInPのショッ
トキー接合を形成する工程を含む半導体装置の製造方法
によって解決される。The above-mentioned problem is caused by one-conductivity-type GaAs on one-conductivity-type InP crystal 2.
Manufacturing of a semiconductor device including a step of forming an InP Schottky junction by forming a metal electrode 4 in contact with the GaAs epitaxial atomic layer 3 after forming the s epitaxial atomic layer 3 by atomic layer epitaxy. Solved by the method.
本発明では，実効的にInPのショットキー接合を形成
する方法として，原子層エピタキシー技術を利用する。
即ち，一導電型のInP結晶上に一導電型のGaAs層を数原
子層乃至数十原子層成長させる。In the present invention, an atomic layer epitaxy technique is used as a method for effectively forming an InP Schottky junction.
That is, several to several tens of atomic layers of a GaAs layer of one conductivity type are grown on an InP crystal of one conductivity type.
第１図は、原子層エピタキシーにより成長したInP結
晶上のGaAs原子層を模式的に表したものである。InP結
晶上にGa層とAs層が１層づつ順次成長する。さらにその
上に金属電極を付着してGaAsショットキー接合を形成す
る。GaAsにおいては，例えばAlのような金属と良好なシ
ョットキー接合を作る技術が既に確立されている。FIG. 1 schematically shows a GaAs atomic layer on an InP crystal grown by atomic layer epitaxy. On the InP crystal, a Ga layer and an As layer are sequentially grown one by one. Further, a metal electrode is attached thereon to form a GaAs Schottky junction. In GaAs, a technique for forming a good Schottky junction with a metal such as Al has already been established.
ところで、GaAs層を数十Å程度に薄く形成すれば，空
乏層はInP結晶内に形成されることになり，実効的にInP
ショットキー接合が形成されたことになり，実験的にも
ショットキー接合の機能を有することが示される。By the way, if the GaAs layer is formed as thin as several tens of millimeters, the depletion layer will be formed in the InP crystal, and the InP crystal will be effectively formed.
This means that the Schottky junction has been formed, and it is experimentally shown that the Schottky junction has the function of the Schottky junction.
以下，本発明の実施例について説明する。 Hereinafter, embodiments of the present invention will be described.
第２図（ａ）乃至（ｄ）は実施例で，本発明の方法を
適用したショットキー接合ダイオードの製造工程を説明
するための断面図であり,1はInP基板でn+−InP基板,2は
バッファ層でｎ−InP,3はGaAsのエピタキシャル原子層,
4は金属電極でAl電極,5は基板側電極を表す。2 (a) to 2 (d) are embodiments and are cross-sectional views for explaining a manufacturing process of a Schottky junction diode to which the method of the present invention is applied, where 1 is an InP substrate and n + -InP substrate; 2 is a buffer layer, n-InP, 3 is an epitaxial atomic layer of GaAs,
Reference numeral 4 denotes a metal electrode and an Al electrode, and 5 denotes a substrate-side electrode.
以下，第２図（ａ）乃至（ｄ）を参照しながら説明す
る。Hereinafter, description will be made with reference to FIGS. 2 (a) to 2 (d).
第２図（ａ）参照 厚さ350μｍのSnドープ（100）n+−InP基板（ｎ＝２
×1018cm-3）１の上に，厚さ２μｍのSnドープｎ−InP
（ｎ＝２×1016cm-3）のバッファ層２を有機金属化学気
相推積（MOCVD）法によりエピタキシャル成長する。See FIG. 2A. Sn-doped (100) n + -InP substrate having a thickness of 350 μm (n = 2
× 10 18 cm -3 ) 2 μm thick Sn-doped n-InP
The buffer layer 2 (n = 2 × 10 16 cm −3 ) is epitaxially grown by metal organic chemical vapor deposition (MOCVD).
第２図（ｂ）参照 Gaソースとしてトリメチルガリウム,Asソースとして
アルシンを用い，基板温度を450℃にしてバッファ層２
の上に,SnドープGaAs層（ｎ＝２×1015cm-3）を原子層
エピタキシーにより,5原子層成長する。１原子層とはGa
とAsの一対の層をいい,5原子層の厚さは14Åである。Referring to FIG. 2 (b), trimethylgallium is used as the Ga source, arsine is used as the As source, the substrate temperature is set to 450 ° C., and the buffer layer 2 is used.
Then, a Sn-doped GaAs layer (n = 2 × 10 15 cm −3 ) is grown by atomic layer epitaxy to form a 5-atomic layer. One atomic layer is Ga
And a pair of layers of As, and the thickness of the five atomic layer is 14Å.
第２図（ｃ）参照 GaAsのエピタキシャル原子層３の上に,Alを厚さ1000
Åに蒸着してAl電極４を形成する。See FIG. 2 (c). On top of the GaAs epitaxial atomic layer 3, Al is
Then, the Al electrode 4 is formed by vapor deposition.
第２図（ｄ）参照 n+−InP基板１側にAuとSnを蒸着しアロイ化して厚さ3
000Åの基板側電極５を形成する。See FIG. 2 (d). Au and Sn are vapor-deposited and alloyed on the n + -InP substrate 1 side to have a thickness of 3
A substrate-side electrode 5 of 000 mm is formed.
Al電極４はショットキー電極を形成し，基板側電極５
はオーミック電極を形成する。The Al electrode 4 forms a Schottky electrode, and the substrate-side electrode 5
Forms an ohmic electrode.
このようにして製造したショットキー接合型ダイオー
ドは，介在させたGaAsエピタキシャル原子層３の厚さは
極めて小さく，空乏層の広がりはInPのキャリア濃度と
外から印加した電圧だけで正確にきまる。このことは,C
−Ｖ測定から求めた1/C2−Ｖプロットが直線になること
から確かめられた。In the Schottky junction type diode manufactured as described above, the thickness of the interposed GaAs epitaxial atomic layer 3 is extremely small, and the spread of the depletion layer is accurately determined only by the carrier concentration of InP and the voltage applied from outside. This means that C
This was confirmed from the fact that the 1 / C 2 -V plot obtained from the -V measurement became a straight line.
また，順方向の電流−電圧特性 IF＝Aexp（qVF/nkT） から決まる理想因子ｎの値がほぼ１になった。Also, forward current - the value of the ideal factor n which is determined from the voltage characteristic I F = Aexp (qV F / nkT) it was almost 1.
これらのことから，空乏層がInP内に広がっており，
実効的にほぼ完全なInPショットキー接合が形成されて
いると考えることができる。From these facts, the depletion layer has spread in InP,
It can be considered that a substantially complete InP Schottky junction is formed effectively.
第３図にこのショットキー接合ダイオードのエネルギ
ーバンド図を示す。空乏層がバッファ層２のInP結晶内
に形成され，実効的にInPショットキー接合が形成され
ている。InPとGaAsのエネルギーギャップEgは，常温で
それぞれ,1.35eV,1.42eVである。FIG. 3 shows an energy band diagram of this Schottky junction diode. A depletion layer is formed in the InP crystal of the buffer layer 2, effectively forming an InP Schottky junction. The energy gap E g of InP and GaAs, respectively at room temperature, 1.35 eV, which is 1.42 eV.
逆方向の暗電流も，従来のｐ−ｎ接合の場合に比べて
著しく減少した。これは,GaAsエピタキシャル原子層３
の成長温度が450℃であるので，従来，熱拡散で問題と
なっていた熱ダメージがほとんどなくなったためであ
る。The dark current in the reverse direction was also significantly reduced as compared with the conventional pn junction. This is the GaAs epitaxial atomic layer 3.
This is because the thermal damage, which has conventionally been a problem in thermal diffusion, has almost disappeared because the growth temperature of GaN is 450 ° C.
良好なInPショットキー接合が実効的に形成されるGaA
sエピタキシャル原子層３の厚さは３原子層以上で，上
限は40層程度である。GaAs that effectively forms a good InP Schottky junction
The thickness of the s epitaxial atomic layer 3 is 3 atomic layers or more, and the upper limit is about 40 layers.
なお，本実施例ではｎ型のInP結晶にｎ型のGaAsエピ
タキシャル原子層を形成したが,p型のInP結晶上にｐ型
のGaAsエピタキシャル原子層を形成するようにしてもよ
い。In this embodiment, an n-type GaAs epitaxial atomic layer is formed on an n-type InP crystal. However, a p-type GaAs epitaxial atomic layer may be formed on a p-type InP crystal.
InP FETのゲート部の形成に，以上述べた方法を適用
できることは勿論である。It goes without saying that the method described above can be applied to the formation of the gate portion of the InP FET.
〔発明の効果〕 以上説明した様に，本発明によれば，従来形成が困難
であったInPのショットキー接合を実効的に形成するこ
とができる。[Effects of the Invention] As described above, according to the present invention, a Schottky junction of InP, which has been difficult to form conventionally, can be effectively formed.
本発明は，高温プロセスを必要とせずにInPのショッ
トキー接合が実現できるので,InPを基板とする光電子集
積回路に適用するとき，効果が大きい。INDUSTRIAL APPLICABILITY The present invention can realize a Schottky junction of InP without requiring a high-temperature process, and is therefore highly effective when applied to an optoelectronic integrated circuit using InP as a substrate.
第１図はInP結晶上のGaAs原子層を模式的に示す図， 第２図（ａ）乃至（ｄ）は実施例で，ショットキー接合
ダイオードの製造工程を説明するための断面図， 第３図はエネルギーバンド図 である。図において， １はInP基板であってn+−InP基板， ２はバッファ層であってｎ−InP結晶， ３はGaAsエピタキシャル原子層， ４は金属電極であってAl電極， ５は基板側電極 を表す。FIG. 1 is a diagram schematically showing a GaAs atomic layer on an InP crystal. FIGS. 2 (a) to 2 (d) are embodiments, and are cross-sectional views for explaining a manufacturing process of a Schottky junction diode. The figure is an energy band diagram. In the figure, 1 is an InP substrate and n + -InP substrate, 2 is a buffer layer and n-InP crystal, 3 is a GaAs epitaxial atomic layer, 4 is a metal electrode and an Al electrode, 5 is a substrate side electrode. Represents
Claims (1)
aAsエピタキシャル原子層（３）を原子層エピタキシー
により形成した後，該GaAsエピタキシャル原子層（３）
に接して金属電極（４）を形成することにより，実効的
にInPのショットキー接合を形成する工程を含むことを
特徴とする半導体装置の製造方法。1. One conductivity type G is formed on a one conductivity type InP crystal (2).
After forming an aAs epitaxial atomic layer (3) by atomic layer epitaxy, the GaAs epitaxial atomic layer (3)
Forming a metal electrode (4) in contact with the semiconductor device, thereby effectively forming an InP Schottky junction.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18098689A JP2789689B2 (en) | 1989-07-12 | 1989-07-12 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18098689A JP2789689B2 (en) | 1989-07-12 | 1989-07-12 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0344967A JPH0344967A (en) | 1991-02-26 |
| JP2789689B2 true JP2789689B2 (en) | 1998-08-20 |
Family
ID=16092744
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18098689A Expired - Lifetime JP2789689B2 (en) | 1989-07-12 | 1989-07-12 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2789689B2 (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6951804B2 (en) | 2001-02-02 | 2005-10-04 | Applied Materials, Inc. | Formation of a tantalum-nitride layer |
| US6878206B2 (en) | 2001-07-16 | 2005-04-12 | Applied Materials, Inc. | Lid assembly for a processing system to facilitate sequential deposition techniques |
| US6911391B2 (en) | 2002-01-26 | 2005-06-28 | Applied Materials, Inc. | Integration of titanium and titanium nitride layers |
| US6833161B2 (en) * | 2002-02-26 | 2004-12-21 | Applied Materials, Inc. | Cyclical deposition of tungsten nitride for metal oxide gate electrode |
| JP5684449B2 (en) * | 2008-07-30 | 2015-03-11 | 株式会社Sumco | Measuring method of specific resistance value of semiconductor wafer |
-
1989
- 1989-07-12 JP JP18098689A patent/JP2789689B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0344967A (en) | 1991-02-26 |
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