JP2788461B2 - Processing machine status detector - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial application field) The present invention relates to a state detection device of a processing machine.

(Prior art) A numerical control device (hereinafter abbreviated as NC device) is attached to various processing machines such as a punch press and a laser processing machine, and two-dimensional XY axes, three-dimensional XYZ axes, and the like are attached to the numerical control devices. While driving, the loader, unloader and other attached devices are controlled to perform predetermined processing.

Here, the above-mentioned NC device is equipped with software for performing various controls, and this software is often prepared by the manufacturer of the processing machine, and the user substitutes numerical values for parameters of the software. This allows the machine to perform a desired operation.

However, with the above-mentioned processing machines, software that has been carefully created on the manufacturer side may still have so-called bugs, causing the user to perform unexpected operations during actual processing or stop unexpectedly. Abnormal situations such as accidents may occur.

Therefore, conventionally, in order to deal with such a situation, a technician has been dispatched from the manufacturer side, the cause has been determined, and predetermined measures have been taken.

(Problems to be Solved by the Invention) However, the conventional countermeasures described above involve a method of observing the current state at the time of machine stop and performing a work of reviewing the software when it is determined that there is a cause in the software. Therefore, it was difficult to re-create the same abnormal situation, and it took a considerable amount of time before it was determined that the software had the cause. Also, even if it is determined that the cause is in the software, it takes a lot of trouble and time to remove the bug. Furthermore, since the machine on the user side is stopped during this time, there is a problem that the operation rate of the machine is reduced, and in some cases, the entire factory line is stopped to make the delivery time short.

Therefore, an object of the present invention is to provide a state detection device of a processing machine that can quickly determine the cause of a machine failure and can immediately take a countermeasure.

[Constitution of the Invention] (Means for Solving the Problems) In view of the conventional problems as described above, the present invention provides a numerical control device and a processing machine controlled by the numerical control device as shown in FIG. A bit change detecting means 1 for detecting a change in bit information indicating a command condition between the two at a predetermined sampling period, and a state of change of the bit information detected by the bit change detecting means 1 is stored in a ring buffer memory or a shift buffer. Change information storage means 2 for sequentially storing in a register memory, power supply backup means 3 for backing up the power of the memory of the change information storage means 2, and the contents stored in the memory when an abnormality has occurred in the processing machine. Operating means 4 for instructing information output from the latest information to older information sequentially, and bits stored in the memory based on the instruction of the operating means 4 Find the command status corresponding to the broadcast from the message table, a configuration in which a change state informing means 5 allowed to display on the display device ON or OFF indicating the bit information and command status and status.

(Example) Next, an example in which the present invention is applied to a punch press equipped with an NC device will be described.

FIG. 2 is a block diagram of an NC device attached to the punch press.

As shown in the figure, the NC device includes a CPU 6, a ROM 7, RAMs 8A, 8B, and a digital input (hereinafter abbreviated as DI) 10 and a digital output (hereinafter abbreviated as DO) 11 , A programmable controller (hereinafter abbreviated as PC) 12.

The RAM 8A is a readable and writable memory, and is used to store required data during processing of the CPU 6. The NC program is also used here as a load.

The RAM 8B is a 16-KB readable / writable memory that is backed up by a power supply. In this example, 4 KB is used for writing a bit change whose state is detected as described later.

The DI 10 and DO 11 are connected to various actuators such as an induction motor 13 of a punch press and various sensors via a connector module 14.

DI10 can receive up to 48 signals from PC12
Alternatively, it is stored as a 0 bit signal.

The DO 11 stores up to 48 types of signals output from the PC 12 to the machine as 1 or 0 bit signals.

The PC 12 stores machine operation procedures in a programmable manner.The CPU 6 stores up to 96 signals input from the PC 12 by the CPU 6 as a DI image as 1 or 0 bit signals to the CPU 6, and the CPU 6 A maximum of 96 signals to be output to the memory are also stored as DO images with 1 or 0 bit signals.

The system bus 9 has another bidirectional RAM (DP
-RAM 15, a plurality of serial communication interfaces (also referred to as SIOs) 16, 17 and a parallel communication interface (hereinafter, referred to as PIO) 18.

The DP-RAM 15 includes an interpolation calculation unit provided for each axis XY in order to drive a servomotor M having an encoder E and a tacho generator TG via a servo amplifier 19.
It is connected to the CPU 20 and mainly performs high-speed exchange of axis control data between the CPU 6 and the interpolation calculation unit 20.

The SIO 16 is connected to a control device 23 of a CRT 21 and a manual data input (hereinafter referred to as MDI) panel 22 to serially transmit display information to the CRT 21 and to input an operation signal from the MDI panel 22 as a serial signal. belongs to.

The SIO 17 is connected to the control device 25 of the control panel 24 and transmits a serial signal input from the control panel 24 to the CPU 6 or the like.

The PIO 18 is for inputting parallel data input from the paper tape reader 26.

FIG. 3 is an explanatory diagram showing the operating system of the NC device in a module configuration.

As shown in the figure, an operation processing module M2 that manages various operation modes, a man-machine interface module M3 that manages the relationship between human and machine, and an axis drive are provided below a main module M1 that supervises and manages the entire NC device. And DI and DO
For example, an operation control module M4 for managing items associated with operations is arranged.

Below the operation processing module M2, there is an automatic operation module
M5 and homing module M6 and manual operation module
M7 is arranged. Below the man-machine interface module M3, a CRT and an MDI control module M8 are arranged. Below the operation control module M4, a drive axis control module M9 and a DI or DO control module M10 are arranged.

In the above-described module configuration, a lower module is arranged and managed under a higher module, so that the entire system operates smoothly.
More specifically, each of the modules M1 to M10 confirms a situation under its own control in units of 8 ms, and executes necessary commands to other modules.

FIG. 4 is a flowchart of a state detection process performed every 8 msec in the operation processing module M2.

In step 401, the latest bit information indicating the command status is input for one of the image signals of the DI10, DO11 and PC12.

In step 402, the bit information indicating the previous command status is compared with the bit information indicating the current command status.

In step 403, it is determined whether or not there is bit information different from the previous bit information among the current bit information. If there is a change, the process proceeds to step 404, and if not, the process proceeds to step 406.

In step 404, the changed bit number is written into the RAM 8B as shown in FIG.

In step 405, the pointer 27 for marking the write position is counted up as shown in FIG.
The pointer 27 is stored in the RAM 8B and is backed up by a power supply.

In step 406, it is determined whether or not an abnormality has occurred in the various operation modes managed by the operation processing module M2. If an abnormality has occurred, the sampling is forcibly terminated, and the process proceeds to the original process. Move on to 407.

If an abnormality occurs in the machine, step 406 is performed at this point.
In order to issue a sampling end command at, if the contents of RAM8B are checked after the inspector arrives, even if the machine is operated during this time, since the contents of RAM8B will not change thereafter, the cause of the abnormality can be accurately determined. This is because it can be grasped.

In step 407, the end of all the bits is determined, and steps 402 to 406 are repeated until the end of all the bits is performed.
And the pointer is counted up according to the number.

Accordingly, as shown in FIG. 6, the changed bit numbers are sequentially written to the RAM 8B, and the last write position is indicated by the pointer 27.

Here, in the next control cycle, it is assumed that data is written from the next address in the RAM 8B, and when the last address 4096 is written, the address is shifted to address 1 in a ring buffer and the previous information is updated.

That is, if there is an average of one bit change in one sampling process, 4096 bits are assigned to address 4096 of RAM 8B.
A full history of bit changes, ie, about 33 seconds, will be written.

FIG. 5 is a flowchart of a status display process performed by the CRT and MDI control module M8.

In step 501, after the occurrence of the abnormality, it is determined whether or not there is a monitoring output command from the MDI panel 22, and if there is no monitoring output command, the process proceeds to the original processing.
If there is, the process proceeds to step 502.

In step 502, the value indicated by the pointer 27 shown in FIG. 6 is input.

In step 503, the RAM 8B is searched based on the pointer value, and the bit information written at the designated address is read.

In step 504, referring to the message table 28 shown in FIG. 7 based on the read bit information, for example, the "press start signal"
Then, as shown in FIG. 8, a bit state, that is, ON or OFF, is added to this, and the display is shifted from the lower side of the screen 21A of the CRT 21 to the upper side with respect to the previous display. That is, the next 450
The number distribution completion ON is displayed in order, such as being displayed above the number 451 press start signal ON.

In step 505, the pointer 27 is counted down.

In step 506, it is determined that the inspector determines an abnormality and instructs the end of the display. Then, the state of the machine change is displayed using the message table 28.

As described above, in the punch press state detection device of this example,
DI10, DO11, and PC1 up to the time when the error occurred
The status of DI and DO images of 2 is stored only for bits that have changed in chronological order and displayed on the CRT21, so the cause of the error can be pursued reliably and quickly with a small memory capacity, and countermeasures for the error can be taken promptly. be able to.

Here, since all the bit information is examined to determine the cause of the abnormality, it is possible to pursue the cause and the position of the software bug shown in the conventional example, and of course, it is not related to the software. An abnormality of the machine itself can also be determined.

In the above embodiment, the detected bit change information is
Is displayed on the printer, but this may be output to a printer, or sent to the manufacturer via a telephone line, and stored in an information medium such as an IC card, and then stored in the manufacturer. Alternatively, it may be decrypted by using.

The present invention is not limited to the above embodiments, but can be implemented in an appropriate mode by making appropriate design changes.

[Effects of the Invention] As can be understood from the above description of the embodiments, in short, the present invention provides a method for changing bit information indicating a command state between a numerical controller and a processing machine controlled by the numerical controller. Bit change detecting means (1) for detecting at a predetermined sampling period, and the bit change detecting means (1)
Change information storage means (2) for sequentially storing the state of change of bit information detected by the memory in a ring buffer-like memory or a shift register-like memory, and power supply backup means for backing up the memory of the change information storage means (2) (3) operating means (4) for instructing the output of the contents stored in the memory from the latest information to the older information in a state where the above occurs in the processing machine; and The command status corresponding to the bit information stored in the memory is searched from the message table based on the command, and ON or OF indicating the bit information and the command status and status is displayed.
A change state notifying means (5) for displaying F on a display device.

That is, according to the present invention, bit information indicating a command condition between the numerical controller and the processing machine is sampled at a predetermined cycle, a change in the bit information is detected, and the state of the change is sequentially stored in, for example, a ring buffer memory. When an abnormality occurs in the processing machine, the latest information stored in the memory is output sequentially from the latest information, and the bit information, command status and status can be displayed on the display device. Can be quickly determined.

At this time, since the change of the bit information is detected and sequentially stored in, for example, a ring buffer type memory, even if the memory has a small capacity, the history of the bit information can be known over a predetermined range before the occurrence of the abnormality. The cause of the occurrence can be more reliably determined.

[Brief description of the drawings]

FIG. 1 is a view showing an outline of the present invention, FIG. 2 and subsequent figures show an embodiment, FIG. 2 is a block diagram of an NC device attached to a punch press, and FIG. 3 shows a module configuration of the NC device. FIG. 4 is a flowchart of a state detection process performed by the operation processing module, FIG. 5 is a flowchart of a state display process performed by the CRT control module, and FIG. 6 is a memory that stores bit change information in time series FIG. 7 is an explanatory diagram of a message table used at the time of display, and FIG. 8 is an explanatory diagram of a CRT screen. DESCRIPTION OF SYMBOLS 1 ... Bit change detection means 2 ... Change information storage means 3 ... Power supply backup means 4 ... Operation means 5 ... Change state notification means 10 ... Digital input 11 ... Digital output 12 ... Programmable controller 8A … Power supply backup RAM 21A …… CRT screen 28 …… Message table

Claims (1)

(57) [Claims] 1. A bit change detecting means (1) for detecting a change in bit information indicating a command state between a numerical controller and a processing machine controlled by the numerical controller at a predetermined sampling period, A change information storage means (2) for sequentially storing a change state of bit information detected by the change detection means (1) in a ring buffer type memory or a shift register type memory, and a memory of the change information storage means (2). A power supply backup unit (3) for backing up a power supply; an operation unit (4) for instructing information output from the latest information to the older information sequentially from the contents stored in the memory when an abnormality occurs in the processing machine; A command status corresponding to the bit information stored in the memory is searched from a message table based on a command from the operating means (4), and the bit information and ON or show a decree situation as well as the state
Change state notifying means for displaying OFF on the display device (5)
And a state detecting device for a processing machine.