JP2785165B2 - Burst signal phase detection circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to BPSK, QPSK
For example, an N-phase PSK (Phase Shift K) that generally allocates N-phase (N ≧ 2) carrier phases to N modulation symbols.
The present invention relates to a phase detection circuit provided for receiving and demodulating a digital modulation signal using eying) as a modulation method, when the digital modulation signal is periodically transmitted in a burst form.

[0002]

2. Description of the Related Art As a detection method used in a phase detection circuit for receiving and demodulating a digital modulation signal by N-phase PSK, a synchronous detection method and a delay detection method are conventionally known. Among them, in the synchronous detection method, a reproduced carrier signal that is phase-synchronized with an input carrier signal to a demodulator obtained from a received signal is generated, and the phase of the input carrier signal is detected using the reproduced carrier signal as a reference signal. The modulation information is determined from the phase change. On the other hand, in the delay detection method, a phase of the input carrier signal is detected by using a signal obtained by delaying the input carrier signal by one symbol length as a reference signal, and modulation information is determined from the phase change.

[0003]

Among the above-mentioned conventional systems, the synchronous detection system can absorb a frequency offset of an input carrier signal to some extent by carrier synchronization.
Since the noise included in the reference signal can be suppressed, the detection performance for the frequency offset and the thermal noise is superior to the differential detection method. However, the synchronous detection method has a limited response speed due to a phase locked loop with respect to a carrier signal, and is not suitable for a case where high-speed detection processing must be performed for each burst, such as periodic burst transmission in the TDMA method. . On the other hand, the differential detection method is generally suitable for burst transmission since phase synchronization with an input carrier signal is not necessary. However, the delay detection method has a disadvantage that when the input carrier signal has a frequency offset, the transmission quality is significantly deteriorated because the input carrier signal does not have a frequency offset absorption capability by phase synchronization.

Generally, to compensate for a frequency offset,
AFC (Automated Frequency Detection) that detects the amount of received frequency offset from the input carrier signal and suppresses the frequency offset before detection by negative feedback to the frequency control terminal of the local oscillator.
atic Frequency Control) configuration is effective. For the detection of the reception frequency offset amount, a method of directly measuring the frequency of the input carrier signal by a counter, a method of measuring the frequency by replacing the frequency with a voltage by a frequency discriminator, and the like are known. However, this AFC configuration also forms a negative feedback loop inside, so the response speed is limited,
There is a problem that it is not suitable for burst transmission. An object of the present invention is to eliminate the influence of the frequency offset of an input carrier signal, which is a problem in the conventional technique, in a periodic burst transmission such as a TDMA scheme, and to realize a circuit. An object of the present invention is to provide a phase detection circuit that can be easily miniaturized, integrated, and reduced in power consumption.

[0005]

SUMMARY OF THE INVENTION A phase detection circuit according to the present invention receives a burst signal formed of a digitally modulated signal based on N-phase PSK (N ≧ 2) and obtains a demodulated output. A local oscillation circuit having an oscillation frequency substantially equal to the center frequency, a phase detection circuit for receiving an oscillation output of the local oscillation circuit, and obtaining a phase detection output of the input carrier signal with reference to the oscillation output; A delay circuit for delaying the detection output by one symbol length,
A phase difference circuit that calculates and outputs a phase difference between the phase detection output and the output of the delay circuit; and receives the phase difference and outputs the phase among N standard phase difference values determined by the N-phase PSK. A provisional decision circuit that outputs a standard phase difference closest to the difference as a provisional decision value, a first adder that calculates and outputs a phase difference error obtained by subtracting the provisional decision value from the phase difference, And an averaging circuit that calculates and outputs an average value of the phase difference error from a predetermined number of sample values, and stores and holds the average value of the phase difference error according to an externally provided sampling clock, and a plurality of different transmissions. A register circuit for individually storing a stored value of the average value of the phase difference error corresponding to each transmitting station when receiving the burst signals having no temporal overlap from a station; The memory retention value of the average value of a given said phase difference error from the road by subtracting from the phase difference output from the phase difference circuit for outputting an estimated value of the phase difference 2
And a determination circuit that inputs the estimated value of the phase difference, determines the standard phase difference closest to the estimated value, and outputs the result as the demodulated output.

[0006]

SUMMARY OF THE INVENTION A phase detection circuit according to the present invention receives a burst signal formed of a digitally modulated signal based on N-phase PSK (N ≧ 2) and obtains a demodulated output. A phase detection circuit which receives an oscillation output of a local oscillation circuit having an oscillation frequency substantially equal to a center frequency and obtains a phase detection output of the input carrier signal with reference to the oscillation output; A delay circuit that delays by the time, a phase difference circuit that calculates and outputs a phase difference between the phase detection output and the output of the delay circuit, and determines a standard phase difference closest to the phase difference and outputs the result as the demodulated output. The phase difference output from the phase difference circuit is input, and the N standard phase difference values determined by the N-phase PSK are input to the phase detection circuit. A tentative determination circuit that outputs a standard phase difference closest to the phase difference as a tentative determination value, a first adder that calculates and outputs a phase difference error obtained by subtracting the tentative determination value from the phase difference, An averaging circuit that calculates and outputs an average value of the phase difference error from a predetermined number of sample values of the phase difference error, and stores and holds the average value of the phase difference error in accordance with an externally provided sampling clock; A register circuit for individually storing the stored value of the average value of the phase difference error corresponding to each transmitting station when receiving the burst signals having no temporal overlap from different transmitting stations; and The storage value of the provided average value of the phase difference error is subtracted from the phase difference output from the phase difference circuit to obtain an estimated value of the phase difference, which is provided to the determination circuit. It is characterized in that a second adder.

FIG. 3 is a diagram showing characteristics of a phase comparison output a (broken line) based on exclusive OR in the above configuration and a phase comparison output b (thick solid line) based on a D-type flip-flop. The horizontal axis in FIG. 3 shows the input phase difference between the DEM-IN and the LO, and the vertical axis shows the phase comparison output. As shown, the input phase differences are -π to 0 radians and 0 to π radians. “a” is a triangular characteristic that rises and falls linearly, and “b” is a step characteristic that takes two values of “0” and “1”. Accordingly, by performing complement switching on the digital value of a according to the polarity of b by the complement switching circuit 26 of FIG. 2, −π as shown by the dashed line in FIG.
Obviously, a phase detection output θ that varies linearly with an input phase difference of π radians is obtained.

Returning to FIG. 1, reference numeral 3 denotes a phase detection output θ of 1
This is a delay circuit that delays by the symbol length of time, and is composed of a shift register or the like. 4 is θ and θ by the delay circuit 3
Is a phase difference circuit for calculating a phase difference Δθ between the value of the output and the one-symbol length delay output θ ′. In addition, 4 is a characteristic of the phase detection output θ shown in FIG. 3, and an apparent phase jump corresponding to ± 2π radian which appears when the values of θ and θ ′ pass ± π radian is caused by overflow of the adder. It also has a function of absorbing the used 2π radians by conversion. Reference numeral 5 denotes a tentative determination circuit which receives the phase difference Δθ obtained from the phase difference circuit 4 and receives the digital phase modulation method (N
Phase PSK) N standard phase difference values Δθ ₁ , Δ
Of the θ ₂ ,..., Δθ _N (hereinafter referred to as the standard phase difference), the standard phase difference Δθ _i (i∈
{1, 2,..., N}) are output as provisional determination values.

FIG. 4 is an explanatory diagram of the above-mentioned provisional judgment operation, and shows an example in the case of QPSK (N = 4) as an example. FIG. 4 is a diagram in which the phase difference Δθ is represented by a point on the circumference. In the case of QPSK, an example of an array of the _four standard phase differences Δθ ₁ , Δθ ₂ , Δθ ₃ , and Δθ ₄ is shown in FIG.
Π / 4, 3π / 4, -3π / 4, −
π / 4 (radian). The example shown is π
In this example, an odd multiple of / 4 radian is used as the standard phase difference, but an integer multiple of π / 2 radian (0, π / 2, π, −π
/ 2) (illustration omitted). now,
In FIG. 4, the phase difference Δθ input to the temporary determination circuit 5
Is the value indicated by ● in the figure, the provisional judgment circuit 5
Standard phase difference [Delta] [theta] ₁ to the temporary decision value output closest to theta. At this time, the phase difference error Δθ _e between Δθ ₁ and Δθ is |
Δθ _e | <π / 4. That is, in the example of FIG.
With 0, π / 2, ± π, and -π / 2 as thresholds, the areas of Δθ with the standard phase differences Δθ ₁ , Δθ ₂ , Δθ ₃ , and Δθ ₄ as tentative judgment values are respectively 0 <Δθ <π / 2, π / 2 <Δ
It can be seen that it suffices to set θ <π, −π <Δθ <−π / 2, −π / 2 <Δθ <0. The above judgment function is performed by an adder, a digital numerical comparator, or a table ROM (Rea).
d Only Memory).

[0010] Again back to FIG. 1, 6 [Delta] [theta] and the temporary decision value [Delta] [theta] _i of the temporary decision circuit 5 phase difference error; Δθ _e = Δθ-
Adder for calculating the [Delta] [theta] _i, 7 is an average circuit for obtaining the mean value <[Delta] [theta] _e> of [Delta] [theta] from the sample value _e of the [Delta] [theta] _e of the predetermined number, the average method is simple average, weighted average with forgetting factor Various digital filtering techniques can be applied. Reference numeral 8 denotes a register circuit, which has the above average value <Δ according to an externally supplied sampling clock (SCL).
θ _e > to update the stored value. When the register circuit receives burst signals from a plurality of different transmitting stations that do not overlap with each other in time, the storage location of the stored value of <Δθ _e > is individually set for each burst signal of each transmitting station. Shall be provided. 9 subtracts the stored value of <Δθ _e > obtained from the register 8 from Δθ, thereby removing the influence of the frequency offset from the estimated value of Δθ.
An adder for determining Δθ>. 10 is the above <Δθ
> In accordance with the same rule as that of the provisional judgment circuit 5, <Δθ
> Is determined, and the demodulated output DEM-
This is a determination circuit that outputs the signal to the outside as OUT.

[0011]

The operation of the present invention based on the configuration example of FIG. 1 will be described below. In the configuration of FIG. 1, the local oscillator circuit 1 and a phase detection circuit phase detection output theta detected by 2, modulation other phase component theta _m, the input carrier signal DEM-IN and the initial phase between the local oscillator output LO An error component θ ₀ , a phase error component θ _e due to frequency offset, and a phase error component θ _n due to noise are included. That is, it is shown by the following (1).

(1) θ = θ _m + θ ₀ + θ _e + θ _n (radian) (1) In the right side of the equation (1), the modulation phase component θ _m is given by the following equation (2).

(Equation 1)

[Outside 1] Δθ _i indicates the ith selected standard phase difference. The phase error component due to the frequency offset theta _e is a frequency offset Delta] f (Hz), comprising one symbol length T farther To the following equation (3).

(Equation 3) As described above, the phase difference Δθ of one symbol length calculated by the delay circuit 3 and the phase difference circuit 4 of FIG.
From equation (3), the following equation (4) is obtained.

Δθ = Δθ _i + 2πΔfT + Δθ _n (4) where Δθ _n is a one symbol length difference value of a phase error component due to noise. Since the initial phase error component θ ₀ is lost by the one symbol length difference processing, it is not included in the equation (4). Therefore, if the influence of the frequency offset Δf is excluded, the initial phase error component θ ₀ is calculated from the phase difference Δθ. Modulation component Δθ
_It can be seen that the delay detection operation of determining _i is performed.

[0012] Now, the temporary decision circuit 5 in FIG. 1, since the temporary determination of the frequency offset Delta] f [Delta] [theta] _i influence from [Delta] [theta] in a form including a take place now, most assumed that there is no error in the tentative decision value [Delta] [theta] _i Then, the phase difference error Δθ _e obtained from the adder 6 becomes the following equation (5) from the equation (4).

Δθ _e = Δθ−Δθ _i ≒ 2πΔfT + Δθ _n (5) In equation (5), it is assumed that the difference value Δθ _n of the phase error component θ _n due to noise does not include a bias. Assuming that the average value is 0 radians, Δθ _e by the averaging circuit 7
The following equation (6) is obtained as the average value <Δθ _e >.

<Δθ _e > ≒ <2πΔfT + Δθ _n > = 2πΔfT (6) (where <·> is an averaging process) <Δθ _e > in the equation (6) is a sampling clock ( (SCL), and the stored value is subtracted from the phase difference value Δθ obtained from the phase difference circuit 4 by the adder 9, so that the value of the adder 9 is calculated from the equations (4) and (6). Output <Δθ>
Is given by the following equation (7).

<Δθ> = Δθ− <Δθ _e > ≒ Δθ _i + Δθ _n (7) Therefore, the estimated value <Δθ> of the phase difference from which the influence value of the frequency offset Δf is removed is calculated by the adder 9. It is clear that the estimated value is obtained at the output,
It can be seen that by determining the standard phase difference closest to θ> and using the result as the demodulated output, the phase detection operation in which the influence of the frequency offset is removed is performed.

Here, an operation example and an effect when the present invention is applied to reception and demodulation of a periodic burst signal such as a TDMA system will be described with reference to FIGS. FIG. 5 is a time chart showing an operation example of the register circuit 8 when a periodic burst signal in the TDMA system is received. FIG. 5A shows a point-to-point communication using an arbitrary slot in a TDMA frame. The case of is shown.
The top row of (A) schematically illustrates a 1 slot / frame periodic burst signal having a frequency offset Δf. The middle stage is a sampling clock (SCL) supplied to the register circuit 8, which is given in synchronism with the same signal within a burst signal section at a frequency of 2 samples / burst in the illustrated example. The lower part shows a change in the stored value of <Δθ _e > supplied from the register circuit 8 to the adder 9. As shown, the register circuit 8
Sampling clock (SCL) pulses A, B, C,
Corresponding to D, given from the averaging circuit 7 immediately before each of the pulse value of _{<Δθ e>, <Δθ e} > A, <Δθ e>
_B , <Δθ _e > _C and <Δθ _e > _D are sequentially stored and held, and the average value <Δθ _e > _B obtained by the pulse B is updated to the average value <Δθ _e > _C in the corresponding slot of the next frame. Since the stored data is stored and supplied to the adder 9, it is understood that the demodulation in which the influence of the frequency offset is removed from the head of the burst can be performed in the corresponding slot in the next frame.

Next, FIG. 5B shows a case of the point-to-multipoint communication using a plurality of frames in the TDMA frame, and sequentially receives burst signals from a plurality of different transmitting stations (child stations). An example of one receiving station (master station) for demodulation is shown. Uppermost (B) is a periodic burst signal of slots / frame represents schematically, the S slots, the S + 1 each burst signal from the slot ...... the assigned slave station frequency offset Delta] f _s ,
Δf _{s + 1} ,... The second stage is (A)
5 shows the same sampling clock (SCL). Third and fourth stages, the first S slots and memory retention value of <[Delta] [theta] _e> According to the S + 1 register circuit 8 for each burst signal of each transmission stations allocated slot <[Delta] [theta] _e>
^(s) and the change of <Δθ _e > ^{(s + 1)} . As is clear from the figure, the register circuit 8 outputs the pulses A, S of the sampling clock SCL for each burst signal.
<Δθ given from the averaging circuit 7 immediately before each pulse corresponding to B, C, D and E, F, G, H, respectively.
_e > ^(s) and <Δθ _e > ^{(s + 1)} , ie, <Δθ _e >
_A ^(s) , <Δθ _e > _B ^(s) , <Δθ _e > _C ^(s) , <Δθ
_e > _D ^(s) , and <Δθ _e > _E ^{(s + 1)} , <Δθ _e > _F
^{(s + 1)} , <Δθ _e > _G ^{(s + 1)} , and <Δθ _e > _H ^{(s + 1)} are sequentially stored and held.

In the above operation, the average values <Δθ _e > _B ^(s) and <Δθ _e > _F ^{(s + 1)} of the burst signals at the respective slot positions obtained by the pulse B and the pulse F are obtained.
Are stored and held in each slot in the next frame until the average value is updated to <Δθ _e > _C ^(s) and <Δθ _e > _G ^{(s + 1)} , respectively. Since each is sequentially supplied to the adder 9, it is possible to perform demodulation in which the influence of the frequency offset of each slave station is removed from the burst head of the next slot at each slot position, as in the case of (A). It turns out that it becomes.

Next, FIG. 6 is an actual measurement example in which the performances of a phase detection circuit based on the configuration of the present invention and a conventional phase detection circuit are compared. The modulation method of this measurement example is π / 4 shift QPSK.
The transmission side has 100% Nyquist filtering, a low-off rate of 0.5, a transmission speed of 384 kbps, and a frequency of an input carrier signal to the demodulation system of 10.7 MHz. The communication mode is the Point described in FIG.
-To-Point communication. The configuration of TDMA is 8 slots / frame, 224 bits / burst, and each burst is composed of 16 bits of a unique word for synchronization, 196 bits of information, and 12 bits of overhead including a preamble. The horizontal axis of FIG. 6 is the offset frequency Δf (kHz) with respect to the center frequency of the input carrier signal of 10.7 MHz, and the vertical axis is the bit error rate of the information portion (196 bits / burst) when the power of the input carrier signal is constant. (BER). The pulse period of the sampling clock (SCL) supplied to the register circuit 8 in the phase detection circuit based on the configuration of the present invention is set to 16 bits. According to the figure, when the absolute value of the frequency offset Δf is around 10 kHz, the BE
It can be seen that while R causes one digit deterioration, the phase detection circuit according to the configuration of the present invention hardly deteriorates. In the configuration of the present invention, the temporary determination value Δ
Since it is assumed that there is almost no error in θ _i , the phase error 2πΔfT due to the frequency offset for each symbol appearing in the equation (6) is equal to the QPS shown in FIG.
As the absolute value of the standard phase difference in the case of K approaches the minimum value π / 4 radian (Δf = ± 24 kHz in FIG. 6),
The effect of the demodulation limit due to an increase in errors in the provisional determination value Δθ _i and a large error in the average value <Δθ _e > can also be confirmed from the figure.

[0017]

As described above in detail, according to the present invention, even when a high-speed demodulation operation such as a periodic burst transmission in the TDMA system is required, the influence of the frequency offset can be eliminated. The performance is also effective in a case where a plurality of transmitting stations having different frequency offsets are supported. Further, since most of the processing included in the configuration of the present invention can be realized by a simple digital circuit not including a multiplier, the circuit is reduced in size, integrated circuit, and reduced in power consumption as compared with an AFC circuit configuration using an analog circuit. Is very easy.

[Brief description of the drawings]

FIG. 1 is a configuration example diagram of a burst signal phase detection circuit according to the present invention.

FIG. 2 is a configuration example diagram of a phase detection circuit 2 of FIG. 1;

FIG. 3 is a diagram showing a phase comparison characteristic between an exclusive OR and a D-type flip-flop;

FIG. 4 is an explanatory diagram in which a phase difference Δθ is represented by points on a circumference.

FIG. 5 is a time chart showing an operation example of the register circuit 8 when receiving a periodic burst signal in the TDMA system.

FIG. 6 is an actual measurement diagram comparing the performances of the phase detection circuit of the present invention and a conventional phase detection circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Local oscillation circuit 2 Phase detection circuit 3 Delay circuit 4 Phase difference circuit 5 Temporary judgment circuit 6 Adder 7 Averaging circuit 8 Register circuit 9 Adder 10 Judgment circuit 21 Comparator 22 Exclusive OR gate 23 D type flip-flop 24 Low Bandpass filter 25 A / D converter 26 Complementary switching circuit

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-3-274844 (JP, A) JP-A-4-172040 (JP, A) JP-A-4-259150 (JP, A) JP-A-5-259 75661 (JP, A) JP-A-3-263937 (JP, A) 1991 IEICE Spring National Convention 2-375 1992 IEICE Spring National Convention, Transactions, Volume 2, P.E. 2-344 1991 IEICE Spring National Convention, Transactions, Volume 2, 2-360 1991 IEICE Spring National Convention, Transactions, Volume 2, 2-376 (58) Field surveyed (Int. Cl. ⁶ , DB name) H04L 27/22 H04L 27/227

Claims (1)

(57) [Claims] 1. A local oscillator having an oscillation frequency substantially equal to the center frequency of an input carrier signal in order to receive a burst signal formed of a digital modulation signal based on N-phase PSK (N ≧ 2) and obtain a demodulated output. A phase detection circuit that receives an oscillation output of a circuit and obtains a phase detection output of the input carrier signal with reference to the oscillation output; a delay circuit that delays the phase detection output by one symbol length; A phase difference circuit that calculates and outputs a phase difference between the output and the output of the delay circuit, and a determination circuit that determines a standard phase difference closest to the phase difference and outputs the result as the demodulated output. The phase difference output from the phase difference circuit is input, and the standard phase difference closest to the phase difference among the N standard phase difference values determined by the N-phase PSK A temporary determination circuit that outputs a temporary determination value, a first adder that calculates and outputs a phase difference error obtained by subtracting the temporary determination value from the phase difference, and a predetermined number of sample values of the phase difference error An averaging circuit that calculates and outputs an average value of the phase difference error; and stores and holds the average value of the phase difference error according to a sampling clock supplied from the outside, and overlaps with time from a plurality of different transmission stations. A register circuit for individually storing a storage value of the average value of the phase difference error corresponding to each transmitting station when receiving the burst signal having no signal, and storing the average value of the phase difference error provided from the register circuit A second adder for obtaining an estimated value of the phase difference by subtracting the held value from the phase difference output from the phase difference circuit and providing the estimated value to the determination circuit. Phase detection circuit of the burst signal.