JP2784797B2 - Wiring formation method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a wiring forming method, and is particularly suitable to be applied to a case where multiple wirings are performed.

[Summary of the Invention] The present invention relates to a method for forming a wiring, wherein charged particles are contained in an atmosphere containing a gaseous raw material on the wiring at least at an intersection of a wiring formed on a substrate and a wiring above the wiring. By irradiating the beam, an insulating film made of a hydrocarbon-based substance generated from the above-mentioned raw material is formed, and the upper wiring is formed on the insulating film.
As a result, multiple wiring can be performed without causing disconnection in an extremely fine region.

[Conventional technology]

FIG. 4 shows an example of a conventional semiconductor integrated circuit having a two-layer wiring structure. As shown in FIG. 4, in this semiconductor integrated circuit, a first-layer wiring 102 is formed on a semiconductor substrate 101 via an interlayer insulating film not shown. This wiring 102
On top of this, an interlayer insulating film 103 is formed.
A second-layer wiring 104 is formed thereon. The second layer wiring 104 is in contact with the first layer wiring 102 through the contact holes C ₁ and C ₂ formed in the interlayer insulating film 103.

FIG. 5 shows another example of a conventional semiconductor integrated circuit having a two-layer wiring structure. As shown in FIG. 5, in this semiconductor integrated circuit, a resist (not shown) was formed only at a portion where it was desired to jump over the first layer wiring 102, and a second layer wiring 104 was formed on this resist. Later, the resist is dissolved and removed to perform a two-layer wiring.

FIG. 6 shows an example of a conventional semiconductor integrated circuit having a three-layer wiring structure. As shown in FIG. 6, in this semiconductor integrated circuit, an interlayer insulating film 1 is formed on a first-layer wiring 102 formed on a semiconductor substrate 1 via an interlayer insulating film (not shown).
03 is formed, and a second-layer wiring 104 is formed on the interlayer insulating film 103.
Are formed. The second-layer wiring 104 is in contact with the first-layer wiring 102 through contact holes C ₃ and C ₄ formed in the interlayer insulating film 103. Further, an interlayer insulating film 105 is formed on the second layer wiring 104, and a third layer wiring 106 is formed on the interlayer insulating film 105. The third-layer wiring 106 is put in contact with the first layer of wiring 102 through a contact hole C ₅ formed in the interlayer insulating film 103 and 105.

[Problems to be solved by the invention]

In the conventional wiring forming method shown in FIGS. 4 and 6, the same number of interlayer insulating films as the number of wiring layers is required. That is, to form a two-layer wiring, two layers of interlayer insulating films are required, and to form a three-layer wiring, three layers of interlayer insulating films are required. In addition, for example, in the example shown in FIG. 6, in order to make the second-layer wiring 104 and the third-layer wiring 106 contact the first-layer wiring 102, the contact holes C ₃ , Since C ₄ and C ₅ must be formed, these contact holes C ₃ and C 5
_4, a possibility that the second layer of the disconnection of the wiring 104 and the third-layer wiring 106 occurs at a higher portion of the C _5. The problem of the disconnection becomes more serious as the wiring is multiplexed.

Further, it is difficult to form multiple wirings in an extremely fine area of, for example, about several hundreds of square meters in any of the above-described conventional wiring forming methods. For example, in the method shown in FIG.
In order to prevent disconnection of step 4, it is necessary to make the shape of the resist formed on the first-layer wiring 102 gentle, so that it is difficult to perform double wiring in an extremely fine region by this method. .

Therefore, an object of the present invention is to perform multiple wiring without disconnection in an extremely fine region, and to further reduce the parasitic capacitance between the wirings. An object of the present invention is to provide a wiring forming method capable of preventing a delay.

[Means for solving the problem]

In order to achieve the above object, the present invention provides a method for forming a wiring, wherein at least an intersection between a wiring (2) formed on a substrate (1) and a wiring (5) above the wiring (2) is provided. By irradiating a charged particle beam (3) in an atmosphere containing a gaseous raw material on the wiring (2), an insulating film (4) made of a hydrocarbon-based substance generated from the raw material is formed. (4) An upper wiring (5) is formed thereon.

As the charged particle beam (3), an electron beam, a positron beam, a muon beam, or the like can be used.
When an electron beam is used, a field emission electron gun (field em
Preferably, an ission gun is used.

[Action]

According to the above-mentioned means, the beam diameter of the charged particle beam (3) can be extremely narrowed to, for example, about several tens of degrees. Therefore, even considering the influence of the multiple scattering of the charged particle beam (3), for example, about 200 degrees. It is possible to form an extremely fine insulating film (4) having a size of the order. Also, in this case,
Reflecting that the intensity distribution of the charged particle beam (3) is Gaussian, the cross-sectional shape of the insulating film (4) has a gentle Gaussian shape. Accordingly, the upper wiring (5) formed on the insulating film (4) has almost no possibility of disconnection at the portion of the insulating film (4). In addition, since the hydrocarbon-based material forming the insulating film has a small dielectric constant, the parasitic capacitance between the wiring and the upper wiring that sandwich the insulating film can be extremely reduced.

As described above, by alternately repeating the formation of the insulating film by the irradiation of the charged particle beam (3) and the formation of the wiring, multiple wiring can be performed without disconnection in an extremely fine region. The parasitic capacitance between them can be made extremely small, whereby a signal delay caused by this parasitic capacitance can be prevented.

〔Example〕

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In all the drawings of the embodiments, the same portions are denoted by the same reference numerals.

Embodiment I FIGS. 1A and 1B show Embodiment I of the present invention.

As shown in FIG. 1A, in this embodiment I, a high vacuum (for example,
The semiconductor substrate 1 is placed in a sample chamber evacuated to about 3 × 10 ⁻⁷ Torr). As the semiconductor substrate 1, for example, a silicon (Si) substrate or a gallium arsenide (GaAs) substrate can be used. Further, it is assumed that the first wiring 2 having an extremely fine width of, for example, about 200 ° is formed on the semiconductor substrate 1 via an interlayer insulating film (not shown). The semiconductor substrate 1 is placed on a sample stage whose temperature can be controlled by a temperature controller. Next, a source gas for forming an insulating film, such as gaseous alkylnaphthalene, is introduced into the sample chamber. The pressure of the source gas in the sample chamber is, for example, a value within a range of 10 ⁻⁷ to 10 ⁻⁵ Torr, for example,
It should be about 10 ^-6 Torr. When the pressure of the source gas in the sample chamber reaches a predetermined value, an electron beam 3 is generated by, for example, a field emission electron gun (not shown), and the beam diameter of the electron beam 3 is narrowed to, for example, about several tens of degrees. The beam 3 is scanned on the wiring 2 under the control of the electron beam controller. In this case, the acceleration voltage of the electron beam 3 is, for example, 0.5
A value within the range of ~ 6 kV. The beam current is, for example, 1
The value should be in the range of 0 ^-13 to 10 ^-7 A.

In the above-described source gas atmosphere, source gas molecules are adsorbed on the surfaces of the wiring 2 and the substrate 1. When the electron beam 3 is irradiated on the adsorbed raw material molecules as described above, the raw material molecules in the portion irradiated with the electron beam 3 are decomposed, and as a result, the amorphous hydrocarbon (C _m H _n) A) insulating material is generated in the same shape as the drawing pattern of the electron beam 3. Thus, the wiring 2 in along with amorphous hydrocarbon so as to cover the wiring 2 (C _m H _n) insulating film 4 made of a material system is formed. In this case, since the thickness of the insulating film 4 formed by one drawing with the electron beam 3 is usually small, the drawing of the electron beam 3 is repeated as necessary to obtain the insulating film 4 having a required film thickness.

After the wiring 2 is covered with the insulating film 4 as shown in FIG. 1B in this manner, a second-layer wiring 5 having an extremely fine width is formed on the insulating film 4 and the substrate 1 by, for example, substantially orthogonal to the wiring 2. It is formed so that In this case, electrical insulation between the first-layer wiring 2 and the second-layer wiring 5 is performed by the insulating film 4.

It should be noted that the first and second wirings
Can be formed, for example, as follows. That is, for example, after a metal film (not shown) for forming a wiring is formed on the entire surface of the semiconductor substrate 1 by, for example, a vapor deposition method or a sputtering method, the metal film is formed in a raw material gas atmosphere such as a gaseous alkylnaphthalene. An electron beam 3 is irradiated thereon in a predetermined pattern to form an ultra-fine resist pattern made of an amorphous hydrocarbon-based material. The resist pattern is used as a mask by, for example, a reactive ion etching (RIE) method. Etch the metal film.
Thereby, the wiring 2 having an extremely fine width can be formed. The wiring 5 having an extremely fine width can be formed in the same manner. It has been confirmed by the present inventors that a resist made of this amorphous hydrocarbon-based material has excellent dry etching resistance. In addition, these wiring
The layers 2 and 5 can also be formed directly by irradiating the semiconductor substrate 1 with the electron beam 3 in an atmosphere of a source gas containing a metal, for example.

As described above, according to the embodiment I, the insulating film 4 having the gentle cross-sectional shape of the Gaussian distribution is formed on the first wiring 2 by the irradiation of the electron beam 3 in the source gas atmosphere. Since the second-layer wiring is formed on the insulating film 4, the second-layer wiring 5 is not likely to be disconnected at the insulating film 4. Further, since the insulating film 4 can have an extremely fine width, double wiring can be performed in an extremely fine region.

Further, an amorphous hydrocarbon constituting the insulating film 4 (C _m H _n)
Since the material of the system has a small dielectric constant, the parasitic capacitance between the first and second wirings 2 and 5 opposed to each other with the insulating film 4 interposed therebetween can be extremely reduced. Signal delay can be prevented.

Example II FIG. 2 shows Example II of the present invention.

In the embodiment I, the insulating film 4 is formed over the entire length of the first-layer wiring 2, whereas in the second embodiment, as shown in FIG. The insulating film 4 is formed only on the first wiring 2 in the same manner as in Example I, and the second wiring 5 is formed on the insulating film 4.

According to the embodiment II, as in the embodiment I, the insulating film 4
Is similar to that of Example I, because the shape of is gentle so that disconnection of the second layer wiring 5 at the portion of the insulating film 4 can be prevented, and double wiring can be performed in an extremely fine region. There are significant advantages. In particular, as described above, forming an extremely fine insulating film 4 only at the intersection of the first-layer wiring 2 and the second-layer wiring 5 to perform interlayer insulation is performed by irradiating the electron beam 3 with this insulating film. 4 can be realized only by using the method of forming 4.

Embodiment III FIG. 3 shows an embodiment III of the present invention.

As shown in FIG. 3, in this embodiment III, a part of the first wiring 2 formed on the semiconductor substrate 1 via an interlayer insulating film, not shown, is partially insulated in the same manner as in the embodiment II. After the film 4 is formed, a second-layer wiring 5 and a third-layer wiring 6 are formed on the insulating film 4 to form three-layer wirings 2, 5, and 6. Here, these second-layer and third-layer wirings 5 and 6 are directly connected to the first-layer wiring 2 in portions other than the insulating film 4.

According to the embodiment III, the second and third wiring layers 5, 6
Can be formed without step disconnection, and triple wiring can be performed in an extremely fine region. In addition, there are the following advantages. That is, three-layer wirings 2, 5, and 6 can be formed without using a three-layer interlayer insulating film as in the related art. Further, it is not necessary to form a contact hole for contacting the second and third wiring layers 5 and 6 with the first wiring layer 2 as in the prior art, and these second and third wiring layers 5 and 6 need not be formed. , 6 can be directly contacted with the first layer wiring 2. Therefore, there is no problem of disconnection of the wiring at the contact hole. Furthermore, these wirings 2, 4,
6 can have the same height. Then, as shown in FIG. 3, a flat surface can be obtained even after the formation of the three layers of wirings 2, 5, and 6, which is advantageous in proceeding with subsequent processes.

Although the embodiments of the present invention have been specifically described above, the present invention is not limited to the above-described embodiments, and various modifications based on the technical idea of the present invention are possible.

For example, in the above-described Examples I, II, and III, the case where a two-layer wiring or a three-layer wiring is formed has been described. However, the present invention can be applied to a case where four or more layers of wiring are formed. Of course there is. In this case, the same advantages as those of the above-described embodiments I, II, and III can be obtained regardless of the number of layers of the wiring. The more the wirings are multiplexed, the more remarkable the advantage of the present invention becomes.

〔The invention's effect〕

Since the present invention is configured as described above, multiplex wiring can be performed without generating a step in an extremely fine region, and the parasitic capacitance between the wirings can be extremely reduced. Thus, signal delay caused by the parasitic capacitance can be prevented.

[Brief description of the drawings]

1A and 1B are perspective views for explaining the embodiment I of the present invention in the order of steps, FIG. 2 is a perspective view for explaining the embodiment II of the present invention, and FIG. FIGS. 4 and 5 are sectional views for explaining a conventional wiring forming method, and FIG. 6 is a perspective view for explaining a conventional wiring forming method. It is. Description of main reference numerals in the drawings: 1: semiconductor substrate, 2: first layer wiring, 3: electron beam, 4: insulating film, 5: second layer wiring, 6: third layer wiring.

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-61-4224 (JP, A) JP-A-63-11672 (JP, A) JP-A-2-963 (JP, A) (58) Investigation Field (Int.Cl. ⁶ , DB name) H01L 21/31 H01L 21/312-21/3213 H01L 21/768

Claims (2)

(57) [Claims] 1. A method of irradiating a charged particle beam in an atmosphere containing a gaseous raw material on at least an intersection of a wiring formed on a substrate and a wiring above the wiring in an atmosphere containing a gaseous raw material. A method of forming a wiring, comprising: forming an insulating film made of a hydrocarbon-based substance to be generated; and forming the upper wiring on the insulating film. 2. The method according to claim 1, wherein said hydrocarbon-based material is amorphous.