JP2782797B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JP2782797B2 JP2782797B2 JP15611089A JP15611089A JP2782797B2 JP 2782797 B2 JP2782797 B2 JP 2782797B2 JP 15611089 A JP15611089 A JP 15611089A JP 15611089 A JP15611089 A JP 15611089A JP 2782797 B2 JP2782797 B2 JP 2782797B2
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- wiring layer
- heating
- wafer
- temperature
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
【発明の詳細な説明】 〔概要〕 アルミニウム系配線層の形成方法に関し, 段差被覆改善のための加熱による配線金属の結晶粒の
粗大化を抑制し,デバイスの製造歩留と信頼性を向上す
ることを目的とし, 基板上にアルミニウム(Al)又はその合金からなる配
線層を被着した後,該基板を加熱すると同時に該配線層
表面にイオンを照射する工程を有するように構成する。DETAILED DESCRIPTION OF THE INVENTION [Overview] Regarding a method for forming an aluminum-based wiring layer, the present invention suppresses coarsening of wiring metal crystal grains due to heating for improving step coverage, thereby improving device manufacturing yield and reliability. For this purpose, a method is provided in which, after a wiring layer made of aluminum (Al) or an alloy thereof is deposited on a substrate, the substrate is heated and, at the same time, the surface of the wiring layer is irradiated with ions.
本発明は半導体装置の製造方法に係り,特にアルミニ
ウム系配線層の形成方法に関する。The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming an aluminum-based wiring layer.
現在,半導体装置の配線材料としては主にAl又はAlを
主成分とする合金(1%Si,2%Cu等)が用いられ,その
成膜方法としてはスパッタ法が多く用いられている。At present, Al or an alloy mainly containing Al (1% Si, 2% Cu, or the like) is mainly used as a wiring material of a semiconductor device, and a sputtering method is often used as a film forming method.
本発明は配線層の成膜後の処理方法として適用するこ
とができる。The present invention can be applied as a processing method after forming a wiring layer.
近年,素子の微細化及び配線構造の多層化により配線
しようとする下地基板の段差形状がより厳しくなってき
ているため,良好な段差被膜を持つ配線を形成すること
が困難となってきている。In recent years, because the underlying substrate to be wired has become stricter in shape due to miniaturization of elements and multi-layered wiring structure, it has become difficult to form a wiring having a good step coating.
現在,このような問題を克服するためにスパッタ成膜
中の基板温度を高温にすることにより,被膜の被覆性及
び基板の平坦性を改善している。At present, in order to overcome such problems, by increasing the substrate temperature during sputter deposition, the coatability of the film and the flatness of the substrate are improved.
又,基板にバイアスをかけてスパッタを行い,堆積と
エッチングを同時に行って段差部に生ずる庇を削りなが
ら堆積することにより段差被覆を改善する方法等がとら
れている。In addition, a method of improving the step coverage by applying a bias to the substrate, performing deposition and etching at the same time, and depositing while shaving the eaves generated at the step portion is adopted.
しかしながら,スパッタ中に基板温度を正確に再現性
良く高温にするには装置的にかなり複雑となり,又,ス
パッタ中の基板温度を正確に知ることは困難であり,経
験的な見地から基板温度を設定する等により成膜条件を
決定している場合が多い。However, accurately raising the substrate temperature with good reproducibility during sputtering requires considerable equipment complexity, and it is difficult to accurately know the substrate temperature during sputtering. In many cases, film forming conditions are determined by setting or the like.
そこで,Al又はAl合金配線層をスパッタ法等で基板上
に被着した後,被処理基板を成膜後大気中に開放しない
で高温に加熱することにより,この問題を解決するとい
う提案がなされている。Therefore, it has been proposed to solve this problem by depositing an Al or Al alloy wiring layer on a substrate by sputtering or the like, and then heating the substrate to be processed to a high temperature without opening to the atmosphere after film formation. ing.
上記の従来の提案により段差被覆を改善するために
は,配線層を融点近くの再結晶化温度以上に加熱する場
合が多いため,条件によってはAlの結晶粒が粗大化して
しまう。これに対し,結晶粒径を加熱温度以外の条件設
定で制御することは困難である。In order to improve the step coverage by the above-mentioned conventional proposal, the wiring layer is often heated to a temperature higher than the recrystallization temperature near the melting point, so that the Al crystal grains become coarse depending on the conditions. On the other hand, it is difficult to control the crystal grain size by setting conditions other than the heating temperature.
結晶粒が粗大化すると,配線層表面に突出したり,配
線抵抗の増大化或いは配線層の信頼性を低下させること
になる。When the crystal grains become coarse, they protrude to the surface of the wiring layer, increase the wiring resistance, or lower the reliability of the wiring layer.
本発明は配線層を成膜する際,段差被覆改善のための
加熱による配線金属の結晶粒の粗大化を抑制し,デバイ
スの製造歩留と信頼性を向上することを目的とする。SUMMARY OF THE INVENTION It is an object of the present invention to suppress the coarsening of crystal grains of wiring metal due to heating for improving step coverage when forming a wiring layer, and to improve the production yield and reliability of devices.
上記課題の解決は、基板上にアルミニウム(Al)又は
その合金からなる配線層を被着した後、該基板を該配線
層の融点以下であって且つ400℃以上に加熱すると同時
に該配線層表面に稀ガス類、プロトン、Si又はTiの少な
くとも一種のイオンを照射する工程を有する半導体装置
の製造方法により達成される。In order to solve the above-mentioned problem, after a wiring layer made of aluminum (Al) or an alloy thereof is deposited on a substrate, the substrate is heated to a temperature lower than the melting point of the wiring layer and higher than 400 ° C. And a step of irradiating at least one ion of rare gas, proton, Si or Ti.
本発明は配線金属の融点付近の温度では,金属原子が
拡散するのに十分なエネルギを持ち移動性が増すため表
面張力の作用により段差部での被覆性が改善され,基板
の平坦化が得られることを利用する点は従来例と同様で
あるが,この際,金属結晶内で再結晶化が進み結晶粒が
粗大化するのを抑制し制御するために,例えば,基板を
高温加熱し且つAr雰囲気中で基板にRF電圧を印加してAr
イオンを照射するようにしたものである。According to the present invention, at a temperature near the melting point of the wiring metal, the metal atoms have sufficient energy to diffuse and the mobility increases, so that the surface tension acts to improve the coverage at the step portion and obtain a flat substrate. However, in this case, in order to suppress and control the progress of recrystallization in the metal crystal and the coarsening of the crystal grains, for example, heating the substrate at a high temperature and Applying RF voltage to the substrate in Ar atmosphere
The ion irradiation is performed.
これは,表面でのAl原子の移動性をArイオンの入射に
より抑制したための効果によるものであり,その結果が
結晶粒径に反映されたものと考えられる。This is due to the effect of suppressing the mobility of Al atoms on the surface by the incidence of Ar ions, and the result is considered to be reflected in the crystal grain size.
ここで,配線金属の融点は次のようである。純Alは66
0℃,Al−1%Si合金は600℃,Al−2%Cu合金は620℃で
ある。Here, the melting point of the wiring metal is as follows. Pure Al 66
The temperature is 0 ° C, the temperature of the Al-1% Si alloy is 600 ° C, and the temperature of the Al-2% Cu alloy is 620 ° C.
次に,本発明の要点である,Arの入射エネルギ(又は
基板バイアス電圧)に対する平均結晶粒径の関係を示す
データを説明する。Next, data showing the relationship between the incident energy of Ar (or the substrate bias voltage) and the average crystal grain size, which is a gist of the present invention, will be described.
第3図は基板バイアス電圧に対する平均結晶粒径の関
係を示す図である。FIG. 3 is a diagram showing the relationship between the average crystal grain size and the substrate bias voltage.
図は,Al−1%Si配線層に加熱温度500℃て基板バイア
スをかけた場合のデータの一例で,基板バイアス電圧の
増加とともに平均結晶粒径が漸減し一定値に近づく様子
を示す。The figure shows an example of data when a substrate bias is applied to an Al-1% Si wiring layer at a heating temperature of 500 ° C., and shows how the average crystal grain size gradually decreases as the substrate bias voltage increases and approaches a constant value.
第4図は加熱温度に対する平均結晶粒径の関係を示す
図である。FIG. 4 is a diagram showing the relationship between the heating temperature and the average crystal grain size.
図は,Al−1%Si配線層に対し,加熱温度が400℃を越
えると結晶粒成長が顕著になり,平均結晶粒径が急増す
る様子を示す。The figure shows that when the heating temperature exceeds 400 ° C. for the Al-1% Si wiring layer, the crystal grain growth becomes remarkable, and the average crystal grain size increases rapidly.
第1図は本発明の一実施例を説明するRF印加式基板加
熱装置の断面図である。FIG. 1 is a sectional view of an RF application type substrate heating apparatus for explaining an embodiment of the present invention.
図において,加熱ステージ1上にスパッタ室から搬送
されてきた被処理基板であるSiウエハ2が載せられ,固
定治具3で固定される。In the figure, a Si wafer 2 as a substrate to be processed, which has been transferred from a sputtering chamber, is placed on a heating stage 1 and fixed by a fixing jig 3.
アノード7及びシールド8は接地され,加熱ステージ
1はマッチング回路11,RF電源10を経て接地される。The anode 7 and the shield 8 are grounded, and the heating stage 1 is grounded via the matching circuit 11 and the RF power supply 10.
加熱ステージ1はカートリッジヒータ9により加熱さ
れ,チャンバ5内で気密を保ちながら上下する構造にな
っており,上(図示の位置)は処理位置,下は搬送位置
である。The heating stage 1 is heated by a cartridge heater 9 and moves up and down while maintaining airtightness in the chamber 5. The upper position (the position shown) is the processing position, and the lower position is the transfer position.
又,加熱ステージ1は懐形状をなし内部は大気圧でカ
ートリッジヒータ9やヒータ固定ブロックや図示しない
が熱電対等が設けられ,外部は減圧側になっている。The heating stage 1 has a pocket shape and the inside is at atmospheric pressure. A cartridge heater 9 and a heater fixing block, a thermocouple (not shown) are provided, and the outside is on the decompression side.
固定されたウエハ2の裏側からは,ウエハを均一に加
熱するためにArガスが導入され,その流量はウエハ裏面
でのArガスの圧力が約1Torrになるようにマスフローコ
ントローラ12を制御する。Ar gas is introduced from the back side of the fixed wafer 2 to uniformly heat the wafer, and the flow rate thereof is controlled by the mass flow controller 12 so that the pressure of the Ar gas on the back surface of the wafer becomes about 1 Torr.
又,チャンバ5内のArガスの圧力は3mTorrになるよう
にマスフローコントローラ4,12からチャンバ5内に入る
流量及び排気口6の排気速度を制御する。Further, the flow rate of the Ar gas in the chamber 5 from the mass flow controllers 4 and 12 into the chamber 5 and the exhaust speed of the exhaust port 6 are controlled so as to be 3 mTorr.
以上のようにしてウエハ2を550℃に加熱して,これ
にRF電源10により周波数13.56MHzのRF電圧〜500Vを印加
した状態で2分間保つ。As described above, the wafer 2 is heated to 550 ° C., and the RF power source 10 applies the RF voltage of 13.56 MHz to 500 V and holds the wafer 2 for 2 minutes.
550℃加熱の場合,結晶粒径はRF電圧の印加をしない
場合は〜10μmであったのが,RF電圧の印加をした実施
例では〜3μmとなった。In the case of heating at 550 ° C., the crystal grain size was 1010 μm when the RF voltage was not applied, but was 〜3 μm in the example where the RF voltage was applied.
ウエハへのArイオンの照射はRF電圧の印加以外に,DC
電圧の印加,またはイオンミリングガンによるAr等のイ
オンビームを用いてもよい。Irradiation of Ar ions on the wafer is performed by DC
A voltage may be applied, or an ion beam of Ar or the like by an ion milling gun may be used.
第2図はスパッタ処理を含めた連続処理装置の構成の
一例を示す断面図である。FIG. 2 is a sectional view showing an example of a configuration of a continuous processing apparatus including a sputtering process.
図において,ウエハは矢印の方向に搬送され,その構
成は,この順にロードロック室21,スパッタ処理室22,実
施例のRF印加式基板加熱装置23,ロードロック室24から
なり,ゲートバルブ23〜29はウエハの搬入用と,各室の
連結用と,ウエハの搬出用のものである。In the figure, the wafer is transported in the direction of the arrow, and is composed of a load lock chamber 21, a sputter processing chamber 22, an RF application type substrate heating device 23 of the embodiment, and a load lock chamber 24 in this order. Numeral 29 is for carrying in the wafer, connecting the chambers, and carrying out the wafer.
この装置により,スパッタ処理後のウエハを大気中に
開放することなしに本発明の処理を行うことができる。With this apparatus, the processing of the present invention can be performed without opening the wafer after the sputtering processing to the atmosphere.
又,一旦大気中に出したウエハでも,RF又はイオンミ
リングの装置を備えることにより,イオン照射により表
面の酸化物を除去することができるので,単独の装置と
しても使用できる。In addition, even if the wafer is once put into the atmosphere, the surface oxide can be removed by ion irradiation by providing a device for RF or ion milling, so that it can be used as a single device.
本発明では配線金属結晶内で再結晶化が進み結晶粒が
粗大化するのを抑制するためにイオンを照射しているの
で,照射イオンは配線金属を侵さないガスのイオンや金
属イオンであればよいと考えられる。In the present invention, ions are irradiated in order to suppress the progress of recrystallization in the wiring metal crystal and the coarsening of the crystal grains. Therefore, the irradiation ions are gas ions or metal ions that do not attack the wiring metal. It is considered good.
従って,作用の説明及び実施例においては照射するイ
オンとしてArを用いたが,これの代わりにその他の不活
性ガス,即ちHe,Ne,Kr,Xe,Rnや,プロトンを用いても,
またはSi,Ti等のイオンを注入しても同様の効果が期待
できる。Therefore, although Ar was used as the ion to be irradiated in the description of the operation and the examples, other inert gas, that is, He, Ne, Kr, Xe, Rn, or proton, could be used instead.
Alternatively, the same effect can be expected by implanting ions such as Si and Ti.
以上説明したように本発明によれば,配線層を成膜す
る際,段差被覆改善のための加熱による配線金属の結晶
粒の粗大化を抑制でき,デバイスの製造歩留と信頼性を
向上することができる。As described above, according to the present invention, when forming a wiring layer, coarsening of crystal grains of wiring metal due to heating for improving step coverage can be suppressed, and the device manufacturing yield and reliability are improved. be able to.
【図面の簡単な説明】 第1図は本発明の一実施例を説明するRF印加式基板加熱
装置の断面図, 第2図はスパッタ処理を含めた連続処理装置の構成の一
例を示す断面図, 第3図は基板バイアス電圧に対する平均結晶粒径の関係
を示す図, 第4図は加熱温度に対する平均結晶粒径の関係を示す図
である。 図において, 1は加熱ステージ, 2は被処理基板でウエハ, 3は固定治具, 4はマスフローコントローラ, 5はチャンバ, 6は排気口, 7はアノード, 8はシールド, 9はカートリッジヒータ, 10はRF電源, 11はマッチング回路 12はマスフローコントローラ である。BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional view of an RF-applied substrate heating apparatus for explaining an embodiment of the present invention, and FIG. 2 is a cross-sectional view showing an example of a configuration of a continuous processing apparatus including a sputtering process. FIG. 3 is a diagram showing the relationship between the average crystal grain size and the substrate bias voltage, and FIG. 4 is a diagram showing the relationship between the average crystal grain size and the heating temperature. In the figure, 1 is a heating stage, 2 is a wafer to be processed, 3 is a fixing jig, 4 is a mass flow controller, 5 is a chamber, 6 is an exhaust port, 7 is an anode, 8 is a shield, 9 is a cartridge heater, 10 Is an RF power supply, 11 is a matching circuit, and 12 is a mass flow controller.
Claims (1)
からなる配線層を被着した後、該基板を該配線層の融点
以下であって且つ400℃以上に加熱すると同時に該配線
層表面に稀ガス類、プロトン、Si又はTiの少なくとも一
種のイオンを照射する工程を有することを特徴とする半
導体装置の製造方法。1. After a wiring layer made of aluminum (Al) or an alloy thereof is deposited on a substrate, the substrate is heated to a temperature lower than the melting point of the wiring layer and higher than 400 ° C. A method for manufacturing a semiconductor device, comprising a step of irradiating at least one kind of ions of a rare gas, proton, Si or Ti.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15611089A JP2782797B2 (en) | 1989-06-19 | 1989-06-19 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15611089A JP2782797B2 (en) | 1989-06-19 | 1989-06-19 | Method for manufacturing semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH0321025A JPH0321025A (en) | 1991-01-29 |
JP2782797B2 true JP2782797B2 (en) | 1998-08-06 |
Family
ID=15620531
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP15611089A Expired - Fee Related JP2782797B2 (en) | 1989-06-19 | 1989-06-19 | Method for manufacturing semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2782797B2 (en) |
-
1989
- 1989-06-19 JP JP15611089A patent/JP2782797B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JPH0321025A (en) | 1991-01-29 |
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