JPH01244615A - Film formation process - Google Patents

Film formation process

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Publication number
JPH01244615A
JPH01244615A JP7299288A JP7299288A JPH01244615A JP H01244615 A JPH01244615 A JP H01244615A JP 7299288 A JP7299288 A JP 7299288A JP 7299288 A JP7299288 A JP 7299288A JP H01244615 A JPH01244615 A JP H01244615A
Authority
JP
Japan
Prior art keywords
film
semiconductor wafer
wafer
etching
gas
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7299288A
Other languages
Japanese (ja)
Other versions
JP2509820B2 (en
Inventor
Noriyoshi Narita
知徳 成田
Kimihiro Matsuse
公裕 松瀬
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tokyo Electron Ltd
Original Assignee
Tokyo Electron Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Electron Ltd filed Critical Tokyo Electron Ltd
Priority to JP7299288A priority Critical patent/JP2509820B2/en
Publication of JPH01244615A publication Critical patent/JPH01244615A/en
Application granted granted Critical
Publication of JP2509820B2 publication Critical patent/JP2509820B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Chemical Vapour Deposition (AREA)

Abstract

PURPOSE:To prevent increase of electrical contact resistance and to enable a metallic thin film to be formed uniformly and stably, by completely removing a naturally oxidized film before formation of the film. CONSTITUTION:When mounting of a semiconductor wafer 2 on a mounting board 3 is finished, a hand arm 17 is retracted into a transportation preliminary chamber 20 and a gate valve 16 is closed. Under these conditions, cleaning of the wafer is carried out by etching off a naturally oxidized film formed on the wafer 2. After the etching, a metallic thin film is formed on the surface to be treated of the semiconductor wafer 2 by means of CVD process. The mounting board 3 carrying the semiconductor wafer 2 is formed of a quartz glass plate having a light-transmitting conductive film 4 thereon, so that, during the cleaning process, electric power can be applied to the light-transmitting conductive film 4 for converting treating gas uniformly into plasma and for realizing stable etching operation. Further, according to such arrangement, stable and uniform film formation can be obtained since the CVD can be performed while infrared rays as heating light is applied to the wafer from the side of the mounting board 3.

Description

【発明の詳細な説明】 〔発明の目的〕 (産業上の利用分野) この発明は、成膜方法に関する。[Detailed description of the invention] [Purpose of the invention] (Industrial application field) The present invention relates to a film forming method.

(従来の技術) 一般に、半導体集積回路に金属薄膜を堆積させて配線等
を行なう技術として、長年の間、蒸着やスパッタリング
等の物理的気相成長方法(PVD)が使用されてきた。
(Prior Art) In general, physical vapor deposition (PVD) methods such as vapor deposition and sputtering have been used for many years as a technique for depositing metal thin films on semiconductor integrated circuits for wiring and the like.

しかし、超LSI等集積回路の高集積化・高速化・高密
度化に伴い、ゲート電極やコンタクト・ホールやスルー
・ホール等の形成の為に、多結晶Siに比べ抵抗が1桁
以上低いW(タングステン)等の高融点金属の金属薄膜
を堆積させる技術が重要となってきている。
However, as integrated circuits such as VLSIs become more highly integrated, faster, and more densely packed, the resistance of W, which is more than an order of magnitude lower than that of polycrystalline Si, is required to form gate electrodes, contact holes, through holes, etc. Techniques for depositing metal thin films of high melting point metals such as (tungsten) are becoming important.

上記のような金属薄膜を形成する手段としては。As a means for forming the metal thin film as described above.

膜成長用ガスを被処理基板の被処理面上に成長させるメ
タルCVD装置で金属薄膜を形成している。
A metal thin film is formed using a metal CVD apparatus that grows a film growth gas on the processing surface of a processing target substrate.

又、最近では、膜厚をより均一に形成するために、被処
理基板を石英板に固定し、石英板側から赤外光等の加熱
光を照射することにより被処理基板を加熱して、この加
熱した状態でCVD処理を行なしかしながら、上記のよ
うなCVD装置による金属薄膜を形成する場合、このC
VD処理をする前工程装置から被処理基板例えば半導体
ウェハをCVD装置に移送する時に、半導体ウェハの表
面に自然酸化膜が例えば数十人程度形成されてしまい、
この酸化膜上に金属薄膜を形成したとしても、シリコン
と金属の間の電気的接触抵抗が高くなり、品質の低下に
つながるという問題点があった。
Recently, in order to form a more uniform film thickness, the substrate to be processed is fixed to a quartz plate and heated by irradiating heating light such as infrared light from the quartz plate side. While performing CVD treatment in this heated state, when forming a metal thin film using the above-mentioned CVD apparatus, this carbon
When a substrate to be processed, such as a semiconductor wafer, is transferred from a pre-processing device for VD processing to a CVD device, a natural oxide film of, for example, about several dozen is formed on the surface of the semiconductor wafer.
Even if a metal thin film is formed on this oxide film, there is a problem in that the electrical contact resistance between silicon and metal increases, leading to a decrease in quality.

又、例えば処理ガスをプラズマ化し半導体ウェハ上に形
成された自然酸化膜をエツチングした後に、金fmr薄
膜を形成することが考えられるが、成膜する時に膜厚を
均一にするために赤外光を照射する場合、半導体ウェハ
は透明で絶縁性の石英等に固定されているため、反応ガ
スを供給したとしてもプラズマ化しなかったり、プラズ
マ発生領域が限られてしまい、自然酸化膜を均一にエツ
チングできないという問題点があった。
Also, for example, it is possible to form a gold FMR thin film after turning the processing gas into plasma and etching the natural oxide film formed on the semiconductor wafer, but in order to make the film thickness uniform during film formation, infrared light is When irradiating semiconductor wafers, the semiconductor wafer is fixed to transparent, insulating quartz, etc., so even if a reactive gas is supplied, it may not turn into plasma, or the plasma generation area is limited, making it difficult to uniformly etch the natural oxide film. The problem was that it couldn't be done.

この発明は上記点に対処してなされたもので、金属:4
膜を成膜する前に、自然酸化膜を完全に除去することに
より、電気的接触抵抗の増大を防止し、安定した膜を均
一に成膜可能とする成膜方法を提供するものである。
This invention was made in response to the above points, and metal: 4
The object of the present invention is to provide a film forming method that completely removes a natural oxide film before forming a film, thereby preventing an increase in electrical contact resistance and making it possible to uniformly form a stable film.

[発明の構成〕 (課題を解決するための手段) この発明は処理容器内に設置された被処理基板の少なく
とも被処理面上に形成された不用な膜を除去する手段と
、この手段の後上記処理容器内で上記被処理基板の少な
くとも被処理面に膜成長用ガスにより所望する膜を成膜
する手段からなることを特徴とする。
[Structure of the Invention] (Means for Solving the Problems) The present invention provides a means for removing an unnecessary film formed on at least a surface to be processed of a substrate to be processed installed in a processing container, and a method for removing an unnecessary film formed on at least a surface to be processed of a substrate to be processed installed in a processing container, and The method is characterized by comprising means for forming a desired film on at least the surface to be processed of the substrate to be processed using a film growth gas in the processing container.

(作用効果) 処理容器内に設置された被処理基板の少なくとも被処理
面上に形成された不用な囚を除去する手段と、この手段
の後上記処理容器内で上記被処理基板の少なくとも被処
理面に膜成長用ガスにより所望する膜を成膜する手段か
らなることにより、安定した膜を被処理基板の被処理面
に成膜することが可能となる。
(Operation and Effect) A means for removing unnecessary particles formed on at least a surface to be processed of a substrate to be processed installed in a processing container; By comprising a means for forming a desired film on the surface using a film growth gas, it becomes possible to form a stable film on the processing surface of the processing target substrate.

特に、半導体ウェハに形成された自然酸化膜を完全にエ
ツチングした後に、金属薄膜を成膜すると、シリコンと
金属薄膜間に起こりうる電気的接触抵抗の増大を防止で
き、品質の向上をはかることができる。
In particular, if a metal thin film is formed after completely etching the native oxide film formed on a semiconductor wafer, it is possible to prevent an increase in electrical contact resistance that may occur between the silicon and metal thin film, thereby improving quality. can.

(実施例) 以下、本発明方法を半導体製造工程の化学的気相成長に
よる薄筒形成工程で、枚葉処理による高融点全屈の薄膜
形成に適用した実施例につき図面を参照して説明する。
(Example) Hereinafter, an example will be described with reference to the drawings in which the method of the present invention is applied to the formation of a high-melting-point, full-reflection thin film by single-wafer processing in a thin tube formation process by chemical vapor deposition in a semiconductor manufacturing process. .

第1図に示すように、冷却水等で壁面を冷却可能で機密
な円筒状Al1(アルミニウム)製反応チャンバ(ト)
上方に、被処理基板例えば被処理面であるSLと5un
2のパターン構造をもつ半導体ウェハ■を。
As shown in Figure 1, there is a cylindrical Al1 (aluminum) reaction chamber whose walls can be cooled with cooling water, etc.
Above, the substrate to be processed, for example, the surface to be processed, SL and 5un.
A semiconductor wafer ■ with a pattern structure of 2.

被処理面が下向きになる如く設置可能で後に説明する加
熱光で急加熱(ラピッドサーマル)可能な材質例えば石
英ガラス製の設置板■が設けられている。この設置板■
は、第2図に示すように半導体ウェハ■を設置するのと
は反対面に加熱光を遮断しないように透光性の電導膜(
イ)例えばSnO,又はITOが厚さ例えば数千人コー
ティングされている。又、設置板■の上方には、設置板
■の周縁に接して支持する導電性例えばAQ製で円筒状
の支持体■が、上記透光性電導膜@)と接して設けられ
ていて、この支持体0は、図示しないR−F電源に接続
している。
An installation plate (2) is provided that can be installed so that the surface to be treated faces downward and is made of a material such as quartz glass that can be rapidly heated (rapid thermal) using heating light, which will be described later. This installation board■
As shown in Figure 2, a transparent conductive film (
b) For example, SnO or ITO is coated to a thickness of, for example, several thousand. Further, above the installation plate (2), a conductive, cylindrical support body (2) made of AQ, for example, is provided in contact with the above-mentioned transparent conductive film (@), and supports the peripheral edge of the installation plate (2). This support body 0 is connected to an RF power source (not shown).

そして、上記設置板■近傍には、例えば半導体ウェハ■
の外縁を用いて設置板■に半導体ウェハ■を固定する如
く、例えばエアシリンダ等の昇降機構0を備えた支持体
■が設けられている。また。
For example, a semiconductor wafer ■ is placed near the installation plate ■.
A support body (2) equipped with a lifting mechanism (0) such as an air cylinder, for example, is provided so as to fix the semiconductor wafer (2) to the installation plate (2) using the outer edge of the support body (2). Also.

設置板■の上方には石英ガラス製の窓(8)を通して設
置板■を例えば300℃〜1000℃に加熱可能な工R
ランプ(infrared ray lamp)■が設
けられている。そして、設置板■近辺の反応チャンバ■
上壁には、例えば2ケ所の排気口(10)が設けられ、
この排気口(10)には、反応チャンバω内を所望の圧
力に減圧及び反応ガス等を排出可能な真空ポンプ(11
)例えばターボ分子ポンプ等が接続されている。
Above the installation plate ■ is a quartz glass window (8) that allows the installation plate ■ to be heated to, for example, 300°C to 1000°C.
An infrared ray lamp is provided. Then, the reaction chamber near the installation plate■
For example, two exhaust ports (10) are provided on the upper wall,
This exhaust port (10) is connected to a vacuum pump (11
) For example, a turbo molecular pump or the like is connected.

それから、反応チャンバ■の下方には、膜成長用ガスや
キャリアガスやエツチングガス等を流出する多数の微少
な流出口をもつ円環状のガス導入口(12)が2系統独
立して設けられている。これらガス導入口(12)は流
量制御機構(13)例えばマス・フロー・コントローラ
等を介してガス供給源に接続されている。また、設置板
■とガス導入口(12)の間には、ガスの流れを制御す
るための例えばステッピングモータ等の直線移動による
移動機構(14)を備えた円板状制御板(15)が設け
られている。
Then, below the reaction chamber (2), two systems of annular gas inlet ports (12) each having a large number of minute outlet ports for flowing out film growth gas, carrier gas, etching gas, etc. are provided independently. There is. These gas inlets (12) are connected to a gas supply source via a flow rate control mechanism (13) such as a mass flow controller. Further, between the installation plate (■) and the gas inlet (12), there is a disc-shaped control plate (15) equipped with a linear movement mechanism (14) such as a stepping motor for controlling the flow of gas. It is provided.

そして、反応チャンバ■の1側面に例えば昇降により開
閉可能なゲートバルブ(16)を介して、半導体ウェハ
■を反応チャンバ■内に搬入及び搬出するため、伸縮回
転自在にウェハ■を保持搬送するハンドアーム(17)
と、ウェハ■を例えば25枚程度所定の間隔を設けて積
載収納したカセット(18)をa置して昇降可能な載置
台(19)を内蔵した機密な搬送予備室(20)が配設
しである。
Then, in order to carry the semiconductor wafer (■) into and out of the reaction chamber (■) via a gate valve (16) that can be opened and closed by lifting and lowering, for example, on one side of the reaction chamber (■), a hand that holds and conveys the wafer (■) in a telescopically rotatable manner is provided. Arm (17)
A confidential transport preliminary chamber (20) is provided with a built-in mounting table (19) that can be moved up and down on which cassettes (18) containing, for example, 25 wafers (25 wafers) are placed at predetermined intervals. It is.

また、上記構成の膜形成装置は制御部(21)で動作制
御される。
Further, the operation of the film forming apparatus having the above configuration is controlled by a control section (21).

次に、上述した膜形成装置による半導体ウェハ■への成
膜方法を第3図に示すフロー図に従って説明する。
Next, a method of forming a film on a semiconductor wafer (1) using the above-mentioned film forming apparatus will be explained according to the flowchart shown in FIG.

予備室(20)の図示しない開閉口よりロボットハンド
又は人手により、例えば被処理半導体ウェハ■が25枚
程度収納されたカセット(18)を、昇降可能な載置台
(工9)上に載置する(A)、この時、ゲートバルブ(
16)は閉じた状態で、反応チャンバω内は既に、真空
ポンプ(11)の働きで所望の低圧状態となる様に減圧
されている。そして、カセット(18)をセットした後
、搬送予備室(20)の図示しない開閉口は機密となる
如く閉じられ、図示しない真空ポンプで反応チャンバα
)と同程度に減圧する(B)。
A cassette (18) containing, for example, about 25 semiconductor wafers to be processed is placed on a lifting table (work 9) through an opening/closing opening (not shown) of the preliminary chamber (20) using a robot hand or a human hand. (A) At this time, the gate valve (
16) is in a closed state, and the pressure inside the reaction chamber ω has already been reduced to a desired low pressure state by the action of the vacuum pump (11). After setting the cassette (18), the opening/closing port (not shown) of the preliminary transport chamber (20) is closed to keep it confidential, and a vacuum pump (not shown) is used to open the reaction chamber α.
) to the same extent as (B).

次に、ゲートバルブ(16)が開かれ(C)、所望の低
圧状態を保ち、載置台(19)の高さを調整することに
より、半導体ウェハ■を伸縮自在なハンドアーム(17
)で、カセット(18)から所望の1枚を取り出し、反
応チャンバω内に搬入する(D)。この時、支持体■が
昇降機構■により下降していて、ウェハ■を被処理面を
下向きに支持体■上に載置する。
Next, the gate valve (16) is opened (C), the desired low pressure state is maintained, and the height of the mounting table (19) is adjusted to hold the semiconductor wafer (■) on the extendable hand arm (17).
), a desired one is taken out from the cassette (18) and carried into the reaction chamber ω (D). At this time, the support (2) is being lowered by the lifting mechanism (2), and the wafer (2) is placed on the support (2) with the surface to be processed facing downward.

そして、昇降機構0で支持体■を上昇し、ウェハ■を設
置板■と支持体■で挟持し設置する(E)。
Then, the support body (2) is raised by the elevating mechanism 0, and the wafer (2) is placed between the installation plate (2) and the support body (2) (E).

この半導体ウェハ■の設置板■への設置が終了すると、
ハンドアーム(17)を搬送予備室(20)内に収納し
、ゲートバルブ(16)を閉じる(F)。
When the installation of this semiconductor wafer ■ on the installation board ■ is completed,
The hand arm (17) is stored in the transfer preliminary chamber (20) and the gate valve (16) is closed (F).

次に半導体ウェハ■被処理面への処理を開始する。Next, processing of the semiconductor wafer's surface to be processed is started.

まず、半導体ウェハ■に形成された自然酸化膜をエツチ
ングして除去するクリーニング処理を実行する。
First, a cleaning process is performed to etch and remove the native oxide film formed on the semiconductor wafer (2).

この処理は、反応チャンバω内を所望の低圧状態例えば
数十〜数百mTorrに保つように真空ポンプ(11)
で排気制御しながら、ガス導入口(12)を開いて、流
量調整機構(13)で流量をw4節しながら処理ガス例
えばAr又はNF、 を均一に拡散して上記ウェハ■上
に供給する。そして、設置板■に接続している導電体の
支持体■に図示しないRF主電源ら電力例えば400(
W)を印加する。すると、上記導電体の支持体■に接続
している石英ガラス製の設置板■の表面に形成された透
光性電導膜に)に電力が印加され1反応チャンバωが導
電性のため上記透光性電導rfAに)との間に放電がお
こり、半導体ウェハ■上に供給された処理ガスがプラズ
マ化され、このプラズマ化されたガスにより上記ウェハ
■上に形成された自然酸化膜を例えば10人/min程
度でエツチングする。この時、上記電力の印加により、
支持体■が高温となるため、図示しない冷却機構により
支持体■を例えば20℃程度に冷却制御しておく。
In this process, a vacuum pump (11) is used to maintain the inside of the reaction chamber ω at a desired low pressure state, for example, several tens to hundreds of mTorr.
The gas inlet (12) is opened while the exhaust is controlled by the flow rate adjustment mechanism (13), and the processing gas, such as Ar or NF, is uniformly diffused and supplied onto the wafer (2) while adjusting the flow rate to w4 with the flow rate adjustment mechanism (13). Then, an electric power of, for example, 400 (
W) is applied. Then, electric power is applied to the translucent conductive film formed on the surface of the quartz glass installation plate (■) connected to the conductor support (■), and since the reaction chamber ω is conductive, the transparent conductive film is A discharge occurs between the photoconductive rfA) and the processing gas supplied onto the semiconductor wafer (2) is turned into plasma. Etches at a rate of about 1 person/min. At this time, by applying the above power,
Since the support (2) is at a high temperature, the support (2) is controlled to be cooled to, for example, about 20° C. by a cooling mechanism (not shown).

上記のようなエツチング処理を終了後、半導体ウェハ■
の被処理面に化学的気相成長法により金属薄膜を形成す
る(H)。
After completing the etching process as described above, the semiconductor wafer is
A thin metal film is formed on the surface to be treated by chemical vapor deposition (H).

この処理は、反応チャンバω内を所望の低圧状態例えば
100〜200waTorrに保つ如く真空ポンプ(1
1)で排気制御しながら、IRランプ■から加熱光であ
る赤外光を石英ガラス製の設置体■に照射する。このこ
とにより石英ガラスおよび石英ガラスにコーティングさ
れている透光性電導膜に)は透明であるため、この設置
体(3)に設置されている半導体ウェハ■が急加熱され
る。
In this process, a vacuum pump (1
While controlling the exhaust in step 1), the quartz glass installation body (2) is irradiated with infrared light, which is heating light, from the IR lamp (2). As a result, since the quartz glass and the transparent conductive film coated on the quartz glass are transparent, the semiconductor wafer (2) placed on this installation body (3) is rapidly heated.

この時、半導体ウェハ■の被処理面の温度を工Rランプ
■で例えば40〜530℃程度となる如くウェハ■から
放射される赤外線をパイロメーターを用いて制御するか
、高感度熱電対を用いてウェハ■の温度を直接検知して
制御する。そして、ガス導入口(12)を開いて、流量
制御機構(13)で反応ガスを構成する膜成長用ガス例
えばIIF、とキャリアガス例えばH2及びArを流出
し、化学的な気相成長を行なう。この処理に際し、支持
体0のウェハ■当接面は熱伝導率の低いセラミック等で
構成すると、ウェハ■の熱分布が一様となり、処理ムラ
が防止できる。
At this time, the temperature of the surface to be processed of the semiconductor wafer (2) is controlled using a pyrometer to control the infrared rays emitted from the wafer (2) to a temperature of, for example, 40 to 530 degrees Celsius using an R lamp (2), or a high-sensitivity thermocouple (2) is used. directly detects and controls the temperature of the wafer. Then, the gas inlet (12) is opened, and a film growth gas such as IIF, which constitutes a reaction gas, and a carrier gas such as H2 and Ar, which constitute a reaction gas, flow out using a flow rate control mechanism (13) to perform chemical vapor phase growth. . During this process, if the wafer 1 contact surface of the support 0 is made of ceramic or the like having low thermal conductivity, the heat distribution of the wafer 2 will be uniform and uneven processing can be prevented.

上記のように化学的な気相成長を行なうと、半導体ウェ
ハ■の被処理面等に形成されたホール等に金属例えばW
(タングステン)の膜を選択的に堆積することができる
When chemical vapor phase growth is performed as described above, metal such as W
(Tungsten) film can be selectively deposited.

そして、所望の膜形成が終了すると、反応ガスの流出を
止められ、昇降機構に)で支持体■がウェハ■を支持し
た状態で降下し、ゲートバルブ(16)が開かれ(1)
、伸縮回転自在なハンドアーム(17)により半導体ウ
ェハ■を反応チャンバ■より搬出する(J)とともにゲ
ートバルブ(16)を閉じて(K)処理が完了する。こ
の処理が完了後、カセット(18)内に未処理ウェハが
無いか確認しくL)、未処理ウェハがある場合再び上記
のエツチング処理および化学的気相成長処理を実行し、
未処理ウェハがない場合、終了する。
When the desired film formation is completed, the outflow of the reaction gas is stopped, the support body (2) is lowered with the wafer (2) supported by the lifting mechanism (2), and the gate valve (16) is opened (1).
Then, the semiconductor wafer (1) is carried out from the reaction chamber (2) by the extendable and rotatable hand arm (17) (J), and the gate valve (16) is closed (K) to complete the process. After this process is completed, check whether there are any unprocessed wafers in the cassette (18), and if there are any unprocessed wafers, perform the above etching process and chemical vapor deposition process again,
If there are no unprocessed wafers, the process ends.

上記のように、被処理基板例えば半導体ウェハを設置す
る設置板を石英ガラスに透光性電導膜を形成したものを
使用することにより、洗浄のためのエツチング処理時に
、上記透光性電導膜に電力を印加し、処理ガスを均一に
プラズマ化してエツチング処理を安定して行なうことが
可能となり、又、成膜時に、上記設置板側から加熱光で
ある赤外光を照射しなからCVD処理を行なえるので均
一で安定した成膜が可能となる。
As mentioned above, by using a quartz glass plate with a transparent conductive film formed thereon as a mounting plate on which a substrate to be processed, such as a semiconductor wafer, is placed, the transparent conductive film can be coated during the etching process for cleaning. By applying electric power, it is possible to uniformly transform the processing gas into plasma and perform etching processing stably. Also, during film formation, CVD processing can be performed without irradiating infrared light, which is heating light, from the installation plate side. This makes it possible to form a uniform and stable film.

この発明は上記実施例に限定されるものではなく、例え
ば反応チャンバ内で半導体ウェハを設置する石英ガラス
製の設置板に透光性電膜を形成する面は、半導体ウェハ
を設置する面に形成しても良く、又、両面に形成しても
良く、何れにおいても上記実施例と同様な効果が得られ
る。又、設置板も石英ガラス製に透光性電導膜を形成し
たものに限定するものでなく、設置板が導電性で透光性
のものなら何れでも良い。さらにエツチング処理するも
のは自然酸化膜でなくとも良く、後に行なうCVD処理
の前工程としてプラズマエツチングを実行しても良い、
さらに又、設置板■とガス導入口(12)の間に設けた
円板状制御板(15)の位置を移動機構(14)で調整
することで、設置された半導体ウェハ■の被処理面によ
り均一に反応ガスが接する如く、反応ガスの流れを制御
することができる。
The present invention is not limited to the embodiments described above, and for example, the surface on which the light-transmitting electrical film is formed on the quartz glass installation plate on which the semiconductor wafer is placed in the reaction chamber is formed on the surface on which the semiconductor wafer is placed. Alternatively, it may be formed on both sides, and in either case, the same effects as in the above embodiment can be obtained. Furthermore, the installation plate is not limited to one made of quartz glass with a transparent conductive film formed thereon, and any installation plate may be used as long as it is conductive and transparent. Furthermore, the material to be etched does not have to be a natural oxide film, and plasma etching may be performed as a pre-process of the CVD treatment to be performed later.
Furthermore, by adjusting the position of the disc-shaped control plate (15) provided between the installation plate ■ and the gas inlet (12) using the moving mechanism (14), the processing surface of the installed semiconductor wafer ■ The flow of the reaction gas can be controlled so that the reaction gas comes in contact with the reactor gas uniformly.

又、不用な膜の除去は、プラズマエツチングで行なわな
くとも、不用な膜が除去できる手段なら何れでも良く、
さらに、CVD処理による成膜においても、どのような
処理でも良く例えばプラズマ(−CV D処理で行なっ
ても良いことは言うまでもない。
Further, unnecessary films need not be removed by plasma etching, but any means that can remove unnecessary films may be used.
Furthermore, it goes without saying that any kind of treatment may be used for film formation by CVD treatment, such as plasma (-CVD treatment).

さらに又、被処理基板例えば半導体ウェハ■の被処理面
に、化学的気相成長法により薄膜例えばW(タングステ
ン)膜を成膜する際、密閉容器を構成する反応チャンバ
■の壁表面に極ねずかではあるがW膜が付着し堆積して
しまうことがある。
Furthermore, when forming a thin film such as a W (tungsten) film by chemical vapor deposition on the processing surface of a substrate to be processed, such as a semiconductor wafer Although it is a small amount, the W film may adhere and accumulate.

この反応チャンバ■の壁表面に付着堆積したW膜をプラ
ズマエツチングによりセルフクリーニングすることも可
能である。次に、このセルフクリーニング処理について
説明する。
It is also possible to self-clean the W film deposited on the wall surface of the reaction chamber (2) by plasma etching. Next, this self-cleaning process will be explained.

設置板■に被処理基板例えば半導体ウェハ■を設置しな
い状態で、反応チャンバω内を所望の低圧状態例えば数
十〜数百mmT。rrに保つように真空ポンプ(11)
で排気制御を行なう、この排気状態でガス導入口(12
)を開いて、流量調節器(13)で流量を調節しながら
処理ガス例えばNF3 を反応チャンバω内に供給する
。そして、設置板■に接続している導電体の支持体■に
図示しないRF主電源ら電力例えば400(W)を印加
する。このことにより、上記導電体の支持体0に接続し
ている石英ガラス製の設置板■の表面に形成された透光
性電導膜(2)に電力が印加され、反応チャンバ■が導
電性のため、上記透光性電導膜(イ)との間に放電がお
こり、反応チャンバω内に供給された処理ガスであるN
F、がプラズマ化され、このプラズマ化されたガスによ
り、反応チャンバ■の壁表面に付着し堆積したW[をプ
ラズマエツチングする。
With no substrate to be processed, such as a semiconductor wafer (2), placed on the installation plate (2), the interior of the reaction chamber (ω) is maintained at a desired low pressure, for example, several tens to hundreds of mmT. Vacuum pump (11) to keep it at rr
Exhaust control is performed at the gas inlet (12) in this exhaust state.
) is opened and a processing gas, for example, NF3, is supplied into the reaction chamber ω while adjusting the flow rate with a flow rate regulator (13). Then, a power of 400 (W), for example, is applied from an RF main power source (not shown) to the conductor support body (2) connected to the installation plate (2). As a result, electric power is applied to the transparent conductive film (2) formed on the surface of the quartz glass installation plate (2) connected to the support 0 of the conductor, and the reaction chamber (2) becomes conductive. Therefore, a discharge occurs between the translucent conductive film (A) and the N, which is the processing gas supplied into the reaction chamber ω.
F is turned into plasma, and the plasma-formed gas plasma-etches W [attached and deposited on the wall surface of the reaction chamber (2).

上記のようなプラズマエツチングによる反応チャンバの
セルフクリーニング処理は、反応チャンバにW膜がある
程度堆積した毎に行なう。例えば予め所定数の被処理基
板のCVD処理を実行した毎に行なうように設定してお
く。又、CVD処理のガスの種類により反応チャンバの
壁表面に堆積する量が異なるので適宜セルフクリーニン
グのタイミングを選択的に決定して良いことは言うまで
もない。
The self-cleaning process of the reaction chamber by plasma etching as described above is performed every time a certain amount of W film is deposited in the reaction chamber. For example, it is set in advance to be performed every time a predetermined number of substrates are subjected to CVD processing. Furthermore, since the amount deposited on the wall surface of the reaction chamber varies depending on the type of gas used in the CVD process, it goes without saying that the self-cleaning timing may be selectively determined as appropriate.

上記のようにセルフクリーニングを所定毎に実行するこ
とにより、反応チャンバ内をいつも清浄な状態とするこ
とができ、反応チャンバに付着堆積したW膜等が塵とな
り、CVD処理に悪影響を与えることを防止できる。
By performing self-cleaning at predetermined intervals as described above, the interior of the reaction chamber can be kept clean at all times, and the W film etc. deposited in the reaction chamber can be prevented from turning into dust and having an adverse effect on the CVD process. It can be prevented.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明方法の一実施例を説明するための膜形成
装置の構成図、第2図は第1図装置の被処理基板を設置
する設置板の拡大図、第3図は第1図の装置による膜形
成を説明するためのフロー図である。 1・・・反応チャンバ   2・・・半導体ウェハ3・
・・設置板      4・・・透光性電導膜5・・・
支持体      9・・・IRクランプ許出願人 東京エレクトロン株式会社 第1図 第2図
FIG. 1 is a block diagram of a film forming apparatus for explaining an embodiment of the method of the present invention, FIG. 2 is an enlarged view of an installation plate on which a substrate to be processed is placed in the apparatus of FIG. 1, and FIG. FIG. 3 is a flow diagram for explaining film formation by the apparatus shown in the figure. 1... Reaction chamber 2... Semiconductor wafer 3.
... Installation board 4 ... Transparent conductive film 5 ...
Support 9...IR clamp applicant Tokyo Electron Ltd. Figure 1 Figure 2

Claims (1)

【特許請求の範囲】[Claims]  処理容器内に設置された被処理基板の少なくとも被処
理面上に形成された不用な膜を除去する手段と、この手
段の後上記処理容器内で上記被処理基板の少なくとも被
処理面に膜成長用ガスにより所望する膜を成膜する手段
からなることを特徴とする成膜方法。
a means for removing an unnecessary film formed on at least the to-be-processed surface of the to-be-processed substrate placed in the processing container; and a method for growing a film on at least the to-be-processed surface of the to-be-processed substrate in the processing container after this means. 1. A film forming method comprising means for forming a desired film using a gas.
JP7299288A 1988-03-25 1988-03-25 Film forming equipment Expired - Fee Related JP2509820B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7299288A JP2509820B2 (en) 1988-03-25 1988-03-25 Film forming equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7299288A JP2509820B2 (en) 1988-03-25 1988-03-25 Film forming equipment

Publications (2)

Publication Number Publication Date
JPH01244615A true JPH01244615A (en) 1989-09-29
JP2509820B2 JP2509820B2 (en) 1996-06-26

Family

ID=13505410

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7299288A Expired - Fee Related JP2509820B2 (en) 1988-03-25 1988-03-25 Film forming equipment

Country Status (1)

Country Link
JP (1) JP2509820B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03138931A (en) * 1989-10-24 1991-06-13 Tokyo Electron Ltd Film forming method
JPH10209079A (en) * 1997-01-23 1998-08-07 Nec Corp Manufacture of semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03138931A (en) * 1989-10-24 1991-06-13 Tokyo Electron Ltd Film forming method
JPH10209079A (en) * 1997-01-23 1998-08-07 Nec Corp Manufacture of semiconductor device
US6407003B2 (en) * 1997-01-23 2002-06-18 Nec Corporation Fabrication process of semiconductor device with titanium film

Also Published As

Publication number Publication date
JP2509820B2 (en) 1996-06-26

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