JPS5910225A - Formation of metal cilicide - Google Patents
Formation of metal cilicideInfo
- Publication number
- JPS5910225A JPS5910225A JP12011282A JP12011282A JPS5910225A JP S5910225 A JPS5910225 A JP S5910225A JP 12011282 A JP12011282 A JP 12011282A JP 12011282 A JP12011282 A JP 12011282A JP S5910225 A JPS5910225 A JP S5910225A
- Authority
- JP
- Japan
- Prior art keywords
- silicon
- metal
- atoms
- sputtering
- metal silicide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
Abstract
Description
【発明の詳細な説明】 Qλ)発明の技術分野 本発明は金jにシリサイドの新規な形成方法に関する。[Detailed description of the invention] Qλ) Technical field of invention The present invention relates to a novel method for forming silicide on gold.
(b) 従来技術と問題点
通紙、モリブデン(+′VAO)、タングステン(W)
又は白金(1’t )などの高一点金属のシリサイド(
シリコン化合物)が、LSIのような高曽度化された半
2!・J坏豪偵回路(IC)の導t(i配線層として汎
く用いられるようになって色た。それはドープ多結晶シ
リコン(lこ比べて抵抗率が1桁程度眩いため高速動作
が可能であり、且つ多結晶シリコンと同様に多層配線構
造に適しているからである。(b) Conventional technology and problems Paper passing, molybdenum (+'VAO), tungsten (W)
Or silicide of high point metal such as platinum (1't) (
Silicon compound) is a high-performance semi-2 like LSI!・It became widely used as a conductor (i) wiring layer for IC circuits (IC).It is made of doped polycrystalline silicon (which has a resistivity about an order of magnitude brighter than that of doped polycrystalline silicon), which enables high-speed operation. This is because, like polycrystalline silicon, it is suitable for multilayer wiring structures.
ところでこのような金属シリサイドをスパッタリング(
以下スパッタと称す)法で形成する場合、従来は金属シ
リサイド材料をターゲットにするか、又は金属とシリコ
ンとの2つのターゲットより同時にスパッタするコラス
パッタ法によって被着させている。そのうち、金属シリ
サイド材料をターゲットにする方法はヌバツタ装置が簡
単で、操作が容易である半面、金属シリサイドに高純度
なものが少なくて、IC自体の品質に患い影響がある。By the way, sputtering (
When forming by a method (hereinafter referred to as sputtering), conventionally, a metal silicide material is used as a target, or a collus sputtering method is used in which sputtering is performed simultaneously from two targets of metal and silicon. Among them, the Nubatsuta device is simple and easy to operate when targeting metal silicide materials, but there are few high-purity metal silicides, which affects the quality of the IC itself.
また2つのターゲットを用いるコラスパッタ法はスパッ
タ操作が複雑であシ、コントロールが難しい欠点がある
。Further, the collus sputtering method using two targets has the drawback that the sputtering operation is complicated and control is difficult.
更に重大な欠点は、連続自動処理工程によってIC上面
にスパッタ法で金属シリサイドを被着すると、装置内の
治具に付着した金属シリサイドが脆弱ではがれやすいた
め、金属シリサイド粉体がIC面上に付着して工C素子
を汚す問題である。An even more serious drawback is that when metal silicide is deposited on the top surface of an IC by sputtering in a continuous automatic processing process, the metal silicide attached to the jig in the equipment is fragile and easily peels off, so the metal silicide powder may not be deposited on the IC surface. The problem is that it adheres and contaminates the C element.
ICの高品質化のためにも、スパッタ法を含むウェハー
処理工程は自動化処理が望まれており、その観点から金
属シリサイド粉体fよる汚染に甚だ厄介な問題である。In order to improve the quality of ICs, automation of wafer processing steps including sputtering is desired, and from this point of view, contamination by metal silicide powder f is an extremely troublesome problem.
(0) 発明の目的
本発明は上記l〜だ問題点を除去して、工Cを清浄に保
持し、高純度の金属シリサイドを形成するスパック法を
Lv某するものである。(0) Purpose of the Invention The present invention eliminates the above-mentioned problems, maintains the process C clean, and improves the level of the spuck method for forming high-purity metal silicide.
C」) 発明の椛成
その目的は、単結晶シリコン又は多結晶シリコン面を有
する基板を高温度に加熱し、その上mlに金属をスパッ
クして被着させ、該金属のシリサイド1良が形成される
形成方法によって達成される。The purpose of the invention is to heat a substrate having a single crystal silicon or polycrystalline silicon surface to a high temperature, sputter and deposit a metal onto the substrate, and form a silicide of the metal. This is achieved by a method of forming
(e) 発明の実施例 以下、図面を4照して一実施例により詳細に説明する。(e) Examples of the invention Hereinafter, one embodiment will be described in detail with reference to the drawings.
第1図はスパック装置の、既要断面図を示しており、真
空容器1中の臥零4ステージ2上にノリ−1ンウエハー
3が載置され、対向電極4百にはト、40(反5が?!
−ゲツ1−とじて取り付けられている今、真壁排気1−
16より真空吸引し、クンタル線ヒータ7によりシリコ
ンウェハー3を700 ’OvC加9)卜シた後、ガス
導入1’Tl 3よりアルゴン(Ar、)ガスを導入し
て、その減圧度を10−”Torr程度とし、対向電極
4を陰極として、約gKVの真流電圧を印加する。そう
すると、ArイオンがMO板5に衝突してMO原子が叩
き出されて、向き合った試料ステージ2上のシリコンウ
ェハー8面に被着する。シリコンウェハー3面は700
Gに加熱されているため、活性化したンリコン原子と
MO原子とが反応し、モリブデンシリサイド(MoSi
2)が作成される。膜厚1000A程度のMOを被着す
れば、約200OAの膜厚をもったMo51g膜が形成
され、X線回折法によってその組成が1ylosii1
であることが確認された。FIG. 1 shows an existing cross-sectional view of the spuck apparatus, in which a Nori-1 wafer 3 is placed on a stage 2 in a vacuum vessel 1, and a counter electrode 400 has a 5?!
-Getsu 1- Now that it is closed and installed, Makabe exhaust 1-
After applying vacuum suction from 16 and applying 700 OvC to the silicon wafer 3 using the Kuntal wire heater 7, argon (Ar) gas was introduced from gas introduction 1'Tl 3, and the degree of vacuum was reduced to 10- Torr, and applying a true current voltage of about gKV using the counter electrode 4 as a cathode. Then, Ar ions collide with the MO plate 5 and MO atoms are knocked out, and the silicon on the sample stage 2 facing the Deposited on 8 wafers. 700 wafers on 3 silicon wafers.
Because it is heated to
2) is created. If MO with a thickness of about 1000A is deposited, a Mo51g film with a thickness of about 200OA is formed, and its composition is determined by X-ray diffraction to be 1ylosii1.
It was confirmed that
ところで、Moを被着させるシリコンウェハ−3面は予
め極めて清浄な面にすることが必要であり、第1図には
図示していないが、例えば第2図に示すように連続処理
工程において、エツチング室10内で高周波スパッタエ
ツチングにてシリコンウェハー8面をエツチングし、そ
のまに真空中でロードロック室11を径でスパッタ室1
2に送入して、大気中に取シ出すことなく前処理し、連
続してスパックする方法が好ましい。尚、第2図には真
空排気[1を図示していないが、各室とも真空に排気さ
れるcまた13は各室間を接続するゲートパルプを示し
ている。By the way, it is necessary to make the third surface of the silicon wafer to which Mo is to be deposited an extremely clean surface in advance, and although it is not shown in FIG. 1, for example, as shown in FIG. 2, in the continuous processing step, Eight sides of the silicon wafer are etched by high frequency sputter etching in the etching chamber 10, and at the same time the load lock chamber 11 is opened in a vacuum with the diameter of the sputter chamber 1.
It is preferable to send the raw material into a tank 2, pre-process it without taking it out into the atmosphere, and then continuously sppack it. Although the evacuation [1] is not shown in FIG. 2, each chamber is evacuated to a vacuum state c or 13 indicates a gate pulp that connects each chamber.
上記例はMoSi。1膜を形成する実施例であるが、そ
の他の金属シリサイド膜も同様にして形成することがで
き、金属の種類とシリコン基板の加熱温度及び生成され
るシリサイド組成を次表に示す。The above example is MoSi. Although this is an example in which one film is formed, other metal silicide films can be formed in the same manner, and the type of metal, the heating temperature of the silicon substrate, and the composition of the silicide produced are shown in the following table.
本発明によれば、スパッタ法で被着する基板面が単結晶
シリコン 多結晶シリコン又は非晶質シリコンであるこ
とが必要で、もし他の材質例えば酸化シリコン族」−に
形成する場合は、初めに非晶質または多結晶シリコン)
換を被着し、その上に金属をスパッタすればよく、例え
ば第2図に示す連続処理工程において、エツチング室1
00代シに非+11+(スパッタ膜では多結晶になりに
くいため)貿または多結晶シリコン膜のスパッタ室を配
置すればよい。According to the present invention, it is necessary that the substrate surface to be deposited by sputtering be made of single crystal silicon, polycrystalline silicon or amorphous silicon; if it is to be formed of other materials such as silicon oxide group, amorphous or polycrystalline silicon)
For example, in the continuous process shown in FIG.
A sputtering chamber for a non-+11+ (because a sputtered film is unlikely to become polycrystalline) or a polycrystalline silicon film may be placed in the 00 range.
このようにして金属シリサイド膜を形成すれば、スパッ
タ装置内において、基板8以外の治具部分例えば試料ス
テージの露出面などには金属が付着し、それは治具とは
反応しないから粘性のある金属としてそのま一付着し、
はがれをおこすことはない。したがって、連続処理して
も工C累子面を清浄に保持することができる。If a metal silicide film is formed in this way, metal will adhere to parts of the jig other than the substrate 8, such as the exposed surface of the sample stage, in the sputtering device, and since it will not react with the jig, viscous metal will As it is, it adheres as it is,
It will not peel off. Therefore, the C-cut surface can be kept clean even during continuous processing.
(f) 発明の効果
以上の説明から明らかなように、本発明によれば、連続
自動処理工程に適用してIC素子を汚染させることがな
く、且つ高純度な金属シリサイドが形成されて、また処
理操作も容易であるため、ICの高品質化に極めて役立
つものである。(f) Effects of the Invention As is clear from the above explanation, the present invention can be applied to a continuous automatic processing process without contaminating IC elements, and can form highly pure metal silicide. Since the processing operation is easy, it is extremely useful for improving the quality of ICs.
第1図は本発明を適用するスパッタ装置の概要断面図、
第2図は本発明による前処理を含む連続処理工程図であ
る。図中、8はシリコン基板、2は試料ステージ、4は
対向電極、5はMoターゲット、7はタンタル線ヒータ
、10はエツチング室。
11はロードロック室、12はスパッタ室を示している
。FIG. 1 is a schematic sectional view of a sputtering apparatus to which the present invention is applied;
FIG. 2 is a continuous processing process diagram including pretreatment according to the present invention. In the figure, 8 is a silicon substrate, 2 is a sample stage, 4 is a counter electrode, 5 is a Mo target, 7 is a tantalum wire heater, and 10 is an etching chamber. Reference numeral 11 indicates a load lock chamber, and 12 indicates a sputtering chamber.
Claims (1)
スパッタリングによって被着させ、該金属のシリサイド
膜を形成する工程が含まれてなることを特徴とする金属
シリサイドの形成方法。1. A method for forming metal silicide, comprising the steps of depositing a metal onto the silicon substrate by sputtering while heating the silicon substrate to form a silicide film of the metal.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12011282A JPS5910225A (en) | 1982-07-09 | 1982-07-09 | Formation of metal cilicide |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12011282A JPS5910225A (en) | 1982-07-09 | 1982-07-09 | Formation of metal cilicide |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5910225A true JPS5910225A (en) | 1984-01-19 |
Family
ID=14778232
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP12011282A Pending JPS5910225A (en) | 1982-07-09 | 1982-07-09 | Formation of metal cilicide |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5910225A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4945200A (en) * | 1989-03-17 | 1990-07-31 | Fort Wayne Wire Die, Inc. | Electrical discharge machine apparatus moving wire electrode guide assembly |
-
1982
- 1982-07-09 JP JP12011282A patent/JPS5910225A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4945200A (en) * | 1989-03-17 | 1990-07-31 | Fort Wayne Wire Die, Inc. | Electrical discharge machine apparatus moving wire electrode guide assembly |
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