JP2779173B2 - Grade controllable membership function circuit, grade controllable membership function generation circuit, fuzzy computer and fuzzy controller using them - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION In a membership function circuit that outputs a signal representing a function value of a predetermined membership function corresponding to an input variable signal, control is performed in accordance with a control signal to which a grade of the membership function is given. Is done. Similarly, in a membership function generating circuit for generating and outputting a signal representing a membership function by signal levels distributed on a plurality of signal lines, the grade of the generated membership function is controlled by a control signal. Such a grade controllable membership function circuit,
By using the grade controllable membership function generating circuit, weighting can be performed for each implication or rule (control rule) in a fuzzy computer or fuzzy controller. Also, a fuzzy controller based on algebraic product rules is realized using a grade controllable membership function circuit.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a grade controllable membership function circuit, a grade controllable membership function generation circuit, a fuzzy computer and a fuzzy controller using the same.

The great human brain understands the concept of stored programs, Boolean algebra, and binary
Digital computers were created by harmonizing the hardware. The continuous operation enabled the development of deep logic and deep processing of data. Digital computers are reliable due to their stable operation, and digital computer systems are becoming ever larger. A digital computer can be any program, as long as the program does not contain information at the human mental level, in this respect it is even called a general purpose machine. The realization of digital computer systems is transforming human life and society.

Another great human brain considered what humans think and how they communicate with each other and created a very important concept, "fuzziness." L.
A. Zadeh proposed the concept of fuzzy sets in 1965. Since then, fuzzy reasoning has been discussed in a number of papers, but there have been few reports of its application, and only in practice with the help of binary digital computers.

In fuzzy research, it is emphasized that human knowledge is based on accumulated experience to be summed up with linguistic information, like expert know-how.
This linguistic information generally has ambiguity, vagueness, uncertainty, incompleteness or inaccuracy, and is characterized by a membership function. The size of the membership is represented by a numerical value in the range between 0.0 and 1.0 and varies within this range.

If the linguistic information is handled by a digital computer, the magnitude (value) of the membership is represented by a binary code. The value represented by the binary code is stored, transferred, and operated on the binary electronic circuit repeatedly and again according to the stored program. Therefore, there is a problem that it takes a long time to process the fuzzy information by the digital system. In addition, binary coded values require an incredibly large number of devices for storage and operations. Although a digital computer is a general-purpose machine as described above, it is not always optimal for processing fuzzy information in real time. There is a need for other types of machines that can process fuzzy information efficiently and at high speed.

SUMMARY OF THE INVENTION The present invention relates to a hardware system suitable for processing fuzzy information, particularly a fuzzy computer, a grade controllable membership function circuit and a grade controllable membership useful in a system called fuzzy control. It is an object to provide a function generation circuit.

Another object of the present invention is to provide a fuzzy computer and a fuzzy controller constructed using the above grade controllable membership function circuit, grade controllable membership function generation circuit.

The grade controllable membership function circuit according to the first invention is a member for outputting a signal of a level representing a predetermined membership function in which a peak level portion of an output signal is determined by a label signal in accordance with an input signal. It is characterized by comprising a ship function circuit and a grade control circuit for controlling the level of the output signal of the membership function circuit in accordance with a grade control signal input thereto.

According to the first invention, the grade of the membership function output from the membership function circuit can be changed according to the grade control signal.

A grade controllable membership function generating circuit according to a second invention is a signal distribution generating circuit for generating a signal level distribution representing a membership function by signal levels distributed on a plurality of signal lines, and a label signal provided And a switch array for converting the signal level distribution into predetermined positions on a plurality of output signal lines in accordance with the signal distribution generating circuit. The signal distribution generating circuit divides the level of a given grade control signal to generate a plurality of levels. And a circuit portion for generating the signal

According to the second aspect, the grade of the membership function generated from the membership function generation circuit can be changed by the grade control signal.

According to the first and second inventions, it is possible to adjust the grade of the membership function according to the manual adjustment or the learning result. Therefore, the membership function is changed according to the importance of the implication rule. Weighting can be given.

A sweep-type fuzzy controller according to a third aspect of the present invention provides a signal representing a membership function value according to one or more given inputs, or a signal representing a predetermined operation result of a signal representing a plurality of membership function values. , A sweep signal generating circuit for generating a sweep signal of a fixed period, and a signal representing a predetermined membership function in synchronization with the input sweep signal, and the output signal of the first circuit is grade controlled. And a fuzzy inference based on algebraic product rules, including a grade controllable membership function circuit for controlling the level of a signal representing a membership function output as a signal in accordance with the grade control signal. I do.

According to the third invention, a fuzzy controller that performs inference based on algebraic product rules can be realized with a very simple configuration.

A parallel type fuzzy controller according to a fourth aspect of the present invention provides a signal representing a membership function value corresponding to one or more given inputs, or a signal representing a predetermined operation result of a signal representing a plurality of membership function values. And a signal level distributed on a plurality of signal lines representing a membership function, and outputs the same. The output signal of the first-stage circuit is provided as a grade control signal, And a grade controllable membership function generating circuit in which the level of the signal level distribution to be output is controlled, and performs fuzzy inference based on algebraic product rules.

According to the fourth aspect, a fuzzy controller that performs an inference operation according to an algebraic product rule can be realized with a simple configuration.

A parallel type fuzzy controller according to a fifth aspect of the present invention outputs a signal representing a membership function according to an applied input signal and a level of a signal representing a membership function output according to an applied grade control signal. At least one grade controllable membership function circuit, which generates and outputs signal levels distributed on a plurality of signal lines representing the membership function, and the grade controllable membership function. And a grade controllable membership function generating circuit for controlling the level of a signal level distribution to be output in accordance with the grade control signal, and the above grade controllable membership function circuit. Yo Characterized by comprising a fuzzy inference synthesis circuit which executes a predetermined fuzzy inference operations on the output signal of the grade controllable membership function generator circuit.

According to the fifth invention, fuzzy inference can be performed while controlling the grades of the membership functions of the antecedent part and the consequent part.
A fuzzy controller useful in the system is realized.

The parallel type fuzzy computer according to the sixth invention generates and outputs signal levels distributed on a plurality of signal lines each representing a different membership function, and receives the same grade control signal. At least three grade controllable membership function generating circuits for controlling the level of a signal level distribution output according to the grade control signal, and the output signals of the at least three grade controllable membership function generating circuits A fuzzy inference engine for executing a predetermined fuzzy inference operation is provided.

According to the sixth invention, it is possible to change or adjust the grade of the membership function in the antecedent part and the consequent part, and a fuzzy computer useful especially in a fuzzy system having a learning function is provided. Realize.

A sweep type fuzzy controller according to a seventh aspect of the present invention is obtained by changing the parallel type fuzzy controller according to the fifth aspect of the present invention to a sweep type fuzzy controller, and represents a membership function corresponding to a given input signal. At least one first grade controllable membership function circuit that outputs a signal and controls the level of a signal representing a membership function that is output according to a given grade control signal;
A sweep signal generating circuit for generating a sweep signal having a constant period, outputting a signal representing a membership function on a time axis in synchronization with the sweep signal, and having the same grade as that of the first grade controllable membership function circuit A second grade controllable membership function circuit to which a control signal is applied and the level of an output signal is controlled in accordance with the grade control signal, and the first and second grade controllable membership function circuits A fuzzy inference synthesizing circuit for performing a predetermined fuzzy inference operation on the output signal of

According to the seventh invention, a sweep type fuzzy
The grade of the membership function of the antecedent part and the consequent part can be changed in the controller, which is particularly suitable for a fuzzy system having a learning function.

A sweep type fuzzy computer according to an eighth aspect of the present invention is a sweep type fuzzy computer in which the larel type fuzzy computer according to the sixth aspect of the invention is changed to a sweep type. , A signal representing different membership functions on the time axis is output in synchronization with the sweep signal, and the same grade control signal is given, and the level of the output signal is controlled according to the grade control signal. Grade controllable membership function circuit and the above grade controllable
A fuzzy inference synthesizing circuit for executing a predetermined fuzzy inference operation on an output signal of the membership function circuit is provided.

According to the eighth invention, the grade of the membership function of the antecedent part and the consequent part can be changed, and a fuzzy computer suitable for constructing a fuzzy system having a learning function is realized.

Description of Embodiment (1) Fuzzy Reasoning and Concepts of Fuzzy Computer and Fuzzy Controller The simplest rule of thumb is that if x is A, then y is B. (If x is A, then y is B). Here, "If x
"If A" is called an antecedent, and "y is B" is called a consequent. A and B
If it is ambiguous linguistic information such as "tall", "elderly person", "positive small value", etc., these can be characterized by the membership function as described above. That is, A and B are fuzzy sets (in the description of the specific circuit to be fired, A, B, etc. indicate voltage signals representing the membership function).

 The above proposition is simply expressed as x = A → y = B.

Humans often make inferences that include fuzzy expressions in the antecedent and consequent parts. This type of reasoning cannot be performed satisfactorily using classical Boolean logic.

 Consider the following form of reasoning:

This form of inference, that is, inferring conclusions from a given premises when implications exist, is called "generalized modus ponens.
modus ponens).

There may be a number of implication rules:

Many implications are else (or otherwise) connected.

"Fuzzy relation from A to B
A to B) ", and this is represented as R _AB (hereinafter simply abbreviated as R).

Generally _{A = {a 1, a 2} , ..., a i, ..., a m} B = {b 1, b 2, ..., b j, ..., b n} when the fuzzy relation from A to B R is Is represented by

The calculation representing the fuzzy relation will be described later. A,
When B is considered as a membership function, the above equation corresponds to a case where the membership function is sampled and described as a vector.

One implication rule (x = A → y =
B), given a premise (x = A '), the "compositional rule of inference" for inferring a conclusion (y = B') from now
It is expressed as follows using the fuzzy function R.

Various operations for expressing a fuzzy relation have been proposed.
See Masaharu Mizumoto and Hans-Jurgen Zimmerm for details
ann, “Comparison of Fuzzy Reasoning Methods,” Fuzzy
Sets and Systems Vol.8, No.3, pp.253-283, (1982)
See

Typical fuzzy relations already proposed include the following.

r _ij = a _i ∧b _j MIN calculation rule r _ij = (a _i ∧b _j ) ∨ (1-a _i ) MAX rule r _ij = 1∧ (1-a _i ∧b _j ) Arithmetic rule The above MIN operation Since the rules are best known and their effectiveness has been proven in industrial applications, the specific circuit example described below uses the MIN operation rule. However, it goes without saying that many other arithmetic rules are also applicable.

Various operations have been proposed for the operation of * in the above equation (that is, the operation with). For example, MIN / MAX operation,
Some use an algebraic product / MAX operation. In the specific circuit example described below, the most commonly used MIN / MAX
The operation is used as the operation of *. That is, the MAX operation is adopted as the operation and the MIN operation is adopted as the operation.

Therefore, the conclusion b _j ′ according to the inference synthesis rule is expressed as follows when the MIN / MAX operation is used as the * operation and the MIN operation rule is used as the fuzzy function.

From the above equation, it can be understood that the fuzzy inference engine or the fuzzy inference synthesizing circuit is mainly configured by using the MIN circuit and the MAX circuit.

Before describing the configuration of the fuzzy computer and the fuzzy controller, the membership function will be described briefly.

Generally, the membership function is often represented by a curve as shown in FIG. 1 (A). However, whether it should be represented by a curve is not essential to the membership function. A more important feature of the membership function is that it takes a continuous value from 0 to 1.

On the other hand, from the viewpoint of circuit design, FIG.
As shown by MF ₁ and MF ₂ , it is easier to handle the membership function by expressing it as a straight broken line, the membership function can be characterized by a small number of parameters, and the design is simpler. Become. Moreover, even if the membership function is represented by a broken line, the above characteristics are not lost.

Basically, a triangular membership function MF ₁ shown by a solid line in FIG. 1B and a trapezoidal membership function MF ₂ shown by a chain line can be considered. Membership function MF ₁ triangular is characterized by the value x _L and slope (called a label) of the variable x when the function mu (x) = peak value P (not necessarily the peak value = 1). The trapezoidal membership function MF ₂ is basically characterized by a variable x _L (also called a label) representing the center of its upper base and a gradient.

The variable x of the membership function μ (x) and the variable y of the function μ (y) appearing later are x, y in the above-described inference form.
Although the same signals are used, they are not particularly related to each other. This specification follows the convention of using such symbols.

Where a variable as shown in FIG. 1 (C) (x) is small functions mu (x) takes the value of 1, eventually in some variable x _L functions mu (x) is lowered at a constant gradient 0 Function
There is also a function MF ₃ (this is called a Z-function) and a function MF ₄ (this is called an S-function) that follows the inverse change of this Z-function.
In addition, various forms of membership functions are conceivable.

The membership functions described above may be embodied in various forms. One of them is as shown in FIG. 2, which is represented by electric signals (voltage or current, but only voltage signals are considered here) distributed on a plurality of (for example, about 25) signal lines l. is there. The variables of the membership function μ (x) take discrete values, and these variables are assigned to each signal line. Signal lines are numbered (1 to 25 in FIG. 2) corresponding to the assigned variables. The plurality of signal lines constitute a kind of bus. Label x _L is represented by the number of signal lines peak voltage appears.

The other is to express the variable x of the membership function μ (x) on the time axis. That is, the variable is the time t (for convenience of explanation, the time t is distinguished from the overall time T). To generate such a membership function μ (x), a sweep signal is required. As the sweep signal, those having various waveforms (for example, a signal having a sawtooth wave, a triangular wave, a sine wave, a sine wave full-wave rectified waveform, etc.) can be considered. Here, a sawtooth wave as shown in FIG. An example will be described.

In FIG. 3, the sweep signal SW of the sawtooth wave changes linearly from −E to + E at a constant period τ, and thereafter returns to −E within a short time (return period). Sweep signal
The point at which the SW crosses zero is the membership function μ (x)
For example, x = 0. Label x _L is represented by the voltage V _L of the sweep signal SW at the time corresponding to the value x _L.

FIG. 4 is a parallel type fuzzy computer which performs an operation using membership functions distributed on the bus lines shown in FIG. 2 and which is applied when one implication exists. Shows the concept of Fuzzy computers are
The three membership function generating circuits 11, 12, 13 for outputting the membership functions A, A ', B distributed on the bus lines shown in FIG. 2, respectively, and the output signals of these circuits 11, 12, 13 are Given above, the above-mentioned Modus-Ponens fuzzy inference operation (specifically, for example, (3-1), (3
-2) The fuzzy inference engine 14 performs the equation (2) and outputs the inference result B '. The membership function generating circuits 11, 12, and 13 are provided with labels LA, LA ', and LB that specify the membership functions to be output. If it is necessary to obtain a deterministic result from the fuzzy computer, i.e. a non-fuzzy output, a fuzzy inference engine 14 is followed by a defuzzifier 15.

An example of the configuration of the fuzzy inference engine 14 is shown in FIG. This performs the operation represented by the equation (3-2). Voltages representing membership functions A and A 'distributed on m signal lines are applied to a C-MIN circuit (correspondence MIN circuit) 21 where a
The MIN operation of _i ∧a _i ′ (i = 1 to m) is performed. C-MI
The N circuit 21 includes m MIW circuits having two inputs and one output. The m output voltages of the C-MIN circuit 21 are input to an E-MAX circuit (ensemble MAX circuit) 22. This E-MAX circuit 22
The output of Represents The E-MAX circuit performs an ensemble MAX operation on m input signals. The output of the E-MAX circuit 22 is used as a truncation input a
Given to 23. On the other hand, the truncation circuit 23 has n
Voltages (b _j , j = 1 to n) representing the fuzzy membership function B distributed on the signal lines are input.
The truncation circuit 23 is a circuit in which one input is all common in the C-MIN circuit. After all, finally the (3-2) operation expression is performed in truncation circuit 23, to obtain a 'conclusion B of the fuzzy inference as a set of' analog voltages distributed on n output lines b _i it can.

FIG. 5 shows the concept of a parallel type fuzzy computer effective when there are r implications. Three membership function generators 11
There are provided r sets of .about.13 and a fuzzy inference engine 14. Labels LA and LB given to the membership function generating circuit have subscripts 1 to r for each implication.
Is attached. There is no need to provide a membership function generating circuit 12 for each of these sets, and one circuit 12 can be shared by all sets. The connection (else or also) of the implications is realized by the MAX circuit 16. That is, the outputs of all the fuzzy inference engines 14 are given to the MAX circuit 16, and the MAX circuit 16 gives the final inference result B '. Of course, concatenation may be performed by an operation other than MAX.

FIG. 7 shows the concept of a sweep type fuzzy computer using a membership function expressed on the time axis shown in FIG. 3, and in the case where one implication exists. The sweep type fuzzy computer has three membership function circuits 31, 32, 33 for outputting membership functions A, A ', B expressed on the time axis, respectively. The output signal is given, the fuzzy inference synthesis circuit 34 that performs the above-mentioned Modus-Ponens fuzzy inference operation and outputs the inference result B ', and the sweep signal SW as an input signal to membership function circuits 31, 32, and 33. And a fuzzy inference synthesizing circuit 34 which supplies a predetermined timing signal synchronized with the sweep signal. It goes without saying that not only the membership functions A, A ', B but also the inference result B' are represented by voltages appearing on the time axis. In the membership function circuits 31, 32, 33, labels (label voltages) LA, LA ′,
LB is given respectively. If it is necessary to obtain a deterministic result from the fuzzy computer, ie a non-fuzzy output, a defuzzifier 36 is connected downstream of the synthesis circuit 34. From the defuzzifier 36, a constant (at least during one period τ of the sweep signal) voltage signal is obtained.

FIG. 8 illustrates the concept of a sweep-type fuzzy computer that is effective when there are r implications. A parallel type fuzzy computer effective when there are r implications shown in FIG. 5 described above and a sweep type fuzzy computer shown in FIG. 7
The configuration can be easily understood by comparing with the basic type of the fuzzy computer of the type.

Fuzzy inference engine 14 described above to aid understanding
FIG. 9 schematically shows inference according to equation (3-2) as an example of fuzzy inference executed by the fuzzy inference synthesizing circuit 34. Here, it is assumed that there are a plurality (r) of implications. Also, a triangular membership function is shown. No. (3-
Membership function A is 2), A ', element a _i of B and the like fuzzy sets, a _i', but using the b _j such are represented, 9
In the figure, the horizontal axis is represented by a function μ (x) or μ (y) (or μ (t)) with the variable x or y (or time t).

Referring to the graph at the top left of FIG. 9, the MIN operation results A1∧A ′ of the membership functions A1 and A ′ are indicated by oblique lines. The maximum value a maxl (truncating input a shown in FIG. 6) of the MIN operation result is obtained. The Figure 9 top center membership function B1 is shown, MIN operation result of this function B1 and the maximum value a maxl are hatched S _1. The hatched portion S ₁ is a inference result for one implication, it is outputted from one fuzzy inference engine 14 or fuzzy inference synthesis circuit 34.

Inferences are made for other implications in a similar manner. The inference results are represented by S ₂ and S _r .

MAX operation of these inference results (circuit 16 or circuit 37)
The result B 'is shown on the right side of FIG. Many methods have been proposed to defuzzify (defuzzify) the inference result, and one of them is the centroid method. According to this method, the center of gravity y _w is obtained by y _w = ∫μ (y) ・ dy / μ (y) dy. That is, the y coordinate (time t) that divides the area indicated by hatching into two right and left parts is obtained. Y _w obtained in this way is defuzzifier 15
Or, it is output as a fixed value from 36.

Both the fuzzy inference engine and the fuzzy inference synthesizing circuit in the above-mentioned fuzzy computer perform inference in which only one fuzzy proposition exists in the antecedent part of the implication. Inferences that involve two fuzzy propositions in the antecedent may be necessary. This is called extended fuzzy inference. The antecedent parts of the implication are connected by "and / or". Either "and" or "or" is selected.

This is represented symbolically as follows:

Extended fuzzy inference on a parallel type fuzzy computer is performed by an extended fuzzy inference engine. The concept of the extended inference engine is shown in FIG. Inputs are membership functions A, B, C, A 'and B', and a join selection c for selecting a join of "and / or". The output is a membership function C 'representing the conclusion. The membership functions A and A 'are the voltages distributed on m signal lines, B and B' are the voltages distributed on m 'signal lines, and C is the voltage distributed on n signal lines. Respectively represented by

FIG. 11 shows the configuration of the extended inference engine, which can be obtained by slightly modifying the configuration of the basic inference engine shown in FIG. A C-MIN operation is performed between the membership functions A and A '(C-MIN
The circuit 21A) performs an E-MAX operation on the m voltages representing the result (E-MAX circuit 22A). The C-MIN and E-MAX calculations are also performed on the membership functions B and B '(C-MIN circuit 21B and E-MAX circuit 22B). The combination "and (an
In this embodiment, “d)” is calculated by “MIN”
r) ”are each realized by the MAX operation. A controlled MIN-MAX circuit 24 is used so that calculation and selection of this connection can be easily performed. Controlled MIN-M
The AX circuit 24 determines the level (H or L) of the coupling selection input signal c.
Can be switched between the MIN operation function and the MAX operation function in accordance with. The results of the two E-MAX calculations are input to the controlled MIN-MAX circuit 24. And a connection selection input signal c for selecting "and" or "or"
Is provided as a control input of the controlled MIN-MAX circuit 24. Membership function C is a truncation circuit
23, and the output a of the controlled MIN-MAX circuit 24 is provided as a truncating signal. From the truncation circuit 23, the voltage distribution of the fuzzy membership function representing the conclusion C 'is obtained.

Next, the concept of the fuzzy controller will be described.

In general, a controller receives a control amount obtained from a control target and outputs an operation amount to the control target in order to perform desired control. Both the control amount and the operation amount are deterministic values. The fuzzy controller also receives a deterministic value as input, performs fuzzy inference, and outputs a deterministic value. On the other hand, as an example, if there is one fuzzy proposition in the antecedent part of the implication, in the fuzzy computer described above, the input is given by a fuzzy set or membership function A ', and the fuzzy set or member function is given. The ship function B '(definite value in some cases) is output.

Fuzzy Reasoning in Fuzzy Controller
One implication (control law) in comparison with the figure
In the case of (there is also one fuzzy proposition in the antecedent part), it is graphically represented as shown in FIG. Relative implications including the membership functions A and B, fuzzy inference result when given definite value x _A is the B 'indicated by hatching. By defuzzifying the inference result, a deterministic inference result B _w ′ is obtained.

FIG. 13 shows a case where there are two fuzzy propositions in the antecedent part of the implication (control rule).
MIN or MAX of the function values a _A and a _B when the definite values x _A and y _B are given to the two membership functions A and B in the antecedent part of the implication (corresponding to the combination and or or) And the result of the operation a _M and the membership function C
Is the fuzzy inference result (C 'indicated by oblique lines). By defuzzifying the inference result C ', a definite inference result _CW ' is obtained.

Parallel type using fuzzy membership functions distributed on bus lines, applied to fuzzy inference with multiple implications (control rules) and two fuzzy propositions in the antecedent of each implication An example of the configuration of the fuzzy controller is shown in FIG. This will be described in comparison with FIG. 5 and FIG. 11 showing the fuzzy inference engine.

 The control law is expressed as follows.

The fuzzy inference engine 14 is a fuzzy inference synthesis circuit 14a.
Has been replaced. Since the two inputs is given by definite values x _A, x _B, circuits 11 and 12 or the like for generating a membership function distributed over the bus line is not required, the membership function circuit 31a, 31b is provided in place of it Can be A fuzzy inference synthesis circuit 14a, membership function circuits 31a, 31b, etc. are provided for each control law, and the labels LA, LB of the membership function circuits 31a, 31b are provided with subscripts corresponding to the control law numbers. Have been. Hereinafter, control law 1 will be described as a representative example.

Membership function circuits 31a, 31b are input variables x _A, the membership function values corresponding to _{x B μ A1 (x A)} , and outputs mu _B1 a (y _B). The output of these circuits 31, 31b is MIN
Or it is given to the MAX circuit 24a. This MIN or MAX circuit
24a corresponds to the controlled MIN-MAX circuit 24, and may be replaced with this circuit 24. The output of the circuit 24a becomes the truncating input a _M1 . On the other hand, the output membership function generator circuit 13 for generating a membership function C1 as a voltage distribution appearing on the bus line (plurality of signal lines) is applied to the truncation circuit 23, MIN operation and a _M1 is carried out , The result of this MIN operation is C ₁ ′.

(R · -1) C ₂ equally well for pieces of control law '~
C _r ′ is obtained, and the MAX operation result (MAX circuit 16) becomes the fuzzy inference result C ′, and the result of defuzzification is obtained.
C _w ′ is obtained.

FIG. 15 shows a configuration example of a sweep type fuzzy controller in which a plurality of implications (control rules) exist (one fuzzy proposition in the antecedent part of the implication). 8 in comparison with FIG, input circuit outputs a membership function A 'because given by definite values x _A 32 (MF in the computer
C2) becomes unnecessary. X _A is given as input to the circuit 31 of the membership function A1. The output of this circuit 31 is given to the MIN circuit 38 to which the output B1 of the membership function circuit 33 is input. The circuit 33 is provided with a sweep signal as its input. The output B1 'of the MIN circuit 38 is input to the MAX circuit 37. Circuit described above is provided for a plurality of implications, output B1'～B _r of all MIN circuit 38 'is input to the MAX circuit 37. It is determined 'definite value B _w by de fuzzifier 36 from' the output B of the MAX circuit 37 and outputted.

If there are two fuzzy propositions in the antecedent part of the implication (control law), two membership function circuits 31a and 31b are provided as shown in FIG. confirmation input x _a, are x _B given. Circuit 31a
And the output of 31b is provided to the MIN or MAX circuit 24a.
The MIN circuit 38 outputs the MIN operation result C 'of the output of the circuit 24a and the membership function C output from the membership function circuit 33c to which the sweep signal is given. Since the inference result C 'is a fuzzy function, its definite value is determined by the defuzzifier.

A fuzzy controller that processes even if there are three or more propositions in the antecedent part of the implication can be constructed by extending the above concept (in both cases of the parallel type and the sweep type). Needless to say.

(2) Fuzzy processor In the case where there are a plurality (r) of implications (control rules) having two fuzzy propositions in the antecedent part,
Referring to FIG. As for the first implication, two membership functions A1, respectively B1 determined value input x _A, the function values a when given a y _B
A1 and a _B1 are obtained. The result of the MIN operation (or the MAX operation) of the shortage value is defined as a _M1 . Similarly for other implications, definite value inputs x _A and y _B are given, and the result a
_Mi (i = 2 to r) is obtained.

The membership function Ci (i = 1 to r) in the consequent part of the implication is changed to its label position Z _Li (i = 1 to
r) a single function C _si (i = 1) extending to the peak
To r). This function is called a singleton and is non-fuzzy.
As a result of the MIN operation, the result of the MIN operation with the singleton C _si (corresponding to the above-described truncation, but the MIN operation becomes unnecessary as described later) is indicated by a thick arrow C _si ′
1 to r).

In the following description, Z _Li is _replaced with Z _i (i
= 1 to r) and C _si ′ are replaced with V _zi (i = 1 to r).

The final fuzzy inference result when a plurality of implications are connected by the MAX operation is shown in the form of a bar graph on the right side of FIG. In order to defuzzify such inference results,
Here, the above-described barycenter method is used. The center of gravity C _sw ′ (this is referred to as Z _w ) is given by the following equation.

The numerator of equation (4) can be calculated by a weighted addition circuit as shown in FIG. 18, and the denominator can be calculated by a simple addition circuit as shown in FIG.

In FIG. 18, the weighted addition circuit includes an operational amplifier 41.
And the input resistances R ₁ , ..., R _r connected in parallel and the feedback resistance R _f
It is composed of a voltage V _z1 to one end of the input resistor _{R 1} ~R _r ~V _zr
Are given. Therefore, the output _Vo1 of this weighted addition circuit is given by the following equation.

Here, if R _f / R _i = Z _i (6), equation (5) represents the numerator of equation (4) (the sign is inverted).

From equation (6), it will be understood that the label of the singleton C _si representing the membership function Ci is realized by the input resistance _Ri and the feedback resistance _Rf .

As shown in Fig. 20, NL (Negative small: "negative small value") to PL (Positive large: "positive large value")
Considering membership functions or singletons represented by up to seven labels, these labels are defined by a resistor R _i (i = 1 to r) and a resistor R _f . In Fig. 20, N such as NL, NM, NS, etc. indicates Negativc, PS, P
P for M, PL, etc. is Positive, L is large, M is medium, S is s
mall represents each, ZR represents zero.

In FIG. 19, the simple addition circuit includes an operational amplification circuit 45,
An input resistor R _o of the connected value equal to the parallel feedback resistor R _o of the same value as the input resistor (not necessarily equal)
, And voltages V _{z1 to} V _zr are respectively applied to one _{ends of} the input resistors. Therefore, the output of this simple addition circuit
V _o2 is represented by the following equation.

This represents the denominator of equation (4) (the sign is inverted).

Fuzzy processor shown schematically in FIG. 17 is the same as confirmation input x _A fuzzy controller, given x _B, performs fuzzy inference based on a predetermined control law,
It has the feature of outputting a definite value (centroid Z _w ). Also,
In the fuzzy inference in this fuzzy processor,
A fuzzy function is used in the antecedent part of the implication (control law), but the consequent part also has the feature that it is expressed by a non-fuzzy quantity (singleton). Since the value of the MIN operation result a _M1 (i = 1 to r) in each control law represents the operation result of the control law, the fuzzy
Eliminates the need for truncation circuits as in computers or fuzzy controllers. The final output (centroid Z _w ) is obtained by performing weighted addition (the heavy represents the singleton label of the consequent part as described above) on the calculation results of the plurality of control rules. Of course, the simple addition described above is necessary, but can be omitted as described in the division of the equation (4). The specific configuration of a fuzzy processor having some of these features is described below. Before that, the basic arithmetic circuit MIN
The circuit and the MAX circuit will be described.

An example of an n-input, one-output MIN circuit configured using bipolar transistors is shown in FIG. Assuming that the input voltage is x ₁ , x ₂ , ..., x _n and the output voltage is z, this circuit Is performed. That is, an output voltage equal to the smallest input voltage is generated.

This MIN circuit is composed of a comparator (comparison circuit) and a compensator (compensation circuit). The comparator is composed of n PNP transistors Q ₁₁ , Q ₁₂ , Q ₁₃ ,..., Q _1n whose emitters are coupled to each other, and a current source CS ₁ of a current I ₁ for driving these transistors. . Input Voltage x ₁ ~x _n are given to the bases of the transistors Q ₁₁ to Q _1n. Since Tonrajisuta Q ₁₁ (the V _min) lowest input voltage of the to Q _1n which is applied to its base is rendered conductive, the other transistor is cut off. Therefore, the emitter / base voltage of the transistor turned on to this input voltage _Vmin is applied to the emitter.
V _EB plus voltage, ie Appears (V _EB is about 0.7V). When the two input voltages have the same value and are lower than the other input voltages, the same result is obtained because a current of I _1/2 flows through the transistor to which the two input voltages are input. The same is true if three or more input voltages are equal and lower than the other input voltages.

The compensator compensates for the voltage V _EB that appears as a MIN operation error at the output of the comparator. The compensator includes a NPN transistor Q _1, and a transistor Q ₁ current source current I ₂ for current-driving the CS ₂ Metropolitan. The MI emitter of the transistor Q ₁ is
Connected to output terminal of N circuit. From the comparator of the output voltage of the transistor Q ₂ base / emitter voltage V _BE
Is subtracted, the output voltage z becomes Will be represented. It is preferable for the current the current source CS ₁ and CS ₂ are I ₁ = I _2.

FIG. 22 shows an example of a MAX circuit. This MAX circuit also includes a comparator and a compensator. The comparators are NPN transistors Q ₂₁ , Q ₂₂ ,..., Q _2n whose bases are controlled by input voltages x ₁ , x ₂ ,..., X _n and whose emitters are coupled to each other, and a current driver for these transistors. and a current source CS ₁ Tokyo. The most high input voltage of the transistor Q ₂₁ ~Q _2n (this is V
only the transistor to be _max) is given a voltage of V _max -V _BE appears in the emitter in a conductive state. Errors of this -V _BE is, PNP transistor Q ₂ and a current source CS ₂ Metropolitan results compensated by compensator made of, to the output terminal Is obtained.

Since all the transistors in the comparators of the MIN and MAX circuits described above are interconnected at the emitter, this circuit is connected to the emitter-coupled fuzzy circuit.
Named Logic Gate (ECFL Gate).

The above-mentioned MIN circuit and MAX circuit can be considered as a cascade connection of two emitter followers driven by a current source. Therefore, they exhibit very high input impedance and very low output impedance. This fact indicates that these circuits are resistant to external noise and signal crosstalk, and that many circuits can be connected to the subsequent stage.

Further, since the above-described MIN circuit and MAX circuit are driven by the current source, no saturation occurs in each transistor. That is, the accumulation effect of the minority carrier in the base region does not occur. Therefore, these circuits exhibit a very high operation speed. According to the experiment, the response speed was less than 10nsec.

Furthermore, opening one or several of the input terminals of the circuit described above does not affect the input / output static characteristics of the entire circuit.

Furthermore, in the above circuit, the PNP and NPN transistors are replaced by p
It is also possible to replace each with a channel and n-channel MOS FET.

The above is not only the MIN and MAX circuits described above, but also
This applies to all the circuits described below.

FIG. 23 shows the overall configuration of a fuzzy processor performing the operation shown in FIG. In order to perform fuzzy inference including r implications (control rules), r rule boards 50 are provided, and each rule board 50 performs inference for each implication. In each rule board 50 (typically the first rule
Using the sign of the board), two definite value input x _A, y _B are respectively given membership function circuit 31a, to 31b, their output a _A1, a _B1 is input to the MIN (or MAX) circuit 24a, MIN
The operation result a _M1 is obtained. The above configuration is the same as the fuzzy controller shown in FIG.

The truncation circuit is unnecessary in the fuzzy processor as described above. The output of MIN circuit 24a is provided to switch array 52. The switch array 52 is for selecting the weighting described above. In this embodiment, seven singleton labels NL to PL shown in FIG. 20 are employed. Therefore, the switch array 52 has seven switches S _{NL to} S _PL , and the operation result a _M1 is given to one terminal of all these switches. The switches S _{NL to} S _PL are preferably those that can be turned on and off manually, such as dip switches. The other terminals of the switches S _{NL to} S _PL are respectively connected to the bases of the transistors Q _{31 to} Q ₃₇ whose collectors are connected to the power supply + _Vcc , and their emitters are connected to the output terminals.

In each rule board 50, one of the seven switches of the switch array 52 is selectively turned on. For example, in the first rule board, the switch S _NL is turned on, and the NL weight is selected. In the second rule board, the switch _SPM is turned on, and the PM weight is set. If you do not want a particular rule board to work, you can turn off all switches on that board.

There is a board that contains a defuzzifier (with no signal attached), and the board has 7
Has two input terminals. A corresponding output terminal of each rule board 50 is connected to each of these input terminals by a connector 53. For example, an input terminal labeled NL corresponds to a switch S _NL of every rule board 50. output terminal (emitter of the transistor Q ₃₁₎ is connected. Thereby, the wired OR connection of the output of all the rule boards is performed for each label.

7 input terminals NL on the defuzzifier board
To PL are the corresponding input resistances R _{1 to} R ₇ of the weighted addition circuit 42.
And each input resistor _Ro of the simple adder circuit 46. The weighted addition circuit 42 is the same as that shown in FIG. 18, and r = 7. Each input resistor R ₁ to R ₇
Are weighted from NL to PL. The simple addition circuit is the same as that shown in FIG.

It is connected to the transistor Q ₄₁ to Q ₄₇ acting as a seven input terminals NL~PL or current source de fuzzifier board. These transistors Q ₄₁ to Q ₄₇ constitute a multi-current mirror and a transistor Q ₄₀ which constitutes a current source 49, each of the transistors Q ₄₁ to Q ₄₇
, A current of a constant value determined by the current source 49 flows.

A de fuzzy corresponding transistors as a current source in fire board (one of Q ₃₁ to Q ₃₇₎ output of the transistor corresponding to switch belonging to the same label in the switch array 52 of each rule board 50 ( Q ₄₁ and ~Q any corresponding ones of the _47), the corresponding wired-oR of the connector 53 between the output terminal and de-fuzzy input terminal of fire board of each rule board 50
And constitute the MAX circuit respectively. For example, 22nd
And the first transistor Q ₃₁ of the rule boards subjected to (Q ₂₁₎ in FIG. 23 for clarity the relationship between FIG., (Q
_2n ) r-th rule board transistor
And Q _31, a transistor Q ₄₁ which marked the de fuzzifier board the (CS _1), a connector 53 for connecting these
And the input / output terminal of the label NL in FIG.

As described above, the MAX circuit is configured by simply connecting the output terminals of the plurality of rule boards 50 and the input terminals of the defuzzifier board by the connector 53 so that the corresponding ones are wired-OR connected. Therefore, the configuration is simplified. One or more rule boards 50
Be removed, without changing the input impedance in the de fuzzifier board since to flow a constant current by a current source (Q ₄₁ ~Q _47), the adder circuit 42 and 46
To the correct input voltage. Also, the current source only needs to be provided on the defuzzifier board.
Since there is no need to provide the rule board 50, each rule board 50 can be simplified. In the circuit of FIG. 23, the compensator shown in FIG. 22 is omitted.

The above configuration of the MAX circuit is also applicable to the MAX circuit 1637 shown in FIGS. 5, 8, 14, and 15.

Output voltage V _o2 of the simple addition circuit 46 is input via the resistor R ₁₄ to the non-inverting input terminal of the operational amplifier 47 of the voltage regulator circuit 48. With a constant reference voltage V _o through the resistor R ₁₁ is provided to the inverting input terminal of the operational amplifier 47, a feedback resistor
Output voltage is fed back through the R _12. Resistance R ₁₁
It is set sufficiently larger than the feedback resistor R ₁₂ (e.g. 10 to 100 times). The non-inverting input terminal is grounded via a resistor R _13. The resistor R ₁₃ is not necessarily required.

Voltage adjusting circuit 48 is output V _o2 of the simple addition circuit 46 generates a control voltage V _c to be a voltage representing the fuzzy logic value of 1.0, which membership function circuit 31a of each rule board 50, 31b of the The feedback is provided to the grade control circuit 51 for controlling the peak value (grade) of the membership function. In this embodiment, the fuzzy logic value is 0.0 to 1.0.
Corresponds to a voltage of 0V to 5V. Since this voltage is inverted by operational amplifier 45 of the single-mentioned adder circuit 46, -5V is applied as the reference voltage V _o is the rotation input terminal of the voltage regulator circuit 48.

As a result, the output voltage _Vo2 of the simple adding circuit 46 is always -5V.
(Corresponding to a fuzzy logical value of 1), so that the denominator of the above-mentioned equation (4) becomes 1, and as a result, the weighted addition circuit 42
Output voltage V _o1 is to represent the center of gravity of the fuzzy inference results of. The output of the weighted addition circuit 42 is inverted by the inverting amplification circuit 43 and becomes a final non-fuzzy output as a positive voltage.

Next, a specific configuration of the rule board 50 will be described with reference to FIG. 24 taking the first rule board as an example.
Since this circuit membership function circuit 31a for generating a membership function represented by voltages, including 31b, their labels LA _1, LB ₁ is given by the voltage (V these labels voltages respectively _LA, V and _LB), the input x _a, y _B also given by the voltage signal (input voltage signals, respectively V _x, and Y _y).
Membership function circuits 31a, 31b is to output a voltage signal representative of the triangular membership function MF ₁ described above. Since the two membership function circuits 31a and 31b have exactly the same configuration, only one circuit 31a will be described. The membership function circuit 31a includes two differential circuits 61 and 62.
Therefore, the operation of these circuits will be described first with reference to FIGS. 25 and 26 taking the differential circuit 62 as an example.

In FIG. 25, the differential circuit 62 has two transistors Q
₆₁ includes a Q _62, the variable resistor R ₂₂ is connected between the emitters of these transistors. Based one transistor Q ₆₁ (which is the input terminal of the membership function circuit) (sweep signal SW is supplied to the input terminal when used in the sweep type fuzzy computer) to the input voltage V _x is given, the base of the other transistor Q ₆₂ is given a voltage V _LA representing a label. Both transistors Q current I by the current source Q _54
61, are supplied to the emitter of Q _62.

I ₆₁ the current flowing through the transistor Q _61, the transistor Q ₆₂
When the current flowing to the I _62, as shown in FIG. 26 (A), when the V _x <V _LA current of the transistor Q ₆₂ I ₆₂ = I flows, no current flows through the transistor Q ₆₁ ( I ₆₁ =
0). When the input voltage V _x becomes more than the label V _LA, the current I ₆₂ of the transistor Q ₆₂ is linearly reduced, the transistor Q ₆₁
The current I ₆₁ flowing through increases linearly from zero. And when it is _{V x = V LA + R 22} I, I 62 = 0, I 61 = I , and the in the region of more large V _X is maintained in this state.

Current mirror CM ₂ is provided, this current mirror is driven by the current I ₆₂ flowing through the transistor Q _62. The output side of the current mirror CM ₂ resistor R _L is connected to the voltage appearing at the resistor R _L and voltage x _2. Since the voltage x ₂ is given by x ₂ = I ₆₂ R _L, the voltage x ₂ is the relative change in the input voltage V _x
26 It changes as shown by the solid line in FIG. Gradient of the portion where the voltage x ₂ changes linearly is given by -R _L / R _22. Therefore, it is possible to change this gradient by varying the value of resistor R _22.

In FIG. 24, another differential circuit 61 is also a differential circuit 62.
It has the same configuration as. Transistor Q, the transistor Q ₅₁ and the label voltage V _LA input voltage V _x is given is given
When the current flowing through the ₅₂ and I _51, I _52, respectively, these current changes as shown in Figure 26 with respect to the input voltage V _x (C).

Current mirror CM ₁ is driven by the current I ₅₁ flowing through the transistor Q _51. Since the current flows I ₅₁ is connected to the resistor R _L to the output side of the current mirror CM _1, the voltage x ₁ lowering in the resistance R _L is the x ₁ = I ₅₁ R _L. Graph showing changes in voltage x ₁ with respect to the input voltage V _x is the solid line in FIG. 26 (D). Gradient of the portion voltage x ₁ is increases linearly is given by R _L / R _21. Two transistors Q of the resistor R ₂₁ is a differential circuit 61
₅₁ and a resistor connected between the emitters of Q _52, the gradient is changed by changing the value of this resistor R _21.

The membership function circuit 31a includes a two-input MIN circuit. For easier understanding, the components of this MIN circuit are denoted by the same reference numerals as the corresponding components Q ₁₁ and Q ₁₂ in the MIN circuit of FIG. Current source CS ₁
The current source 64 of the MIN circuit 24a described later is used. No compensator is provided. As described above, the compensator of the MIN circuit
The base voltage V _EB is subtracted, and the compensator of the MAX circuit adds the emitter / base voltage V _EB of the transistor. Therefore, when the MIN circuit and the MAX circuit are continuously connected, compensators for these circuits can be omitted. The aforementioned transistors Q ₃₁ and Q
_41, since no compensator is provided in the MAX circuit including a wired OR, it is possible to omit the compensator MIN circuit including transistors Q _11, Q _12.

The voltages x ₁ and x ₂ described above are the transistors that make up the MIN circuit.
Which hit the base of Q _11, Q _12. These transistors
The output voltage V _A1 (a _A1 ) appearing at the emitters of Q ₁₁ and Q ₁₂ is the MIN operation result of the voltages x ₁ and x ₂ , and its graph is shown by a solid line in FIG. 26 (E). Output voltage V _A1 is input voltage V
It changes in a triangular shape with respect to _x , and represents a triangular membership function MF. The input voltage corresponding to the peak value is the label voltage _VLA . Also by the resistor R ₂₁ or R _22, as shown by SL _1, SL _2, for example FIG. 1 (B), gradient is changed.

Although not particularly relevant in FIG. 24, it will be described for just in case, if the sweep signal described above the input voltage V _x, the output voltage V
_A1 changes like a triangular wave on the time axis. Input voltage V _x and the label voltage V _LA can take positive and negative values.

Similarly, from the other membership function circuits 31b,
An output voltage V _B1 representing a membership function value (a _B1 ) corresponding to the input voltage V _y is obtained under the set label voltage V _LB.

The MIN circuit 24a includes a wired OR 63 and a current source 64.
Then, the output voltages V _A1 and V _{B1 of the} membership function circuits 31a and 31b are given to the wired OR 63. Voltage at which the output of wired OR63 represents the MIN operation result corresponding to a _M1
V _M1 .

More specifically, the membership function circuit 31a
Transistors Q ₁₁ and Q ₁₂ and membership function circuit 31b
Transistors Q ₁₁ and Q ₁₂ , a wired OR 63, and a current source 6
It can be said that the 4 and 4 constitute a 4-input MIN circuit.

Figure 26 (E) membership function circuit 31a as can be seen from the graph of the peak value of the membership function in the 31b is determined by IR _L. If the resistance _RL is fixed, the peak value changes by changing the current I.

Grade Control circuit 51 is a circuit for changing the current I in accordance with the control voltage V _c given. The grade control circuit 51 has a current mirror CM ₄ serving as a current source. The current mirror CM ₄ and the transistors Q ₅₃ and Q _{54 serving} as current sources for the membership function circuit 31 a and the current mirror CM _{4 serving} as a current source for the membership function circuit 31 b are provided. transistors Q _53, Q ₅₄ constitute a multi-current mirror. Therefore, the current mirror CM
₄ is equal to the current I flowing through these transistors Q
It will flow to _53, Q _54. Current mirror CM ₄ contains a capacitor C _1. The capacitor C ₁ is a capacitor for phase compensation. Oscillation when the feedback input V _c of the grade control circuit 51 the output of the voltage regulator circuit 48 as Figure 23 can be prevented by the capacitor C _1.

Driving the current mirror CM ₄ Hamou one current mirror CM _5. Resistor R _o it is connected to the collector of one transistor of the current mirror CM _5. The current I _passes through this resistor _Ro.
By flows, voltage of V _R = IR _o appears.

A current source CS _o for driving the differential circuit 65 to the grade control circuit 51 is provided. Differential circuit 65 whose emitters includes two transistors Q _71, Q ₇₂ are connected by two resistors R _23, R ₂₄ equal value, the connection point of the two resistors to the output side of the current source CS _o It is connected. The base of one transistor Q ₇₁ is given control voltage V _c, the above voltage V _R is applied to the base of the other Torajisuta Q _72. If with these voltage V _c and V _R equal current flows equal to the transistors Q _71, Q ₇₂ by the current mirror CM ₃ in.

The difference occurs in the current I ₁ and I ₂ flowing through both transistors when the the voltage V _c and V _R unequal. Since the current mirror CM ₃ serves to flow a current equal to the two transistors Q ₇₁ and Q _72, the current difference between the currents I ₁ and I _2, the base of the transistor Q ₇₃ which is connected to the collector of the transistor Q ₇₂ the flow, the emitter current amplification factor β times the current of the difference of the transistor Q ₇₃ flows. Since the emitter of the transistor Q ₇₃ is connected to a current mirror CM ₄ through the Zener diode ZD, the current flowing through the current mirror CM ₄ changes. This current change is manifested as a change of the current I flowing through the resistor R _o, the voltage V _R acts to be equal to the control voltage V _c. Zener diode ZD is for imparting a suitable potential to the emitter of the transistor Q _73, may be alternatively by providing a plurality of transistors.

The current I and the voltage V _{R where} the difference between the voltage V _c and V _R is ΔV, R ₂₃ = R ₂₄ = r _c are given by the following equations.

_{I = (1 / r e)} · β · ΔV V R = R o · I = (1 / r E) · β · R o · ΔV = (1 / r e) · β · R o (V c -V _{R) Thus, V R = [(1 /} r e) · β · R o / {1+ (1 / r e) · β · R o}] · V c where _{(1 / r e) · β} · R _{If o} >> 1, then V _R = V _c . Therefore, the current I flowing through the resistor R is I = _Vc / _Ro .

As described above, the control voltage is controlled current I by V _c, the membership function circuit 31a, the peak voltage of 31b is, the output voltage V _o2 is the reference voltage V _o of the simple addition circuit 46 shown in FIG. 23 (Fuzzy (Equivalent to logic 1). Since the control voltage V _c is applied to all rule board 50, the above control is performed in all rule board 50.

The combination of the membership function circuit 31a or 31b and the grade control circuit 51 is called a grade controllable membership function circuit (GC-MFC).

Although not particularly related to this embodiment, when controlling the peak value of the grade controllable membership function circuit for each rule board, the simple addition circuit 46 is used.
Output voltage 7V _o2 (V _c ) should not be fed back to each rule board. Then, the output voltage _Vo1 of the weighted addition circuit 42 is calculated by the simple addition circuit 46 according to the equation (4).
Divided by the output voltage V _o2 so as to obtain a final non-fuzzy output.

(3) Fuzzy controller based on algebraic product rule Next, a sweep-type fuzzy controller based on algebraic rule, which is one of the applications of the grade controllable membership function circuit (hereinafter referred to as GC-MFC). explain.

As the simplest example, let us consider a case where there is one implication (control rule) and the antecedent of that implication contains one fuzzy proposition. No.
In the sweep type controller shown in Fig. 15, MIN operation is used as fuzzy inference synthesis operation (MIN
Circuit 38). The fuzzy controller described here uses an algebraic seat (so-called multiplication) as a fuzzy inference synthesis operation.

Referring to FIG. 27 (A), two GC-MFCs 31GC and 33CG are provided. This GC-MFC is a combination of a membership function circuit (MFC 1a) 31a and a grade control circuit 51 shown in FIG. On one of GC-MFC31CG given a definite value input V _x. Also, a label voltage _VLA is set. The grade control voltage for the circuit 31GC (corresponding to V _c of FIG. 24) is given a constant voltage V _c. Of course, (to the weighting, for example to be described later) as necessary for the control voltage V _c may be changed. Membership function circuit in place of the GC-MFC 31GC is when a control voltage V _c is constant (transistor circuit 31a in Figure 24
A constant current is supplied to the transistors Q ₅₃ and Q ₅₄ by a constant current source).

The other GC-MFC 33GC, sweep signal SW is supplied from the timing circuit 60 as its input (corresponding to V _x of FIG. 24). The grade control voltage as (V corresponding to _c), preceding GC-MFC 31GC of the output voltage V _A (first 24 Figure output voltage V _A1
Support) is applied to a unique label voltage V _LB are set in the circuit 33GC.

As described above, the grade control voltage sets the grade (peak value) in the GC-MFC. GC-MFC 33
GC-MFC 31 GC output voltage V _A as GC grade control voltage
From the GC-MFC 33GC, the output voltage V _A
The corresponding values were multiplied by, so that the output V _B representing the membership function distributed on the time axis is obtained. That is, a fuzzy inference operation of an algebraic product is performed.

Output voltage V _B of the GC-MFC 33GC is then applied to the center of gravity determination circuit 36SW, a voltage V _w is created to represent the center of gravity, a definite output of the fuzzy controller.

If there are multiple implications, the fifteenth
As with the fuzzy controller shown in the figure, two GC
A circuit consisting of MFC 31GC and 33GC is prepared for the number of implications, the MAX operation of those outputs is performed, and the MAX operation result may be defuzzified by a defuzzifier (center-of-gravity determining circuit).

If two fuzzy propositions exist in the antecedent part of one implication, the output of the MIN or MAX circuit 24a shown in FIG. 16 is given as a grade control voltage of the GC-MFC 33GC, and the GC-MFC 33GC Is the membership function circuit of the consequent of the implication. When there are a plurality of implications having two or more fuzzy propositions in the antecedent part, the output of each GC-MFC 33GC is output to the MAX circuit 37 (15th
Needless to say, it is only necessary to give the figure).

FIG. 27 (B) shows an example of a parallel type fuzzy controller based on the algebraic product rule. 27th
Explaining in comparison with FIG. (A), instead of the GC-MFC 33GC, a grade controllable membership function generator GC-MFG 13GC, which will be described in detail later, is used.
The output of the GC-MFC 31GC is provided as Grade Control voltage V _c of the GC-MFG 13GC. The output of the GC-MFG 13GC is given to the defuzzifier 15 and the truncation circuit is not required. This controller can also be expanded if there are multiple implications by using the MAX circuit 16, or by applying the output of the MIN or MAX circuit 24a shown in FIG. 14 as the control voltage Vc to the GC-MFG13GC. It can be extended to be applicable even when two or more fuzzy propositions exist in the antecedent part of the application.

An example of the center of gravity determination circuit 36SW in FIG. 27 (A) will be briefly described with reference to FIGS. 28 and 29.
FIG. 28 is an example of a configuration of the center of gravity determination circuit 36SW, and FIG. 29 is a waveform diagram showing the operation of the fuzzy controller shown in FIG. 27 including the center of gravity determination circuit. In the sweep type fuzzy controller, a voltage signal representing an inference result is expressed on a time axis. The fuzzy inference is performed for each period τ of the sweep signal SW, and one operation of determining the center of gravity is performed in two periods 2τ. Thus, during two periods 2.tau, the input voltage V _x is held constant. Let T be the time axis of the sweep signal SW, and let t be a local time variable of the voltage V _B (t) representing the inference result. The origin of the time t is, for example, a point where the sweep signal SW crosses zero.

As described with reference to FIG. 9, the position of the center of gravity of the inference result B 'is the time when the area of the function B' = μ (t) is divided into two on the time axis, left and right (front and back). The area S ₀ of the inference result B ′ output in the first cycle is obtained. Then the second
In the period of the integral operation for obtaining the area of the inference result B 'is performed on a time axis, the time t _w when the integrated value just becomes S _0/2 is to represent the center of gravity position. That is, the center of gravity of the inference result B ', the time on the time axis t when the integration value becomes S _0/2 or time or sweep signal at this time on the time axis T at that time,
Expressed by the phase of SW. This phase of the sweep signal SW is further represented as a voltage V _w of the sweep signal SW corresponding thereto. Therefore, this voltage _Vw is the inference result B '
Is output from the center-of-gravity determining circuit 36SW.

Referring to FIGS. 28 and 29, the above-described integration operation for obtaining the area can be realized by charging the capacitor, and the charging voltage represents the integrated value. Capacitance is 2C ₀ (C ₀ is a certain value)
And the capacitor C _11, the capacitance and the capacitor C ₁₂ of the C ₀ is provided as a half thereof. Voltage signal V _B representing the inference result is converted into a current I _B corresponding to the voltage at the voltage / current converting circuit 63 is supplied to the change-over switch 64. Changeover switch 64 is a one to switch whether to flow into the current I _B in the capacitor C ₁₂ or to flow into the capacitor C _11, is controlled by the switch control signal SC, the switching control signal SC is outputted from the timing circuit 60, It becomes H level in the first cycle and L level in the second cycle.
Repeat with τ.

In the first cycle the input current I _B is applied to the capacitor C _11, is charged in the capacitor C _11. Voltage V ₁ of the capacitor C ₁₁ at the time when the first period has ended represents the area S ₀ of the above, which is provided to the negative input terminal of the comparator 65. In the second period, the current I _B flows into the capacitor C ₁₂ through the switch 64. Since the capacitance of the capacitor C ₁₂ is a half of the capacitance of the capacitor C _11, an area (which is which is integrated when the half of the charge of the charging electric charge of the capacitor C ₁₁ is charged in the capacitor C ₁₂ is the S _0/2 it means that the), the voltage V ₂ of capacitor C ₁₂ is the voltage of the capacitor C ₁₁
V equals ₁ . Voltage of the capacitor C ₁₂ is comparator 6
5 positive input terminal. Therefore, it comes to the time when the output V ₀ which comparator 65 is up standing is the time t _w representing the center of gravity. When the second cycle ends, the charges of the capacitors C ₁₁ and C ₁₂ are discharged by the switches 61 and 62 which are turned on by the reset signal PR generated from the timing circuit 60.

Output voltage V _o of the comparator 65 is then in the matter of the rise of the signal V _0, is sent to the time t _w of the rise in the circuit for converting the voltage V _w of the sweep signal SW corresponding thereto. Signal V ₀
Is detected by a differentiating circuit 66, and this rising detection pulse is converted into a single pulse signal _SD having a constant width by a monostable multivibrator or the like and output. The pulse width of the pulse signal S _D may be any time sufficient to charge the capacitor C _c to be described later, as short as possible it is preferable. The pulse signal _SD is used to control the analog switch 67, and this switch 67 is turned on for the duration of the pulse width of the pulse signal _SD . Then, the capacitor _Cc is charged by the sweep signal SW input to the switch 67 until the voltage of the capacitor Cc becomes equal to the current voltage of the signal. The voltage of the capacitor _Cc is held until the next pulse signal _SD is generated. When the switch 67 by the next pulse signal S _D is turned on, the capacitor C _c to a voltage of the sweep signal SW is equal to the voltage of the Invite sweep signal SW higher than the voltage of the capacitor C _c is charged, if low Sweep signal SW
Capacitor _Cc is discharged until the voltage becomes equal to In this way, the voltage of the capacitor _Cc always represents the determined position of the center of gravity. This voltage is output for example via an FET input operational amplifier 68 as the center-of-gravity position voltage V _w.

Centroid determining principles according to the circuit of FIG. 28 is filled into the first capacitor capacitance 2C _o with the input current in the first cycle, then, in a second period following this, the first capacitor at the same input current the continue to charge the second capacitor half of the capacity c _o capacity, which voltage of the second capacitor to detect when t _w that is equal to the voltage of the first capacitor as the time which represents the center of gravity It is. 2C _o capacitance
And instead of using two capacitors C _o, it is also possible to use two capacitors capacitance are equal. In this case, a current that is twice the input current is used in the second integration operation of the inference result. That is, in this method, a first capacitor having a certain capacity is charged by an input current, and then a second capacitor having the same capacity as the first capacitor is charged by an input current twice as large. time t _w the voltage of the capacitor becomes equal to the voltage of the first capacitor
May be detected as the time representing the center of gravity. The voltage may be doubled instead of the current.

(4) Fuzzy controller capable of assigning weights to each rule Fig. 14 shows a parallel controller when there are multiple implication rules (control rules) having two fuzzy propositions in the antecedent part, as described above. 1 shows a fuzzy controller of the type. Fuzzy inference for one implication rule (control rule) is executed by one fuzzy inference synthesizing circuit 14a to which the outputs of two membership function circuits 31a and 31b and one membership function generating circuit 13 are input. You. A group of these circuits 31a, 31b, 13 and 14a is called a rule board.

In fuzzy inference on the premise that there are multiple implication rules (control rules), not all implication rules always have the same importance. Some of the implications will be very important and others will be less important. Therefore, the implication rules (control rules) are weighted according to their importance. This weighting is performed on the rule board. Weighting is performed by simultaneously controlling the grade (peak value) of the membership function of both the antecedent and consequent parts,
Those with higher importance are set to higher grades. The same weight is assigned to the membership function circuit and the membership function generation circuit belonging to one rule board.
That is, the peak of the membership of the antecedent and the consequent is set to the same value.

To control the weight of the membership function of the membership function circuit,
A membership function circuit (GC-MFC) is used. To weight the membership functions generated from the membership function generator,
Controllable membership function generator (GC-
MFG) is used. Using such GC-MFC and GC-MFG, one rule of the fuzzy controller of FIG.
The rewritten circuit of board R is shown in FIG. No.
In FIG. 30, the membership function circuits 31a and 31 shown in FIG.
b, Membership function generator 13 is GC-MFC 31GCa, 31GC
b, GC-MFG Except that it is replaced by 13GC, it is exactly the same as one rule board shown in FIG. GC-MFC 31GC
a, (Pikuno value of the membership function) up to grade 31Gcb and GC-MFG 13GC is controlled to be identical with one grade control voltage V _c. This control voltage V _c
May be manually set from the outside, or may be adjusted by a digital computer or the like in accordance with the learning result of the control target using the fuzzy controller.

Control voltage V _c in GC-MFC is, GC-M shown in FIG. 24
FC (grade control circuit 51 and membership function circuit 31a
Or given to the place of the control voltage V _c in composed) by a combination of 31b. GC-MFG is described below.

In FIG. 31, a GC-MFG 73 includes a voltage distribution generating circuit 74 for generating a predetermined voltage distribution on a plurality of signal lines, a switch array 75 for sending out the generated voltage distribution on a predetermined power signal line, and It comprises a decoder 76 which decodes a code representing a given label and controls the switches of the switch array 75. Voltage distribution generator
The shape of the voltage distribution generated from 74 is predetermined, but the position of this voltage distribution on the output signal line is varied by a switch array 75 controlled by the output of decoder 76. Therefore, a voltage distribution representing the membership function corresponding to the given label appears on the output line. Voltage score grade generated by the voltage distribution generator circuit 74 (voltage value) is adjusted by the grade control signal V _c.

Some specific examples of GC-MFG will be described below. Here, seven types of membership functions are generated.
Label these membership functions with NL, NM,
NS, ZR, PS, PM and PL. It is also assumed that the number of points (corresponding to the number of elements of the fuzzy set) in the variable area of the membership function is limited to 25. Therefore, there are 25 output terminals of the membership function generation circuit.

FIG. 32 and FIG. 33 show examples of GC-MFG using a switch matrix as a switch array. In FIG. 32, below the output terminals numbered from 0 to 24 of the GC-MFG, seven types of membership functions output from these output terminals are illustrated.

The output value of the fuzzy membership function is quantized into four levels for simplicity. The four levels are _{0, V c1, V c2,} V c3 = V c, the maximum value of the control voltage V _c is, for example, 5V. These four levels of voltages are generated in voltage distribution generating circuit 74A. The circuit 74A comprises three resistors 71 connected in series, the control voltage V _c to the resistance circuit is applied, the voltage at the connection point of the resistor 71 is V _c1, V _c2. Therefore, _{V c1 = V c / 3,} V c2 = 2V c / 3. Five voltage lines V2, which are obliquely drawn in FIG. 32, extend from the voltage distribution generating circuit 74A.
_c3 , the voltage _Vc2 on the lines on both sides, and the outermost 2
Each of the lines is _supplied with a voltage _Vc1 .

The decoder 76A is a 1-of-8 decoder. A 3-bit (c ₁ , c ₂ , c ₃ ) binary signal representing a label is input to the decoder 76A. Decoder 76A outputs an H-level signal to one of eight output terminals according to the code represented by the input signal. The eight output terminals correspond to no designation and the seven types of labels described above. For example, when the input code signal is 000, an H-level signal is output to an undesignated departure terminal, and when the input code signal is 001, an H-level signal is output to an NL output terminal. From these output terminals, signal run-in SL indicated by horizontal lines in FIG. 32 is extended except for output terminals not specified.

In the switch matrix 75A, an output line OL extends from a predetermined intersection of the voltage line VL and the signal line SL to 25 output terminals. The signal 75a indicated by a small square at these intersections is provided between the voltage line VL and the output line OL, and is turned on and off by the voltage of the signal line SL, as shown in FIG. The switch is composed of, for example, a MOS FET. One output line O
Of course, L may be provided with two or more switches 75a. Each output line OL is grounded on its output terminal side via a resistor 75b.

In the above configuration, when a label of a certain membership function is given to the decoder 76A, an H (enable) level signal appears on a signal line SL corresponding to the label, and a switch 75 provided on the signal line is provided.
a turns on. As a result, each voltage of the voltage distribution generating circuit 74A appears at the corresponding output terminal via the output line OL through the switch 75a that is turned on, so that the voltage distribution representing the membership function is output.
The grade of the membership function outputted is varied by a control voltage V _c.

34 and 35 show a GC-MFG using a pass transistor array 75B as a switch array.

Voltage distribution generator circuit 74B, in order to quantize the membership functions at the level of 11, has a voltage dividing circuit consisting of ten series resistors 71, the control voltage V _c is applied to the voltage divider circuit. Ground terminal and the fuzzy truth value voltage to the connection point of the resistors _{0, V c1 = V c /} 10, V c2 = 2V c / 10, ..., V c9 = 9V c / 10, V c10 =
Appears V _c, these fuzzy truth value 0,1 / 10, ..., corresponding respectively to the 9/10 and 1. These voltages V _c1 ~V _c10 is also variable by a control voltage V _c. Also this generation circuit
The 74B has a PROM programmed with the value of the label = ZR membership function. This PROM is provided with a power supply line VL connected to the voltage source and the ground, and an output line OL connected to an output terminal via a pass transistor array 75B. PROM has two layers, upper and lower
An output layer OL is formed on the first layer, and a power supply line VL is formed on the second layer. These upper and lower 2
The layers are insulated by an insulating layer such as photosensitive polyimide. By forming through holes at the intersections of these layers, the shape of the membership function is programmed. Since the through-holes can be formed using mask ROM technology, any form of membership function can be programmed. A black circle indicating a node between the line VL and the line OL indicates a through hole. The line VL and the line OL are connected at the point where the through hole is formed,
Fuzzy truth voltage is pass transistor array 75B
Is forwarded to The node between the two lines VL and OL may be short-circuited by field ROM technology, that is, by applying a high voltage to break down the desired intersection.

The pass transistor array 75B outputs the output line OL extending from the voltage distribution generating circuit 74B, the signal line SL connected to the seven output terminals of the decoder 76B, and the voltage at the intersection of these lines to the left or right by four digits or eight. Includes a diagonal line BL for shifting by the digit, a switching element provided at the intersection of the signal line SL with the output line OL and the diagonal line BL, and a PMOS FET 75c controlled by the voltage of the signal line SL. Have been. The state of connection of the switching element 75c is shown in FIG. Each switch array rows of switching elements controlled by the connected seven signal lines SL also those lines to the decoder _{76B S 1, S 2, ...} S 7
And S _{1 to} S ₇ sometimes refer to signals on these lines SL.

Switch array S ₁ is shifted membership function programmed in the voltage distribution generator circuit 74B to 4 digits left, the switch rows S _3, S ₄ and S ₆ are 4 digits right, respectively left 8 digits and 8 digits right shift. Switch array S ₂ and S ₅ is not to shift the programmed membership function to the right or left, directly sends the output terminal thereof. Switch array S ₇ is a switch array, which is grounded, dropping the switch S ₇ is turned on, all the output terminals to the ground level when the other switch S ₁ to S ₆ is turned off.

Relationship between Bainaryi level of membership functions of the label and the signal S ₁ to S ₇ are shown in Figure 36. decoder
76B is a 3-bit binary signal c ₁ , c ₂ , c ₃ (0
V or + 5V) according to the table shown in FIG.
The bit signals are converted into binary signals S _{1 to} S ₇ (−5 V “L level” or +5 V “H level”). Specifically, as shown in FIG.
It consists of a combination with

For example, the label you entered is in the case of PL, the switch rows S ₃ and S ₆ are turned on. The membership function programmed in the voltage distribution generator circuit 74B, is shifted through the switch row S ₃ to 4 digits right, is further shifted to the 8 digit right through the switch row S _6, therefore, the programmed membership function was 12 The membership function shifted to the right by the digit and appearing at the output terminal is
PL (large positive value).

In FIG. 34, the ground
The line VL connected to the level is connected to the center 25 output lines OL, and to the left and right, 12 lines each parallel to the output line OL and the oblique line BL are connected. At the intersection with the signal line SL, the switch rows S ₁ and S
₂ , S ₃ , S ₄ and S ₆ are provided. This means that no matter how the programmed membership function is shifted,
This is to ensure that the ground level signal is output to the output terminal.

Pass transistor array 75B must pass the fuzzy truth voltage (0-5V) to the output terminal without attenuating. In a normal PMOS circuit, if the fuzzy truth value voltage is lower than the threshold voltage of the PMOS FET, the PMOS FET has a gate voltage V _G (output of the decoder) of 0.
If it is V, it will not be completely on. To ensure that PMOS FET is fully on, there is a need to a V _G to -5V about. To this end, as described above, the decoder 76B is configured to generate an output that takes -5V (L) and + 5V (H). An example of a NAND gate 77 constituting the decoder of Figure 37 for generating such an output signal S ₁ to S ₇ are shown in FIG. 38.

In the above description, the fuzzy membership functions are shown as chevron or triangular. However, various types of membership functions are conceivable, and it is preferable that a different type can be selected as needed.

FIG. 39 shows a voltage distribution generating circuit mainly applicable to a GC-MFG of the type shown in FIG. 32, in which a fuzzy membership function type can be selected. The partial pressure is controlled by a control voltage V _c voltage V _c1 ~V _c4
The output line OL is connected to the voltage line VL connected to the node where appears, so as to output a voltage distribution representing a fuzzy membership function form of a mountain or triangle shape.
1 and an output line OL2 connected to output a voltage distribution representing a trapezoidal function form. These lines OL1 and OL2 have switching elements and NMOS
The FETs 70A and 70B are connected, and the lines OL1 and OL2 on the output side of these switching elements are connected to an output line OL connected to an output terminal. Switching element 70B
The directly by the selection signal c _s, elements 70A inverter 79
Respectively.

When the selection signal c _s is at the L level, the switching element 70
When A is turned on, a voltage representing a chevron or triangular membership function form is output to the output line OL.
Conversely, when the signal _cs is at the H level, the element 70B is turned on, so that a voltage representing a trapezoidal function is output. In this way, it is possible to select the fuzzy membership function form.

In the circuit of the 39 figure, if FET 70A, the thread hold value voltage 70B and V _TH (usually about 1V), Bainaryi-level selection signal c _s to control these FET is, L level V
_It suffices if it is below _TH and the H level is above V _TH + 5V. Where 5V
Is the maximum voltage of the control voltage V _c.

As for the distribution form of the generated voltage in the voltage distribution generation circuit, that is, the fuzzy membership function form, not only the above-mentioned two forms, but also three or more forms can be prepared in advance and one of them can be selected. You can also do so. It goes without saying that the selection of the function form is also applicable to the GC-MFG shown in FIG.

The voltage distribution generating circuit generates voltage signals distributed on a plurality of lines. Therefore, it is possible to apply the output voltage of one voltage distribution generating circuit to a plurality of switch arrays 75. FIG. 40 includes one voltage distribution generating circuit 74 and a plurality of switch arrays 75 to which the output voltage is applied.
GC-MFG is shown. Each switch array 75 is driven by a respective decoder 76. Each decoder 76 is provided with a code signal of the same or different label. Therefore, a plurality of voltage distributions representing the same or different membership functions can be obtained from the GC-MFG. Moreover equal and can be controlled simultaneously by grade control voltage V _c of the plurality of membership functions.

The GC-MFG shown in FIG. 40 is suitably used especially for the parallel type fuzzy computer shown in FIGS. 4 and 5 (see the sixth invention). Also in this case, it is needless to say that the grade can be controlled for each application.

GC-MFC is also applicable to the sweep type fuzzy computer shown in FIG. 8 (see the eighth invention). In this case, it is preferable that the grade can be adjusted for each application.

[Brief description of the drawings]

FIG. 1 is a graph showing a membership function. FIG. 1A shows a general function, FIG. 1B shows a triangular and trapezoidal function, and FIG. 1C shows a Z function and an S function. Each function is shown. FIG. 2 shows a membership function represented by voltages distributed on a plurality of signal lines. FIG. 3 is a waveform diagram showing a sawtooth sweep signal and a membership function signal waveform. FIG. 4 is a block diagram showing the concept of a basic parallel type fuzzy computer, and FIG. 5 is a block diagram showing the concept of the same type fuzzy computer when a plurality of implications exist. FIG. 6 is a block diagram showing the configuration of a basic parallel type fuzzy inference engine. FIG. 7 is a block diagram showing the concept of a basic sweep type fuzzy computer, and FIG. 8 is a block diagram showing the concept of a sweep type fuzzy computer applied to fuzzy inference having a plurality of implications. It is. FIG. 9 is an explanatory diagram schematically showing the process of fuzzy inference. FIG. 10 shows the concept of an extended fuzzy inference engine of the parallel type, and FIG. 11 is a block diagram showing its configuration. FIG. 12 and FIG. 13 are explanatory diagrams of the inference process in the fuzzy controller. FIG. 14 is a block diagram showing a configuration of a parallel type fuzzy controller. FIG. 15 is a block diagram showing the configuration of a sweep type fuzzy controller, and FIG. 16 is a block diagram showing another example of the controller. FIG. 17 is an explanatory diagram of the inference process when the consequent part of the implication is represented by a singleton. FIG. 18 is a circuit diagram of a weighted addition circuit, and FIG. 19 is a circuit diagram of a simple addition circuit. FIG. 20 is a graph showing the membership function, its label, and its singleton form. FIG. 21 is a circuit diagram of the MIN circuit, and FIG. 22 is a circuit diagram of the MAX circuit. FIG. 23 is a circuit diagram showing the configuration of a fuzzy processor.
FIG. 24 is a circuit diagram showing the configuration of the rule board of the fuzzy processor. FIG. 25 is a circuit diagram showing a part of the membership function circuit for explaining the membership function circuit, and FIGS. 26 (A) to (E).
Is a graph showing signals of the same circuit. FIGS. 27 (A) and 27 (B) are block diagrams each showing a configuration example of a fuzzy controller for performing inference by algebraic product operation. FIG. 28 is a circuit diagram showing a configuration of the center of gravity determination circuit. FIG. 29 is a waveform chart showing the operation of the circuits shown in FIGS. 27 and 28. Fig. 30 shows the rules for a parallel type fuzzy controller that weights each rule board.
It is a block diagram showing a board. FIG. 31 is a block diagram showing a basic configuration of a grade controllable membership function generating circuit. FIG. 32 is a circuit diagram showing a grade controllable membership function generation circuit realized using a switch matrix, and FIG. 33 shows a specific configuration of symbols in FIG. FIG. 34 is a circuit diagram showing a grade controllable membership function generation circuit realized by using a pass transistor array. FIG. 35 is a diagram showing a specific configuration of symbols in FIG. 34. Is a table showing the operation of the decoder in FIG. 34, FIG. 37 is a circuit diagram showing a specific configuration of the decoder, and FIG. 38 is a circuit diagram showing a NAND gate used in the circuit in FIG. FIG. 39 is a circuit diagram showing a voltage distribution generating circuit capable of selecting a membership function type. FIG. 40 is a block diagram showing a developed form of the grade controllable membership function generating circuit. 11,12,13 …… Membership function generation circuit, 13GC …… Grade controllable membership function generation circuit, 14 …… Fuzzy inference engine, 14a, 34 …… Fuzzy inference synthesis circuit, 31,32,33… ... Membership function circuit, 31GC, 33GC, 31GCa, 31GCb ... Grade controllable membership function circuit, 50 ... Rule board, 51 ... Grade control circuit, 52 ... Switch array, 53 ... Connector .

Claims (8)

(57) [Claims] 1. A output signal (a _A1 or a _B1) level peak level portion represents the membership functions predetermined determined by the label signal (L _A1 or L _B1) of the signal (a _A1 or a _B1) the membership function circuit to output according to the input signal (x _a or y _B) (31a or 31b), and the level of the output signal of the membership function circuit (31a or 31b) (a _A1 or a _B1) A grade controllable membership function circuit comprising: a grade control circuit (51) for controlling according to an input grade control signal (V _c ). 2. A signal distribution generating circuit (74 or 74A or 74B) for generating a signal level distribution representing a membership function by signal levels distributed on a plurality of signal lines, and according to a given label signal, A switch array (75 or 75A or 75B) for converting a signal level distribution into predetermined positions on a plurality of output signal lines, wherein the signal distribution generating circuit (74 or 74A or 74B) is provided with a grade control signal A grade controllable membership function generating circuit comprising a circuit portion for generating a signal of a plurality of levels by dividing a level of (V _c ). 3. A first stage circuit (31GC or 24a) for outputting a signal representing a membership function value corresponding to one or a plurality of applied inputs or a signal representing a predetermined operation result of a signal representing a plurality of membership function values. ), A sweep signal generation circuit (60) for generating a sweep signal (SW) having a constant period, and a signal representing a predetermined membership function in synchronization with the input sweep signal (SW), and the first-stage circuit ( The output signal of 31GC or 24a) is the grade control signal (V
_c ) a grade controller membership function circuit (33GC) in which the level of a signal representing a membership function output according to the grade control signal (V _c ) is controlled in accordance with an algebraic product rule. Sweep type fuzzy controller. 4. An initial stage circuit (31GC or 24a) for outputting a signal representing a membership function value corresponding to one or a plurality of applied inputs or a signal representing a predetermined operation result of a signal representing a plurality of membership function values. ), And a signal level distributed on a plurality of signal lines representing the membership function is generated and output, and the output signal of the first stage number (31GC or 24a) is given as a grade control signal (V _c ). A parallel type fuzzy controller based on an algebraic product rule, including a grade controllable membership function generator (13GC) in which the level of a signal level distribution to be output is controlled according to a grade control signal (V _c ). 5. A signal representing a membership function corresponding to a given input signal is output, and a level of a signal representing a membership function outputted according to a given grade control signal (V _c ) is controlled. One grade controllable membership function circuit (31GCa, 31GCb), for generating and outputting signal levels distributed on a plurality of signal lines representing the membership function, and the above grade controllable membership function The same grade control signal (V _c ) as that of the circuits (31GCa, 31GCb) is given, and the grade controllable membership function generation in which the level of the signal level distribution to be output is controlled according to the grade control signal (V _c ) Circuit (13GC) and the above grade controllable membership function Fuzzy inference synthesizing circuit (14a) for performing a predetermined fuzzy inference operation on the output signal of the circuit (31GCa, 31GCb) and the output signal of the grade controllable membership function generating circuit (13GC). Fuzzy controller. 6. A signal which is distributed and generated on a plurality of signal lines each representing a different membership function and is output, and is supplied with the same grade control signal, and is output in response to the grade control signal. At least three grade controllable membership function generation circuits whose levels are controlled, and a predetermined fuzzy inference operation is performed on output signals of the at least three grade controllable membership function generation circuits. Fuzzy inference engine that performs parallel processing. 7. A signal for representing a membership function corresponding to an applied input signal is output, and a level of a signal representing a membership function output in response to a provided grade control signal is controlled.
Controllable membership function circuit, a sweep signal generation circuit for generating a sweep signal of a fixed period, a signal representing a membership function on a time axis in synchronization with the sweep signal, and the first grade A second grade controllable membership function circuit that receives the same grade control signal as the controllable membership function circuit and controls the level of the output signal in accordance with the grade control signal; A fuzzy inference synthesizing circuit for performing a predetermined fuzzy inference operation on an output signal of the second grade controllable membership function circuit; 8. A sweep signal generating circuit for generating a sweep signal of a fixed period, outputting signals representing different membership functions on a time axis in synchronization with the sweep signal, and receiving the same grade control signal. At least three grade controllable membership function circuits whose output signal levels are controlled in accordance with the grade control signal, and performing a predetermined fuzzy inference operation on the output signal of the grade controllable membership function circuit A fuzzy computer of the sweep type comprising a fuzzy inference synthesis circuit to be executed.