JP2769163B2 - Center of gravity determination circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION One of the defuzzifiers for converting a fuzzy quantity into a definite value is a centroid determining circuit. To determine the center of gravity, multiplication and division are required. By controlling the magnitude of the electric signal representing the fuzzy amount so that the divisor (denominator) becomes 1, and using a weighted addition circuit, the multiplication circuit and division can be performed. The circuit can be omitted.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a center-of-gravity determining circuit which is positioned as an effective circuit of a defuzzifier for converting a fuzzy quantity into a definite value.

The inventor has already proposed a hardware system called a fuzzy controller or fuzzy computer which can process fuzzy information at high speed. In this system, fuzzy information including a fuzzy membership function, a fuzzy inference result, and the like are represented by electric signals (voltage or current) distributed on a plurality of lines. Often it is necessary to find a single definite value from fuzzy information represented by an electrical signal distribution output from a fuzzy controller or a fuzzy computer. A circuit for converting fuzzy information into a definite value is a defuzzifier, and an example of a defuzzifier is a center-of-gravity determining circuit.

The center of gravity determination circuit includes a multiplication circuit, an addition circuit, and a division (division) circuit. Here, the hardware of the multiplication circuit and the division circuit is complicated, adjustment is not easy, and the dynamic range is limited.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a circuit capable of determining the center of gravity of fuzzy information without using a multiplication circuit and a division circuit.

The center-of-gravity determining circuit according to the first aspect of the present invention provides a weight for multiplying each of the electric signals representing fuzzy information distributed on a plurality of lines by a predetermined value k and multiplying each of the electric signals by a value according to the rank of the line to add them. Adder circuit, a simple adder circuit for multiplying each of the electric signals representing the fuzzy information by a predetermined value k and adding them together, and the above-described predetermined adder so that the output signal of the simple adder circuit represents a value corresponding to 1. It is characterized by comprising control means for controlling the value k.

According to the first invention, the predetermined value k is controlled so that the output signal of the simple adder circuit represents a value corresponding to 1, so that each of the electric signals distributed on a plurality of lines has The output signal of the weighted addition circuit that multiplies the values according to the ranks and adds them will represent the center of gravity. Since the output signal of the simple addition circuit serving as the divisor (denominator) in the center-of-gravity calculation represents 1, the division circuit is unnecessary. Further, since multiplication and addition are performed by a weighted addition circuit, an addition circuit in a normal sense is unnecessary. In this manner, the center of gravity of the fuzzy information is determined with a simple configuration, and a signal representing the determined center of gravity can be obtained.

The center-of-gravity determining circuit according to the second invention executes a predetermined fuzzy inference based on an output signal of a membership circuit (including a membership function circuit and a membership function generating circuit) for outputting a signal representing a membership function. Is applied to a fuzzy processing device (including a fuzzy computer and a fuzzy controller) that outputs a signal representing the inference results distributed on a plurality of lines, and outputs the inference results distributed on the plurality of lines. A weighted addition circuit for multiplying each of the signals represented by a value corresponding to the rank of the line and adding them, a simple addition circuit for adding signals representing inference results distributed over a plurality of lines, and a simple addition circuit. A group for controlling the level of the signal output from the membership circuit so that the output signal indicates a value corresponding to 1. Characterized in that it comprises a chromatography de control means.

In the second invention, the output signal of the simple addition circuit is 1
Since the grade of the membership function of the membership circuit in the fuzzy processing device is adjusted so as to represent a value corresponding to the following equation, the multiplication circuit and the division circuit are omitted as in the first invention, and the fuzzy inference is performed. The center of gravity of the result can be determined.

Description of Embodiment [First Embodiment] FIG. 1 shows the overall configuration of the center of gravity determination circuit. The input of this center of gravity determination circuit is fuzzy information. This fuzzy information indicates the inference result output from the fuzzy inference synthesis circuit of the fuzzy controller or the fuzzy inference engine of the fuzzy computer.
It may represent the middle of inference or may represent a membership function output from a membership function generating circuit.

There are n signal lines l ₁ , l ₂ , l ₃ ,..., l _i ,..., l _n−1 , l _n , and the fuzzy information is an electric signal (voltage or current) distributed on these n lines. ). Fuzzy information is a fuzzy set (or membership function)
The fuzzy set (membership function) is a set of grades (function values) corresponding to a plurality of elements (variables).

FIG. 2 shows an example of fuzzy information. Let the elements of the fuzzy set (or the variables of the membership function) be x
, Which are discrete values x ₁ , x ₂ , x ₃ , ..., x _i , ..., x _n-1 , x
_{Let n} be taken. The element (or variable) x ₁ ~x _n is embodied by a plurality of signal lines l ₁ to l _n. The grade corresponding to these elements (function value corresponding to the _{variable) μ 1, μ 2, μ} 3, ..., μ i, ..., μ n-1, μ n is on these lines l ₁ to l _n Represented by an analog voltage or current signal appearing.

In the following discussion it is assumed that grade μ ₁ ~μ _n is represented by a voltage. Voltage representing the grade μ ₁ ~μ _n in the circuit thus also expressed in convenience μ ₁ ~μ _n.

The center of gravity CG (position on the x-axis) of this fuzzy information is given by the following equation.

Multiplication, addition and division (division) are required to find the center of gravity CG as can be seen from equation (1). According to the center of gravity determination circuit of FIG. 1, the center of gravity CG is obtained only by addition without using multiplication and division.

 Equation (1) is modified as follows.

If k is adjusted so that the denominator of the equation (2) becomes 1, the center of gravity CG is represented by the following equation.

In FIG. 1, n signal lines l _i on which a voltage μ _i representing fuzzy information is distributed are connected to the input side of the variable coefficient array 5. Coefficient k multiplying calculates voltage μ _i (kμ
_i ) is performed by the variable coefficient array 5.

The output (kμ ₁ ) (i = _{1 to} n) of the variable coefficient array 5 is given to the weighted addition circuit 2. Weighted addition circuit 2
Is the operation on the right side of equation (3) (Kμ ₁ ) x _i to output a voltage signal representing the center of gravity CG.

The output (kμ ₁ ) (i = _{1 to} n) of the variable coefficient array 5 is also input to the simple addition circuit 3. This simple addition circuit 3 is a denominator of the formula (2). The calculation of (kμ _i ) is performed, and an output representing the calculation result is input to one input terminal of a voltage adjustment circuit (comparator or differential circuit) 4.

The other input terminal of the voltage adjusting circuit 4 is supplied with a voltage corresponding to grade 1 in the fuzzy information. Individual grades representing fuzzy information can take on continuous values in the range of 0-1. The coefficient k in the variable coefficient array 5 is adjusted by the output signal of the voltage adjustment circuit 4 so that the output of the simple addition circuit 3 always becomes 1.

FIG. 3 shows a specific configuration example of the weighted addition circuit 2. A resistor connected in parallel to the input side of the operational amplifier 41
Variable coefficient array 5 through R ₁ , R ₂ , R ₃ , ..., R _i , ..., R _n-1 , R _n
Output _{kμ 1, kμ 2, kμ 3} , ..., kμ i, ..., kμ n-1, kμ n inputs. The operational amplifier 41 is provided with a feedback resistor _Rf .

Therefore, the output voltage V ₀ which operational amplifier 41 is given by the following equation.

V ₀ = − [(R _f / R ₁ ) kμ ₁ + (R _f / R ₂ ) k μ ₂ + ... + (R _f / R _i ) k μ ₁ + ... + (R _f / R _n ) k μ _n ] (4) R _f / Ri = x _i (5) Equation (4) is simplified as follows.

This is substantially the same as Equation (3) described above. The minus sign simply indicates the inversion of the voltage, and if necessary, an inversion (amplification) circuit may be connected to make the value positive.

The (5) As can be seen from the equation, elements (variable) x _i of the fuzzy information, as embodied by the sequence position of the signal line l _i (membership function) is the weighted addition circuit 2, input-side resistor It is represented by R _i and is realized.

It can be easily understood that the simple addition circuit 3 is realized by setting all the input-side resistors R _i (i = 1 to n) to the same value in the configuration of the weighted addition circuit shown in FIG. Like.

The variable coefficient array 5 can be realized by various means. For example a variable amplification circuit amplification factor k is the output voltage of the voltage regulator circuit 4 to be realized by providing each line, the input resistance of the simple addition circuit 3 and the weighted addition circuit 2 (R ₁ ~R _n, etc.) Can be realized by changing the same at the same time. Further, as shown in FIG. 4, a MOS FET can be used instead of the feedback resistor.

In FIG. 4, the weighted addition circuit 2 includes an operational amplifier 41.
NMOS FETs Q as a feedback resistor and a plurality of input resistors R ₁ to R _{n
Consists of one} and the other. The simple addition circuit 3 includes an operational amplifier 42, and a nMOS FETs Q ₂ Metropolitan used as a feedback resistor and a plurality of input resistors R of the same value. Since these MOS FETs Q ₁ and Q ₂ are controlled by the output voltage V _C of the voltage adjusting circuit 4 to change the resistance between the source and the drain, the gains k ₁ and k _{2 of} these adding circuits 2 and 3 are changed. Instead, the output of the simple addition circuit 3 can always be 1. It is preferable to use the good linearity of the drain characteristic of the MOS FET. In this embodiment, equation (2) is expressed as follows.

Further, the input resistors R _{1 to} R _n and R may be replaced by MOS FETs. In this case, it is particularly suitable for IC.

Second Embodiment Next, a fuzzy membership function generating circuit (MF
G) and / or fuzzy membership functions (MF
An embodiment will be described in which the denominator of equation (2) is set to 1 by adjusting the grade of C).

Prior to the description of this embodiment, a fuzzy processing circuit (including a fuzzy computer and a fuzzy controller) will be described.

(1) Fuzzy inference and concepts of fuzzy computers and fuzzy controllers The simplest rule of thumb is that if x is A, then y is B. (If x is A, then y is B) It can be expressed by the proposition. Here, "If x
"If A" is called an antecedent, and "y is B" is called a consequent. A and B
If it is ambiguous linguistic information such as "tall", "elderly person", "positive small value", etc., these can be characterized by the membership function as described above. That is, A and B are fuzzy sets (in the description of a specific circuit described later, A and B etc. indicate voltage signals representing a membership function).

 The above proposition is simply expressed as x = A → y = B.

Humans often make inferences that include fuzzy expressions in the antecedent and consequent parts. This type of reasoning cannot be performed satisfactorily using classical Boolean logic.

 Consider the following form of reasoning:

Implication: x = A → y = B Premise: x = A ′ Conclusion: y = B ′ The form of this inference, that is, from the given premises when implication exists Inferring the conclusion is "generalized Modus Ponens (generalized
modus ponens).

There may be a number of implication rules:

Premise: x = A ' conclusion: y = B' Many implications are connective else (or otherwise) or and.

"Fuzzy relation from A to B
A to B) ", and this is represented as R _AB (hereinafter simply abbreviated as R).

Generally _{A = {a 1, a 2} , ..., a i, ..., a m} B = {b 1, b 2, ..., b j, ..., b n} when the fuzzy relation from A to B R is Is represented by

The calculation representing the fuzzy relation will be described later. A,
When B is considered as a membership function, the above equation corresponds to a case where the membership function is sampled and described as a vector.

One implication rule (x = A → y =
B), when premises (x = A ') are given, a "compositional rule of inference" when inferring a conclusion (y = B') from these.
Is expressed as follows using the fuzzy relation R.

b _j = (r _{ij ai} ′) (1) = {(a _i b _j ) a _i ′} (2) Various operations representing a fuzzy relation have been proposed.
See Masaharu Mizumoto and Hans-Jurgen Zimmerm for details
ann, “Comparison of Fuzzy Reasoning Methods,” Fuzzy
Sets and Systems Vol.8, No.3, pp.253-283, (1982)
See

Typical fuzzy relations already proposed include the following.

r _ij = a _i ∧b _j MIN calculation rule r _ij = (a _i ∧b _j ) ∨ (1-a _i ) MAX rule r _ij = 1∧ (1-a _i ∧b _j ) Arithmetic rule The above MIN operation Since the rules are best known and have proven their effectiveness in industrial applications, the MIN operation rules are used in the specific circuit examples described below.
However, it goes without saying that many other arithmetic rules are also applicable.

Various operations have been proposed for the operation of * in the above equation (that is, the operation with). For example, MIN / MAX operation,
Some use an algebraic product / MAX operation. In the specific circuit example described below, the most commonly used MIN / MAX
The operation is used as the operation of *. That is, the MAX operation is adopted as the operation and the MIN operation is adopted as the operation.

Therefore, the conclusion b _j ′ according to the inference synthesis rule is expressed as follows when the MIN / MAX operation is used as the * operation and the MIN operation rule is used as the fuzzy relation.

From the above equation, it can be understood that the fuzzy inference engine or the fuzzy inference synthesizing circuit is mainly configured by using the MIN circuit and the MAX circuit.

Before describing the configuration of the fuzzy computer and the fuzzy controller, the membership function will be described briefly.

Generally, the membership function is often represented by a curve as shown in FIG. 5 (A). However, whether it should be represented by a curve is not essential to the membership function. A more important feature of the membership function is that it takes a continuous value from 0 to 1.

On the other hand, from the viewpoint of circuit design, FIG.
As shown by MF ₁ and MF ₂ , it is easier to handle the membership function by expressing it as a straight broken line, the membership function can be characterized by a small number of parameters, and the design is simpler. Become. Moreover, even if the membership function is represented by a broken line, the above characteristics are not lost.

Basically, a triangular membership function MF ₁ shown by a solid line in FIG. 5B and a trapezoidal membership function MF ₂ shown by a chain line are considered. Membership function MF ₁ triangular is characterized by the value x _L and slope (called a label) of the variable x when the function mu (x) = peak value P (not necessarily the peak value = 1). Membership function MF ₂ trapezoidal is basically characterized by a gradient with variable x _L representing the center of the upper base (also called label).

The variable x of the membership function μ (x) and the variable y of the function μ (y) appearing later are x, y in the above-described inference form.
The same symbols are used as, but are not particularly related to each other. This specification follows the convention of using such symbols.

Where a variable as shown in FIG. 5 (C) (x) is small functions mu (x) takes the value of 1, eventually in some variable x _L functions mu (x) is lowered at a constant gradient 0 Function
There is also a function MF ₃ (this is called a Z-function) and a function MF ₄ (this is called an S-function) that follows the change opposite to this Z-function.
In addition, various forms of membership functions are conceivable.

The membership functions described above may be embodied in various forms. As an example, as shown in FIG. 6, electric signals distributed on a plurality of (for example, 25) signal lines 1 (voltage or current, but here only voltage signals are considered)
Is represented by The variables of the membership function μ (x) take discrete values, and these variables are assigned to each signal line. Signal lines are numbered (1 to 25 in FIG. 6) corresponding to the assigned variables. The plurality of signal lines constitute a kind of bus. Label x _L
Is represented by the number of the signal line where the peak voltage appears.

FIG. 7 is a parallel type fuzzy computer which performs an operation using the membership functions distributed on the bus lines shown in FIG. 6 and which is applied when one implication exists. Shows the concept of Fuzzy computers are
Three membership function generating circuits 11, 12, 13 for respectively outputting membership functions A, A ', B distributed on the bus lines shown in FIG. 6, and output signals of these circuits 11, 12, 13 Is given, and the above-mentioned Modus-Ponens fuzzy inference operation (specifically, for example, (3-1),
(3-2), and a fuzzy inference engine 14 for outputting the inference result B '. The membership function generating circuits 11, 12, and 13 are provided with labels LA, LA ', and LB that specify the membership functions to be output. If it is necessary to obtain a deterministic result from the fuzzy computer, ie a non-fuzzy output, a fuzzy inference engine 14 is followed by a defuzzifier 15.

FIG. 9 shows an example of the configuration of the fuzzy inference engine 14 described above. This performs the operation represented by the equation (3-2). Voltages representing membership functions A and A 'distributed on m signal lines are applied to a C-MIN circuit (correspondence MIN circuit) 21 where a
The MIN operation of _i ∧a _i ′ (i = 1 to m) is performed. C-MI
The N circuit 21 includes m MIN circuits having two inputs and one output. The m output voltages of the C-MIN circuit 21 are input to an E-MAX circuit (ensemble MAX circuit) 22. This E-MAX circuit 22
The output of Represents The E-MAX circuit performs an ensemble MAX operation on m input signals. The output of the E-MAX circuit 22 is used as a truncation input a
Given to 23. On the other hand, the truncation circuit 23 has n
Voltages (b _j , j = 1 to n) representing the fuzzy membership function B distributed on the signal lines are input.
The truncation circuit 23 is a circuit in which one input is all common in the C-MIN circuit. After all, finally the (3-2) operation expression is performed in truncation circuit 23, to obtain a 'result B of the fuzzy inference as a set of' analog voltages distributed on n output lines b _j it can.

FIG. 8 shows the concept of a fuzzy computer of the parallel type which is effective when there are r implications. Three membership function generators 11
There are provided r sets of .about.13 and a fuzzy inference engine 14. Labels LA and LB given to the membership function generating circuit have subscripts 1 to r for each implication.
Is attached. There is no need to provide a membership function generating circuit 12 for each of these sets, and one circuit 12 can be shared by all sets. The connection (else or also) of the implications is realized by the MAX circuit 16. That is, the outputs of all the fuzzy inference engines 14 are supplied to the MAX circuit 16, from which the final inference result B 'is obtained. Of course, concatenation may be performed by an operation other than MAX.

Fuzzy inference engine 14 described above to aid understanding
FIG. 10 schematically shows the inference according to the equation (3-2) as an example of the fuzzy inference executed in the above.
Here, it is assumed that there are a plurality (r) of implementations. Also, a triangular membership function is shown. In equation (3-2), the membership function A,
A'B etc. are represented using the elements a _i , a _i ', b _j etc. of the fuzzy set, but in FIG. 10 the function μ (x) or μ (y) is set with the horizontal axis as a variable x or y. Is represented by

Referring to the upper left graph in FIG. 10, the MIN operation results A1∧A ′ of the membership functions A1 and A ′ are indicated by oblique lines. The maximum value a max1 (truncating input a shown in FIG. 9) of the MIN operation result is obtained. The Fig. 10 top central membership functions B1 are shown, MIN operation result of this function B1 and the maximum value a max1 is indicated by hatching S _1. The hatched portion S ₁ is a inference result for one implication, it is outputted from one fuzzy inference engine 14 or fuzzy inference synthesis circuit 34.

Inferences are made for other implications in a similar manner. The inference results are represented by S ₂ and S _r .

The result B 'of the MAX operation (circuit 16) of these inference results is shown on the right side of FIG. Many techniques have been proposed to defuzzify (defuzzify) the inference result, and one of them is the centroid method, which is the subject of the present invention. According to this method, the center of gravity y _W is determined by y _W = ∫μ (y) ・ dy / ∫μ (y) dy. That is, the y coordinate which divides the area shown by hatching into two right and left is obtained. The thus obtained y _W is output from the defuzzifier 15 as a fixed value.

Both the fuzzy inference engine and the fuzzy inference synthesizing circuit in the fuzzy computer described above perform inference that only one fuzzy proposition exists in the antecedent part of the implication. An inference involving two fuzzy propositions in the subject part may be required. This is called extended fuzzy inference. The antecedent parts of the implication are connected by "and / or".
Either "and" or "or" is selected.

Implication: If x is A and / or y is B, then z is C (If x is A and / or y is B, then z is C) Premise: x is A 'and / or y is Conclusion that is B ' : z is C'.

 This is represented symbolically as follows:

Implication: x = A and / or y = B → z = C premises: x = A ′ and / or y = B ′ Conclusion: z = C ′ Extended fuzzy inference in a parallel type fuzzy computer is based on extended fuzzy Performed by the inference engine. The concept of the extended inference engine is shown in FIG. Inputs are membership functions A, B, C, A 'and B', and a join selection c for selecting a join of "and / or". The output is a membership function C 'representing the result. The membership functions A and A 'are the voltages distributed on m signal lines, B and B' are the voltages distributed on m 'signal lines, and C is the voltage distributed on n signal lines. Respectively represented by

FIG. 12 shows the configuration of the extended inference engine, which can be obtained by slightly modifying the configuration of the basic inference engine shown in FIG. A C-MIN operation is performed between the membership functions A and A '(C-MIN
The circuit 21A) performs an E-MAX operation on the m voltages representing the result (E-MAX circuit 22A). The C-MIN and E-MAX calculations are also performed on the membership functions B and B '(C-MIN circuit 21B and E-MAX circuit 22B). The combination "and (an
In this embodiment, “d)” is calculated by “MIN”
r) ”are each realized by the MAX operation. A controlled MIN-MAX circuit 24 is used so that calculation and selection of this connection can be easily performed. Controlled MIN-M
The AX circuit 24 determines the level (H or L) of the coupling selection input signal c.
Can be switched between the MIN operation function and the MAX operation function in accordance with. The results of the two E-MAX calculations are input to the controlled MIN-MAX circuit 24. And a connection selection input signal c for selecting "and" or "or"
Is provided as a control input of the controlled MIN-MAX circuit 24. Membership function C is a truncation circuit
23, and the output a of the controlled MIN-MAX circuit 24 is provided as a truncating signal. From the truncation circuit 23, the voltage distribution of the fuzzy membership function representing the conclusion C 'is obtained.

Next, the concept of the fuzzy controller will be described.

In general, a controller receives a control amount obtained from a control target and outputs an operation amount to the control target in order to perform desired control. Both the control amount and the operation amount are deterministic values. The fuzzy controller also receives a deterministic value as input, performs fuzzy inference, and outputs a deterministic value. On the other hand, as an example, there is one fuzzy proposition in the antecedent part of the implication. In the above-mentioned fuzzy computer, the input is given by a fuzzy set or membership function A ', and the fuzzy set or membership function is given. The function B ′ (determined value in some cases) is output.

Fuzzy Reasoning in Fuzzy Controller No. 10
One implication (control law) in comparison with the figure
In the case of (there is also one fuzzy proposition in the antecedent part), it is graphically represented as shown in FIG. Relative implications including the membership functions A and B, fuzzy inference result when given definite value x _A is the B 'indicated by hatching. By defuzzifying the inference result, a definite inference result B _W ′ is obtained.

FIG. 14 shows a case where there are two fuzzy propositions in the antecedent part of the implication (control rule).
MIN or MAX of the function values a _A and a _B when the definite values x _A and y _B are given to the two membership functions A and B in the antecedent part of the implication (corresponding to the combination and or or) And the result of the operation a _M and the membership function C
Is the fuzzy inference result (C 'indicated by oblique lines). By defuzzifying the inference result C ', a definite inference result _CW ' is obtained.

Parallel type using fuzzy membership functions distributed on bus lines, applied to fuzzy inference with multiple implications (control rules) and two fuzzy propositions in the antecedent of each implication One configuration example of the fuzzy controller is shown in FIG. This will be described in comparison with FIG. 8 and FIG. 12 showing the fuzzy inference engine.

 The control law is expressed as follows.

Implication: control law 1 x = A1 and / or y = B1 → z = C1 control law 2 x = A2 and / or y = B2 → z = C2 ... control law r x = Ar and / or y = Br → z = Cr premises: x = x _A and / or y = y _B Conclusion: z = C 'The fuzzy inference engine 14 is a fuzzy inference synthesis circuit 14a.
Has been replaced. Since the two inputs is given by definite values x _A, x _B, circuits 11 and 12 or the like for generating a membership function distributed over the bus line is not required, the membership function circuit 31a, 31b is provided in place of it Can be A fuzzy inference synthesis circuit 14a, membership function circuits 31a, 31b, etc. are provided for each control law, and the labels LA, LB of the membership function circuits 31a, 31b are provided with subscripts corresponding to the control law numbers. Have been. Hereinafter, control law 1 will be described as a representative example.

Membership function circuits 31a, 31b are input variables x _A, the membership function values corresponding to _{x B μ A1 (x A)} , and outputs mu _B1 a (y _B). The output of these circuits 31a and 31b is MIN
Or it is given to the MAX circuit 24a. This MIN or MAX circuit
24a corresponds to the controlled MIN-MAX circuit 24, and may be replaced with this circuit 24. The output of the circuit 24a becomes the truncating input a _M1 . On the other hand, the output membership function generator circuit 13 for generating a membership function C1 as a voltage distribution appearing on the bus line (plurality of signal lines) is applied to the truncation circuit 23, MIN operation and a _M1 is carried out , The result of this MIN operation is C ₁ ′.

Similarly, for the (r-1) control rules, C ₂ ′ to C _r ′
Are obtained, the MAX operation result (MAX circuit 16) becomes the fuzzy inference result C ', and the defuzzified result C _W ' is obtained.

(2) Center-of-gravity determining circuit FIG. 16 shows an example in which the center-of-gravity determining circuit according to the present invention is applied to the fuzzy computer shown in FIG. Instead of the membership function generating circuits 11 to 13, grade controllable membership function generating circuits (hereinafter referred to as GC-MFG) 11GC to 13GC are used.
As a specific example of the defuzzifier 15, a center-of-gravity determining circuit including a weighted adding circuit 2 and a simple adding circuit 3 is used. GC-MFG, as described below the specific configuration, in which the voltage of the voltage distribution representing a membership function generated in response to the control voltage V _c applied (grade) is changed. The control voltage V _c is generated by the voltage adjustment circuit 4. Then, the simple output of the adder circuit 3 is always to be 1 (i.e. the (2) equation as the denominator is 1) the control voltage V _c from the voltage adjusting circuit 4 is output, GC-MFG
Given to 11GC-13GC. From the weighted addition circuit 2, a definite value (non-fuzzy output) representing the center of gravity of the inference result is obtained.

Needless to say, this concept can be applied to the fuzzy computers shown in FIGS. 8, 11 and 12.

FIG. 17 shows an example in which the center-of-gravity determining circuit according to the present invention is applied to the fuzzy controller shown in FIG. Here, the MAX circuit 16 is omitted, and only the circuit that processes one implication rule is shown.
It is needless to say that the present invention can also be applied to a fuzzy controller for a plurality of applications including. A grade control circuit 51 for controlling the peak value (grade) of the membership function of the membership function circuits 31a and 31b is provided. As the output control voltage V _c of the voltage adjusting circuit 4 is given to the grade control circuit 51 and GC-MFG 13GC, the output of the simple addition circuit 3 is always 1,
The grades of the membership functions of the membership function circuits 31a and 31b and the GC-MFG 13GC are adjusted. The combination of the grade control circuit 51 and the membership function circuit 31a or 31b is called a grade controllable membership function circuit (GC-MFC).

(3) GC-MFG and GC-MFC Next, specific examples of GC-MFG and GC-MFC will be described.

In FIG. 18, a GC-MFG 73 includes a voltage distribution generating circuit 74 for generating a predetermined voltage distribution on a plurality of signal lines, a switch array 75 for sending out the generated voltage distribution on a predetermined output signal line, and It comprises a decoder 76 which decodes a code representing a given label and controls the switches of the switch array 75. Voltage distribution generator
The shape of the voltage distribution generated from 74 is predetermined, but the position of this voltage distribution on the output signal line is varied by a switch array 75 controlled by the output of decoder 76. Therefore, a voltage distribution representing the membership function corresponding to the given label appears on the output line. Grade voltage distribution generated by the voltage distribution generator circuit 74 (voltage value) is adjusted by the grade control signal V _c.

Some specific examples of GC-MFG will be described below. Here, seven types of membership functions are generated.
Label these membership functions with NL, NM,
NS, ZR, PS, PM and PL. Where N is Negative, P
Is Positive, ZR is zero, L is Large, M is Medium, S is
Each represents Small. It is also assumed that the number of points (corresponding to the number of elements of the fuzzy set) in the variable area of the membership function is limited to 25. Therefore, the membership function generator has 25 output terminals.

FIG. 19 and FIG. 20 show examples of GC-MFG using a switch matrix as a switch array. In FIG. 19, below the output terminals numbered from 0 to 24 of the GC-MFG, seven types of membership functions output from these output terminals are illustrated.

The output value of the fuzzy membership function is quantized into four levels for simplicity. The four levels are _{0, V c1, V c2,} V c3 = V c, the maximum value of the control voltage V _c is, for example, 5V. These four levels of voltages are generated in voltage distribution generating circuit 74A. The circuit 74A comprises three resistors 71 connected in series, the control voltage V _c to the resistance circuit is applied, the voltage at the connection point of the resistor 71 is V _c1, V _c2. Therefore, _{V c1 = V c / 3,} V c2 = 2V c / 3. Five voltage lines VL, which are obliquely drawn in FIG. 19, extend from the voltage distribution generating circuit 74A, and a voltage V
_c3 , the voltage _Vc2 on the lines on both sides, and the outermost 2
Each of the lines is _supplied with a voltage _Vc1 .

The decoder 76A is a 1-of-8 decoder. A 3-bit (c ₁ , c ₂ , c ₃ ) binary signal representing a label is input to the decoder 76A. Decoder 76A outputs an H-level signal to one of eight output terminals according to the code represented by the input signal. The eight output terminals correspond to no designation and the seven types of labels described above. For example, when the input code signal is 000, an H level signal is output to an unspecified output terminal, and when the input code signal is 001, an H level signal is output to an NL output terminal. From these output terminals, signal lines SL indicated by horizontal lines in FIG. 19 extend except for output terminals not specified.

In the switch matrix 75A, an output line OL extends from a predetermined intersection of the voltage line VL and the signal line SL to 25 output terminals. Symbols 75a indicated by small squares at these intersections are provided between the voltage line VL and the output line OL and are turned on and off by the voltage of the signal line SL as shown in FIG. The switch is composed of, for example, a MOS FET. One output line O
Of course, L may be provided with two or more switches 75a. Each output line OL is grounded on its output terminal side via a resistor 75b.

In the above configuration, when a label of a certain membership function is given to the decoder 76A, an H (enable) level signal appears on a signal line SL corresponding to the label, and a switch 75 provided on the signal line is provided.
a turns on. As a result, each voltage of the voltage distribution generating circuit 74A appears at the corresponding output terminal via the output line OL through the switch 75a that is turned on, so that the voltage distribution representing the membership function is output.
The grade of the membership function outputted is varied by a control voltage V _c.

FIGS. 21 and 22 show a GC-MFG using a pass transistor array 75B as a switch array.

Voltage distribution generator circuit 74B, in order to quantize the membership functions at the level of 11, has a voltage dividing circuit consisting of ten series resistors 71, the control voltage V _c is applied to the voltage divider circuit. Ground terminal and the fuzzy truth value voltage to the connection point of the resistors _{0, V c1 = V c /} 10, V c2 = 2V c / 10, ..., V c9 = 9V c / 10, V c10 =
Appears V _c, these fuzzy truth value 0,1 / 10, ..., corresponding respectively to the 9/10 and 1. These voltages V _c1 ~V _c10 is also variable by a control voltage V _c. Also this generation circuit
The 74B has a PROM programmed with the value of the label = ZR membership function. This PROM is provided with a power supply line VL connected to the voltage source and the ground, and an output line OL connected to an output terminal via a pass transistor array 75B. PROM has two layers, upper and lower
An output line OL is formed in a first layer, and a power supply line VL is formed in a second layer. These upper and lower two layers are insulated by an insulating layer such as photosensitive polyimide. By forming through holes at the intersections of these layers, the shape of the membership function is programmed. Since the through-holes can be formed using mask ROM technology, any form of membership function can be programmed. A black circle indicating a node between the line VL and the line OL indicates a through hole. The line VL and the line OL are connected at the point where the through hole is formed,
Fuzzy truth voltage is pass transistor array 75B
Is forwarded to The node between the two lines VL and OL may be short-circuited by field ROM technology, that is, by applying a high voltage to break down the desired intersection.

The pass transistor array 75B outputs the output line OL extending from the voltage distribution generating circuit 74B, the signal line SL connected to the seven output terminals of the decoder 76B, and the voltage at the intersection of these lines to the left or right by four digits or eight. Includes a diagonal line BL for shifting by the digit, a switching element provided at the intersection of the signal line SL with the output line OL and the diagonal line BL, and a PMOS FET 75c controlled by the voltage of the signal line SL. Have been. The manner of connection of the switching element 75c is shown in FIG. The seven signal lines SL connected to the decoder 76B or the columns of the switching elements controlled by those lines are respectively referred to as switch columns S ₁ , S ₂ ,.
And S _7. S _{1 to} S ₇ sometimes refer to signals on these lines SL.

Switch array S ₁ shifts the membership functions programmed in the voltage distribution generator circuit 74B to 4 digits left,
The switch rows S ₃ , S ₄ and S ₆ are shifted four digits to the right, eight digits to the left, and eight digits to the right. Switch array S ₂ and S ₅ is not to shift the programmed membership function to the right or left, directly sends the output terminal thereof. Switch array S ₇ is a switch array, which is grounded, dropping the switch S ₇ is turned on, all the output terminals to the ground level when the other switch S ₁ to S ₆ is turned off.

The relationship between the label of the membership function and the binary level of the signals S ₁ -S ₇ is shown in FIG. decoder
76B is a 3-bit binary signal c ₁ , c ₂ , c ₃ (0
V or +5 V) according to the table shown in FIG.
The binary signals S _{1 to} S ₇ are converted to binary signals S _{1 to} S ₇ (−5 V “L level” or +5 V “H level”). Specifically, as shown in FIG.
It consists of a combination with

For example, the label you entered is in the case of PL, the switch rows S ₃ and S ₆ are turned on. Membership function programmed in the voltage distribution generator circuit 74B is shifted through the switch row S ₃ to 4 digits right, is further shifted to the 8 digit right through the switch row S _6. Thus, the programmed membership function is shifted right by 12 digits, and the membership function appearing at the output terminal is
PL (large positive value).

In FIG. 21, the ground distribution of the voltage distribution generation circuit 74B
The line VL connected to the level is connected to the center 25 output lines OL, and to the left and right, 12 lines each parallel to the output line OL and the oblique line BL are connected. At the intersection with the signal line SL, the switch rows S ₁ and S
₂ , S ₃ , S ₄ and S ₆ are provided. This means that no matter how the programmed membership function is shifted,
This is to ensure that the ground level signal is output to the output terminal.

Pass transistor array 75B must pass the fuzzy truth voltage (0-5V) to the output terminal without attenuating. In a normal PMOS circuit, if the fuzzy truth value voltage is lower than the threshold voltage of the PMOS FET, the PMOS FET has a gate voltage V _G (output of the decoder) of 0.
If it is V, it will not be completely on. To ensure that PMOS FET is fully on, there is a need to a V _G to -5V about. To this end, as described above, the decoder 76B is configured to generate an output that takes -5V (L) and + 5V (H). An example of a NAND gate 77 constituting the decoder of Figure 24 for generating such an output signal S ₁ to S ₇ are shown in FIG. 25.

In the above description, the fuzzy membership functions are shown as chevron or triangular. However, various types of membership functions are conceivable, and it is preferable that a different type can be selected as needed.

FIG. 26 shows a voltage distribution generating circuit mainly applicable to a GC-MFG of the type shown in FIG. 19, wherein a fuzzy membership function type can be selected. The partial pressure is controlled by a control voltage V _c voltage V _c1 ~V _c4
The output line OL is connected to the voltage line VL connected to the node where appears, so as to output a voltage distribution representing a fuzzy membership function form of a mountain or triangle shape.
1 and an output line OL2 connected to output a voltage distribution representing a trapezoidal function form. These lines OL1 and OL2 have switching elements and NMOS
FETs 70A and 70B are connected, and lines OL1 and OL2 are connected to an output line OL connected to an output terminal on the output side of these switching elements. Switching element 70B
The directly by the selection signal c _s, elements 70A inverter 79
Respectively.

When the selection signal c _s is at the L level, the switching element 70
When A is turned on, a voltage representing a chevron or triangular membership function form is output to the output line OL.
Conversely, when the signal _cs is at the H level, the element 70B is turned on, so that a voltage representing a trapezoidal function is output. In this way, it is possible to select the fuzzy membership function form.

In the circuit of Figure 26, if FET 70A, the thread hold value voltage 70B and V _TH (usually about 1V), Bainaryi-level selection signal c _s to control these FET is, L level V
_It suffices if it is below _TH and the H level is above V _TH + 5V. Where 5V
Is the maximum voltage of the control voltage V _c.

As for the distribution form of the generated voltage in the voltage distribution generation circuit, that is, the fuzzy membership function form, not only the above-mentioned two forms, but also three or more forms can be prepared in advance and one of them can be selected. You can also do so. It goes without saying that the selection of the function form is also applicable to the GC-MFG shown in FIG.

The voltage distribution generating circuit generates voltage signals distributed on a plurality of lines. Therefore, it is possible to apply the output voltage of one voltage distribution generating circuit to a plurality of switch arrays 75. FIG. 27 includes one voltage distribution generating circuit 74 and a plurality of switch arrays 75 to which the output voltage is applied.
GC-MFG is shown. Each switch array 75 is driven by a respective decoder 76. Each decoder 76 is provided with a code signal of the same or different label. Therefore, a plurality of voltage distributions representing the same or different membership functions can be obtained from the GC-MFG. Moreover equal and can be controlled simultaneously by grade control voltage V _c of the plurality of membership functions.

Next, a specific example of GC-MFC will be described with reference to FIG. Membership function circuit 31a, since 31b generates a membership function represented by voltages, their labels LA _1, LB ₁ is given by the voltage (V these labels voltages respectively _LA, and V _LB) , the input x _a, y _B also provided with a voltage signal (an input voltage signal, respectively V _x, and Y _y). Membership function circuits 31a, 31b is to output a voltage signal representative of the triangular membership function MF ₁ described above. Since the two membership function circuits 31a and 31b have exactly the same configuration, only one circuit 31a will be described. Since the membership function circuit 31a includes two differential circuits 61 and 62, the operation of these circuits will be described first.
An example will be described with reference to FIGS. 29 and 30.

29, the differential circuit 62 has two transistors Q
₆₁ includes a Q _62, the variable resistor R ₂₂ is connected between the emitters of these transistors. Based one transistor Q ₆₁ (which is the input terminal of the membership function circuit) is supplied with an input voltage V _X, the base of the other transistor Q ₆₂ is given a voltage V _LA representing a label. Current I is applied to both transistors by current source Q ₅₄
It is supplied to the emitter of Q _61, Q _62.

I ₆₁ the current flowing through the transistor Q _61, the transistor Q ₆₂
When the current flowing to the I _62, as shown in Figure 30 (A), when the V _x <V _LA current of the transistor Q ₆₂ I ₆₂ = I flows, no current flows through the transistor Q ₆₁ ( I ₆₁ =
0). When the input voltage V _X is equal to or greater than the label V _LA, the current I ₆₂ of the transistor Q ₆₂ is linearly reduced, the transistor Q ₆₁
The current I ₆₁ flowing through increases linearly from zero. And when it is _{V x = V LA + R 22} I, I 62 = 0, I 61 = I , and the in the region of more large V _x is maintained in this state.

Current mirror CM ₂ is provided, this current mirror is driven by the current I ₆₂ flowing through the transistor Q _62. The output side of the current mirror CM ₂ resistor R _L is connected to the voltage appearing at the resistor R _L and voltage x _2. Since the voltage x ₂ is given by x ₂ = I ₆₂ R _L, the voltage x ₂ is the relative change in the input voltage V _x
It changes as shown by the solid line in FIG. Gradient of the portion where the voltage x ₂ changes linearly is given by -R _L / R _22. Therefore, it is possible to change this gradient by varying the value of resistor R _22.

In FIG. 28, another differential circuit 61 is also a differential circuit 62.
It has the same configuration as. Transistor Q, the transistor Q ₅₁ and the label voltage V _LA input voltage V _x is given is given
When the current flowing through the ₅₂ and I _51, I _52, respectively, these current changes as shown in Figure 30 with respect to the input voltage V _x (C).

Current mirror CM ₁ is driven by the current I ₅₁ flowing through the transistor Q _51. Since the current flows I ₅₁ is connected to the resistor R _L to the output side of the current mirror CM _1, the voltage x ₁ is lowered by the resistor R _L is the x ₁ = I ₅₁ R _L. Graph showing changes in voltage x ₁ with respect to the input voltage V _x is the solid line in Figure 30 (D). Gradient of the portion voltage x ₁ is increases linearly is given by R _L / R _21. Two transistors Q of the resistor R ₂₁ is a differential circuit 61
₅₁ and a resistor connected between the emitters of Q _52, the gradient is changed by changing the value of this resistor R _21.

The membership function circuit 31a includes a two-input MIN circuit. The voltages x ₁ and x ₂ described above are applied to the bases of the transistors Q ₁₁ and Q ₁₂ constituting the MIN circuit. The output voltage V appearing at the emitters of these transistors Q ₁₁ and Q _12
A (mu _A) is a MIN operation result of the voltage x ₁ and x _2, the graph is shown by the solid line in Figure 30 (E). The output voltage V _A is changed to a triangular shape with respect to the input voltage V _X, representing the triangular membership function MF _1. The input voltage corresponding to the peak value is the label voltage _VLA . Also by the resistor R ₂₁ or R _22, as shown by SL _1, SL _2, for example FIG. 5 (B), gradient is changed.

Similarly, from the other membership function circuits 31b,
Under the set label voltage V _LB , an output voltage V _B representing a membership function value (μ _B ) corresponding to the input voltage V _y is obtained.

The MIN circuit 24a (included in the fuzzy inference synthesis circuit 14a, see FIG. 15) includes a wired OR 63 and a current source 64. Then, the output voltages V _A and V _{B of the} membership function circuits 31a and 31b are given to the wired OR 63. The output of the wired OR63 becomes a voltage V _M representing the MIN operation result corresponding to a _M1 (a _M).

More specifically, the membership function circuit 31a
Transistors Q ₁₁ and Q ₁₂ and membership function circuit 31b
Transistors Q ₁₁ and Q ₁₂ , a wired OR 63, and a current source 6
It can be said that the 4 and 4 constitute a 4-input MIN circuit.

Membership function circuit 31a as seen from the graph of Figure 30 (E), the peak value of the membership function in the 31b is determined by IR _L. If the resistance _RL is constant, the current I
Changing the peak value changes.

Grade Control circuit 51 is a circuit for changing the current I in accordance with the control voltage V _c given. The grade control circuit 51 has a current mirror CM ₄ serving as a current source. The current mirror CM ₄ and the transistors Q ₅₃ and Q _{54 serving} as current sources for the membership function circuit 31 a and the current mirror CM _{4 serving} as a current source for the membership function circuit 31 b are provided. transistors Q _53, Q ₅₄ constitute a multi-current mirror. Therefore, the current mirror CM
₄ is equal to the current I flowing through these transistors Q
It will flow to _53, Q _54. Current mirror CM ₄ contains a capacitor C _1. The capacitor C ₁ is a capacitor for phase compensation. Oscillation when the feedback of the output of the voltage adjusting circuit 4 to the input V _c of the grade control circuit 51 as in the FIG. 17 can be prevented by the capacitor C _1.

Driving the current mirror CM ₄ Hamou one current mirror CM _5. Resistor R _o it is connected to the collector of one transistor of the current mirror CM _5. The current I _passes through this resistor _Ro.
By flows, voltage of V _R = IR _o appears.

A current source CS _o for driving the differential circuit 65 to the grade control circuit 51 is provided. Differential circuit 65 whose emitters includes two transistors Q _71, Q ₇₂ are connected by two resistors R _23, R ₂₄ equal value, the connection point of the two resistors to the output side of the current source CS _o It is connected. The base of one transistor Q ₇₁ is given control voltage V _c, the above voltage V _R to the base of the other transistor Q ₇₂
Is given. If with these voltage V _c and V _R equal current flows equal to the transistors Q _71, Q ₇₂ by the current mirror CM ₃ in.

The difference occurs in the current I ₁ and I ₂ flowing through both transistors when the the voltage V _c and V _R unequal. Since the current mirror CM ₃ serves to flow a current equal to the two transistors Q ₇₁ and Q _72, the current difference between the currents I ₁ and I _2, the base of the transistor Q ₇₃ which is connected to the collector of the transistor Q ₇₂ the flow, the emitter current amplification factor β times the current of the difference of the transistor Q ₇₃ flows. Since the emitter of the transistor Q ₇₃ is connected to a current mirror CM ₄ through the Zener diode ZD, the current flowing through the current mirror CM ₄ changes. This current change is manifested as a change of the current I flowing through the resistor R _o, the voltage V _R acts to be equal to the control voltage V _c. Zener diode ZD is for imparting a suitable potential to the emitter of the transistor Q _73, may be alternatively by providing a plurality of transistors.

Current I when the difference between the voltage V _c and V _R [Delta] V, and _{R 23 = R 24 = r e} ,
Voltage V _R is given by the following equation.

_{I = (1 / r e)} · β · ΔV V R = R o · I = (1 / r e) · β · R o · ΔV = (1 / r e) · β · R o (V c -V _{R) Thus, V R = [(1 /} r e) · β · R o / {1+ (1 / r e) · β · R o}] · V c where _{(1 / r e) · β} · R _{If o} >> 1, then V _R = V _c . Therefore, the current I flowing through the resistor R is I = _Vc / _Ro .

As described above, the current I is controlled by a control voltage V _c, the membership function circuit 31a, the peak voltage of 31b is the output voltage of the simple addition circuit 3 is controlled to be 1.

[Brief description of the drawings]

FIG. 1 shows the first embodiment and is a block diagram of a center of gravity determination circuit. FIG. 2 is a graph for explaining fuzzy information and its center of gravity. FIG. 3 is a circuit diagram showing a configuration example of a weighted addition circuit. FIG. 4 is a circuit diagram showing a modification. FIG. 5 to FIG. 30 show a second embodiment. FIG. 5 is a graph showing a membership function. FIG. 5A shows a general shape, FIG. 5B shows a triangular and trapezoidal function, and FIG. 5C shows a Z function and an S function. Each function is shown. FIG. 6 shows a membership function represented by voltages distributed on a plurality of signal lines. FIG. 7 is a block diagram showing the concept of a basic parallel type fuzzy computer, and FIG. 8 is a block diagram showing the concept of the same type of fuzzy computer when a plurality of implications exist. FIG. 9 is a block diagram showing the configuration of a basic parallel type fuzzy inference engine. FIG. 10 is an explanatory diagram schematically showing the process of fuzzy inference. FIG. 11 shows the concept of an extended fuzzy inference engine of the parallel type, and FIG. 12 is a block diagram showing its configuration. FIG. 13 and FIG. 14 are explanatory diagrams of the inference process in the fuzzy controller. FIG. 15 is a block diagram showing a configuration of a parallel type fuzzy controller. FIG. 16 is a block diagram showing an example of a fuzzy computer to which the center of gravity determination circuit is applied. FIG. 17 is a block diagram showing an example of a fuzzy controller to which a center of gravity determination circuit is applied. FIG. 18 is a block diagram showing a basic configuration of a grade controllable membership function circuit. FIG. 19 is a circuit diagram showing a grade controllable membership function generation circuit realized using a switch matrix, and FIG. 20 shows a specific configuration of symbols in FIG. FIG. 21 is a circuit diagram showing a grade controllable membership function generation circuit realized using a pass transistor array. FIG. 22 is a diagram showing a specific configuration of symbols in FIG. 21, and FIG. Is a table showing the operation of the decoder in FIG. 21, FIG. 24 is a circuit diagram showing a specific configuration of the decoder, and FIG. 25 is a circuit diagram showing a NAND gate used in the circuit of FIG. FIG. 26 is a circuit diagram showing a voltage distribution generating circuit capable of selecting a membership function type. FIG. 27 is a block diagram showing a developed form of the grade controllable membership function generating circuit. FIG. 28 is a block diagram showing a specific configuration example of a grade controllable membership function circuit. FIG. 29 is a circuit diagram showing a part of the membership function circuit for explaining the membership function circuit, and FIGS. 30 (A) to (E).
Is a graph showing signals of the same circuit. 2 ... weighted addition circuit, 3 ... simple addition circuit, 4 ... voltage adjustment circuit, 5 ... variable coefficient array, 11GC, 12GC, 13GC ... grade controllable membership function generation circuit, 14 ... fuzzy inference engine, 14a ...... fuzzy inference synthesis circuit, 31a, 31b ...... grade controllable membership function circuit, 51 ...... grade control _{circuit, Q 1, Q 2 ...... MOS} FET.

Claims (4)

(57) [Claims] An electric signal (μ1, μ2,... Μn) representing fuzzy information distributed on a plurality of lines is multiplied by a predetermined value k and multiplied by a value corresponding to the rank of the line. A weighted addition circuit (2,
5) and electric signals (μ1, μ2,...) Representing the fuzzy information.
μn) is multiplied by a predetermined value k and added together, and the simple addition circuit (3, 5); and the predetermined addition so that the output signal of the simple addition circuit (3) represents a value corresponding to 1. And a control means (4, 5, or 4, Q1, Q2) for controlling the value k. 2. The method according to claim 1, wherein the weighted addition circuit and the simple addition circuit include electric signals (μ1, μ1) representing the fuzzy information.
2. A center-of-gravity determining circuit according to claim 1, wherein circuit means (5) for multiplying each of (2,... Μn) by a predetermined value k is shared. 3. An electric signal (μ1, μ2,..., Μ) representing the fuzzy information by adjusting the amplification degree of the addition circuit.
n) multiplied by a predetermined value k (Q1, Q
2. The center-of-gravity determining circuit according to claim 1, further comprising: (2). 4. A membership circuit (11GC, 12GC, 13GC, or 31a, 3a, 3c) for outputting a signal representing a membership function.
1b) is applied to a fuzzy processing device (14 or 14a) for executing a predetermined fuzzy inference based on the output signal and outputting a signal representing an inference result distributed on a plurality of lines, A weighted addition circuit (2) for multiplying each of the signals representing the distributed inference results by a value corresponding to the rank of the line and adding them, and adding a signal representing the inference results distributed on a plurality of lines A simple adding circuit (3), and the membership circuits (11GC, 12GC, 13GC) so that the output signal of the simple adding circuit (3) represents a value corresponding to 1.
Grade control means (4, 11GC, 12GC, 13GC, or 4, 5GC) for controlling the level of the signal output from the GC or 31a, 31b)
1) and a center of gravity determination circuit comprising: