JP2779085B2 - Thin film transistor substrate - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor substrate provided with a thin film MOS transistor used for a liquid crystal display.

[0002]

2. Description of the Related Art The above-mentioned thin film transistor substrate (hereinafter, referred to as a thin film transistor substrate)
This is called a TFT substrate. 3) is known as a liquid crystal display device using ()). In this liquid crystal display device, a thin film MOS transistor T
And a counter substrate 2 on which a counter electrode 3 is formed is disposed to face a TFT substrate on which a pixel electrode 10 is formed, and
It has a structure in which a liquid crystal layer 4 is sandwiched between both substrates 1 and 2. Further, a protective layer 5 is formed on the thin-film MOS transistor T, and an alignment film is formed on each of the substrates 1 and 2 at a portion in contact with the liquid crystal layer 4.

A thin film MOS formed on the TFT substrate
The transistor T and the like are made of a metal oxide,
It is formed by forming a thin film such as a semiconductor. Each thin film is formed by forming a film with a sputtering device or a plasma CVD device, covering only a necessary portion of the film with a resist using a spin coater device, an exposure device, and a developing device sequentially, and then etching the film. This is performed by etching and removing unnecessary film portions not covered with the resist, and thereafter dissolving or peeling the resist to obtain a desired pattern.

FIG. 4 is a schematic plan view of a TFT substrate manufactured by the above-described method. On the glass substrate 1, a plurality of gate bus lines 6 as scanning lines are formed in a horizontal direction.
The source bus line 7 crosses the gate bus line 6
Are formed. A pixel electrode 10 is formed in a region surrounded by the gate bus line 6 and the source bus line 7, and the pixel electrode 10 is a thin film provided near an intersection of the gate bus line 6 and the source bus line 7. It is connected to the drain electrode 8 of the MOS transistor T. Further, outside the gate bus line 6 and the source bus line 7,
Short rings 1 connected to both ends of each bus line 6 and 7
1 is formed. The short ring 11 has a large electrostatic charge on the glass substrate 1 and has a thin film MOS structure.
Since the transistor T and the bus lines 6 and 7 are easily broken by static electricity, the transistor T and the bus lines 6 and 7 are formed so as to prevent static electricity charging and destruction. Note that an insulating layer 9 is formed in places where it is difficult to short-circuit, for example, between the gate bus line 6 and the source bus line 7.

Generally, metals such as Al, Ta, Ti, and Mo are used for the gate bus line 6, the source bus line 7, and the drain electrode 8 as materials of each part. For the insulating layer 9 and the protective layer 5, an oxide film or a nitride film such as SiO ₂ or Si ₃ N ₄ is used, and the picture element electrode 10 and the counter electrode 3 are used.
In many cases, a transparent conductive material such as an ITO film (indium oxide film) is used. As a material of the short ring 11,
Low resistance materials are used for that purpose.

[0006]

By the way, in recent years, the application of liquid crystal display devices to OA equipment and AV equipment has been advanced, and demands for full color, large size, high definition, high contrast and the like have been remarkable. Problems to meet these requirements include improvement in transistor characteristics, increase in effective picture element area (opening ratio), miniaturization of bus lines 6, 7 and the like, and improvement in yield.

However, while each of the above-described problems is being carried out, fine defects such as disconnection and poor connection which occur in the bus lines 6 and 7 and the thin film MOS transistor T which have been miniaturized in response to high definition frequently occur. However, there is a problem that the quality and the yield are reduced.

Many of the above-mentioned fine defects can be relatively easily corrected by a repair technique such as laser currently used, and a problem is how to detect a fine defect portion in a TFT substrate manufacturing process. Is.

That is, in order to detect a fine defect, it is essential to precisely measure the resistance value and the leakage current value of the bus lines 6 and 7 and the like.
The transistor T and the minute bus lines 6 and 7 are easily damaged by static electricity. In addition to the glass substrate 1 having a large electrostatic charge, the bus lines 6 and 7 have a short ring 11 which is a low-resistance wiring. Just before the completion of the display device,
For example, since the rubbing process described below is performed until completion, it is not possible to perform accurate measurement and accurate defect position identification during the manufacture of the TFT substrate.

Therefore, in order to enable the above-described measurement and the like, it is conceivable to use a high-resistance material such as n ⁺ -Si for the short ring 11. However, an alignment film is formed on the TFT substrate and a liquid crystal is formed. When a rubbing process for orientation is performed, a large amount of static electricity is generated due to friction generated during the rubbing process, and therefore, there is a problem that even if measurement and position identification can be performed, complete electrostatic protection measures cannot be secured.

The present invention has been made to solve such a conventional problem, and an object of the present invention is to provide a thin film transistor substrate capable of ensuring not only measurement and position identification, but also a complete electrostatic protection measure. I do.

[0012]

According to the thin film transistor substrate of the present invention, a plurality of scanning lines and a plurality of signal lines are formed on a transparent insulating substrate so as to intersect with each other, and are surrounded by the scanning lines and the signal lines. In a thin film transistor substrate driven by a thin film transistor formed in the vicinity of an intersection between a scanning line and a signal line, a scanning line is provided outside the both ends of each scanning line and each signal line on the substrate. And a short ring is formed apart from all of the signal lines, and a depletion type MOS transistor is formed between the short ring and both ends of the scanning line and the signal line, thereby achieving the above object. can do.

[0013]

According to the present invention, a depletion type MOS transistor is provided between a scanning line and a signal line and a short ring. The depletion type MOS transistor, the scanning line (or signal line) and the insulating film and the n ⁺ -Si layer overlying control gate bus line which is wired between the short ring is formed, the n ⁺ -Si layer Has one end connected to a scanning line (or a signal line) and the other end connected to a short ring. The electrical effect is that a depletion type MOS transistor is used.
Therefore, when no voltage is applied to the control gate bus line, the short ring and the scanning line (or signal line) are in a conductive state due to the conductivity of the n ⁺ -Si layer. Follow
In many manufacturing processes other than inspection
Can be reliably prevented. In addition, antistatic measures
Power supply and connection terminals to apply voltage constantly
Since it is not necessary to take measures, electrostatic countermeasures are facilitated. On the other hand, when a negative voltage is applied to the control gate bus line, a charge is generated along a contact surface with the n ⁺ -Si layer by a dielectric action generated in an insulating layer on the control gate bus line, and the charge causes n ^The depletion layer spreads in the ⁺ -Si layer, and a high resistance state is established between the short ring and the scanning line (or signal line), which is equivalent to a state where the short ring is separated from the scanning line (or signal line). Therefore,
If voltage is applied only at the time of inspection, inspection of the thin film transistor substrate
Can be inspected. Thus, the voltage on the gate
Low resistance when no voltage is applied and when voltage is applied to the gate
The depletion type MOS transistor which becomes high resistance
By using it, the electrostatic couple can be used regardless of the working environment.
Measures and inspections can be performed.

[0014]

Embodiments of the present invention will be described below.

FIG. 1 is a plan view showing a part of a thin film transistor substrate according to this embodiment, and FIG. 2 is a sectional view thereof. FIG.
1A is a sectional view taken along line AA in FIG. 1, FIG. 2B is a sectional view taken along line BB in FIG. 1, and FIG.
It is sectional drawing by a line.

In the TFT substrate, a plurality of gate bus lines 6 as scanning lines which are long in the horizontal direction are formed on a transparent insulating glass substrate 1, and the gate bus lines 6 intersect with the gate bus lines 6 to form a signal which is long in the vertical direction. A plurality of source bus lines 7 are formed as lines. A picture element electrode 10 is formed in a region surrounded by the gate bus line 6 and the source bus line 7, and the thin film MOS transistor T formed near the intersection of the gate bus line 6 and the source bus line 7 includes the picture element electrode 10. It is electrically connected to the elementary electrode 10.

The thin-film MOS transistor T is formed on a gate electrode 6a branched from the gate bus line 6. Specifically, as shown in FIG. 2B, an insulating film 15 is formed to cover the gate electrode 6a, and a semiconductor layer 14 made of amorphous silicon (a-Si) is formed on the insulating film 15. ing. The n ⁺ -Si layers 13 and 13 are formed partially on the semiconductor layer 14,
A drain electrode 16 is formed on one (left side) n ⁺ -Si layer 13, and a source electrode 7 a branched from the source bus line 7 is formed on the other n ⁺ -Si layer 13. . Further, the picture element electrode 10 is formed in connection with the drain electrode 16, and the protective layer 5 is formed on the uppermost layer.

Further, a short ring 11 is formed on the glass substrate 1 outside of both ends of each gate bus line 6 and each source bus line 7 so as to be separated from all the bus lines 6 and 7. Depletion type M between ring 11 and both ends of all bus lines 6 and 7
OS transistor (hereinafter referred to as depletion type FE)
It is called T. ) Is formed.

The above depletion type FET is shown in FIG.
As shown in (a) and (c), the gate bus line 6
(Or the source bus line 7) and the control gate bus line 12 wired between the short ring 11, and the insulating film 15 and the n ⁺ -Si layer 13 which are sequentially formed over the control gate bus line 12. And n ⁺
One end of the Si layer 13 is connected to the gate bus line 6 (or the source bus line 7), and the other end is connected to the short ring 1
1 is connected. The electrical operation of this FET is such that when no voltage is applied to the control gate bus line 12, the short ring 11 and the gate bus line 6
(Or the source bus line 7) is conductive due to the conductivity of the n ⁺ -Si layer 13. On the other hand, when a negative voltage is applied to the control gate bus line 12, charges are generated along the contact surface with the n ⁺ -Si layer 13 due to the dielectric action generated in the insulating layer 15 on the control gate bus line 12, This charge causes a depletion layer to spread in the n ⁺ -Si layer 13, and a high resistance state is established between the short ring 11 and the gate bus line 6 (or the source bus line 7), and the gate bus line 6 (or the source bus line 7)
From the state where the short ring 11 is separated.

Next, a method of manufacturing the thin film transistor substrate having the above configuration will be described.

First, on the glass substrate 1, aluminum constituting the gate electrode 6a and the gate bus line 6 of the thin-film MOS transistor T and the control gate bus line 12 and the short ring 11 of the depletion type FET,
Thickness of metal film such as tantalum, molybdenum, chromium, etc.
A film is formed with a thickness of about 0.4 μm by a sputtering apparatus. afterwards,
The resist is applied by a spin coater, the pattern of the gate bus line is exposed by an exposing machine, developed by a developing device, and the resist is left on the pattern portion. Subsequently, unnecessary portions are removed by etching with an etching device, and the resist is removed with a peeling device. Thus, the gate electrode 6a and the gate bus line 6 of the thin-film MOS transistor T, and the control gate bus line 12 and the short ring 11 of the depletion type FET are formed. In this embodiment, aluminum is used for each of the gate bus lines 6 and 12.

Next, an insulating film such as a silicon nitride film is formed to a thickness of 0.3 to 0.5 μm by a plasma CVD apparatus, and then resist application, exposure, development and etching are sequentially performed to pattern unnecessary portions. Then, the control gate bus line 12 of the depletion type FET is covered with an insulating film 15.

Next, in order to form the thin-film MOS transistor T, the semiconductor layer 14, the n ⁺ -Si layer 13, and the like are formed by repeating film formation and patterning. Depletion type FE
For the T portion, the semiconductor layer 14 is removed, the n ⁺ -Si layer 13 is formed with a thickness of 50 to 80 nm, and is patterned so that the bus lines 6 and 7 and the short ring 11 can be connected as shown in FIG. leave.

Subsequently, the source electrode 7a, the source bus line 7, and the drain electrode 16 of the thin-film MOS transistor T
The source electrode 7a, the source bus line 7, and the drain electrode 16 are formed by depositing and patterning a metal film such as molybdenum, titanium, tungsten, or the like constituting the above by a sputtering apparatus.

Next, an ITO film is formed by patterning, the picture element electrode 10 is formed so as to be connected to the drain electrode 16, and finally, the protective film 5 is formed by film formation and patterning. Is completed.

The TFT substrate thus manufactured is
As described above, the depletion type FET is provided between the gate bus line 6 (or the source bus line 7) and the short ring 11, and when no voltage is applied to the control gate bus line 12, the short ring 11 and the gate bus line 6 (or the source bus line 7) and the control gate bus line 12
When a negative voltage is applied to the short ring 11 from the gate bus line 6 (or the source bus line 7).
Is equal to the state of being disconnected.

Therefore, only at the time of inspection, a voltage is applied to the control gate bus line 12 to disconnect the short ring 11 from the bus lines 6 and 7, and precise measurement and defect detection of the bus lines 6, 7 and the thin film MOS transistor T are performed. . When the voltage application is stopped, the short ring 11 returns to a state where the bus lines 6, 7 and the like are short-circuited.

Next, the effect of the short ring having such a configuration will be described.

In this embodiment, the distance between the gate bus line 6 and the source bus line 7 and the short ring 11 and the control gate bus line 1 of the depletion type FET are set.
2 and the width of the n ⁺ -Si layer 13 were set and processed as shown in Table 1.

[0030]

[Table 1]

Table 2 shows the results obtained in the case of the present embodiment. The resistance between each bus line 6 and 7 and the short ring 11 according to the voltage applied to the control gate bus line of the depletion type FET is shown. Show.

[0032]

[Table 2]

On the other hand, Table 3 shows the resistance value between each bus line and the short ring in the prior art.

[0034]

[Table 3]

As can be understood from Tables 1 to 3, in the case of the short ring used in the present embodiment, the resistance value in the normal state where no voltage is applied is much lower than in the conventional case, and the resistance to destruction due to static electricity is small. The effect is greater. Further, when a voltage is applied, a value equal to or higher than the conventional high resistance value is obtained.

Further, Table 4 shows the yield by the correction on the TFT substrate by the defect detection according to the present embodiment and the yield by the conventional technique.

[0037]

[Table 4]

As can be understood from Table 4, in the case of this embodiment, the effect of the short ring for protection against electrostatic breakdown and the effect of the measurement and defect inspection can be reduced, and the defect correction on the TFT substrate can be easily performed. In this way, the yield can be greatly improved, and it has high technical and industrial value.

[0039]

As described above, the present invention provides a depletion type FET between a scanning line and a signal line and a short ring.
Is provided, the effect of the short ring for protection against electrostatic destruction and the reduction in the effect of measurement and defect inspection can be achieved.
Defect correction on the FT substrate can be facilitated, and the yield can be greatly improved. That is, a depletion type MOS transistor
The use of a static
Measures and inspections can be performed. Also depletion
Thin-film transistor
Apply voltage only during inspection without changing the configuration of the
Can be inspected if added, and many other manufacturing processes
Now, a power supply and connection terminals for constantly applying voltage are provided.
It is not necessary to take measures against static electricity.
You.

[Brief description of the drawings]

FIG. 1 is a plan view showing a thin film transistor substrate of the present invention.

FIG. 2 is a sectional view showing each part of the thin film transistor substrate of FIG. 1;

FIG. 3 is a cross-sectional view showing a conventional liquid crystal display device using a thin film transistor substrate.

FIG. 4 is a plan view showing a conventional thin film transistor substrate.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Glass substrate 6 Gate bus line 7 Source bus line 10 Pixel electrode T Thin-film MOS transistor 11 Short ring

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G02F 1/136 G02F 1/13 101 G09F 9/00-9/30

Claims (1)

(57) [Claims] A plurality of scanning lines and a plurality of signal lines are formed on a transparent insulating substrate so as to intersect with each other, and a pixel electrode provided in a region surrounded by the scanning lines and the signal lines includes a plurality of scanning lines and a plurality of signal lines. In a thin film transistor substrate driven by a thin film transistor formed near an intersection with a signal line, outside of both ends of each scanning line and each signal line on the substrate,
A thin film transistor substrate in which a short ring is formed apart from all of the scanning lines and the signal lines, and a depletion type MOS transistor is formed between the short ring and both ends of the scanning lines and the signal lines.