JPH05181157A - Thin film transistor substrate - Google Patents

Abstract

PURPOSE:To ensure perfect protection from static electricity as well as measurement and positioning. CONSTITUTION:A depression type MOS transistor is disposed between a short ring 11 and gate bus lines 6 as scanning lines and between the ring 11 and source bus lines 7 as signal lines. This transistor has a structure in which an insulating film and an n<+>-Si layer have been formed so as to cover a control gate bus line 12 laid between the lines 6 or 7 and the ring 11, one end of the Si layer has been connected to the lines 6 or 7 and the other end to the ring 11.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor substrate having a thin film MOS transistor used in a liquid crystal display device.

[0002]

2. Description of the Related Art The above-mentioned thin film transistor substrate (hereinafter,
This is called a TFT substrate. 3 is known as a liquid crystal display device using (1). This liquid crystal display device has a thin film MOS transistor T on the surface of a glass substrate 1.
And the counter substrate 2 on which the counter electrode 3 is formed so as to face the TFT substrate on which the pixel electrode 10 is formed,
The liquid crystal layer 4 is sandwiched between the substrates 1 and 2. Further, a protective layer 5 is formed on the thin film MOS transistor T, and an alignment film is formed on each of the substrates 1 and 2 in contact with the liquid crystal layer 4.

Thin film MOS formed on the TFT substrate
The transistor T and the like are formed on the glass substrate 1 with a metal oxide,
It is configured by forming a thin film such as a semiconductor. To form each thin film, a film is generated by a sputtering device or a plasma CVD device, and only a required portion of the film is covered with a resist by sequentially using a spin coater device, an exposure device and a developing device, and then an etching device. The unnecessary film portion not covered with the resist is removed by etching, and then the resist is dissolved or peeled to obtain a desired pattern.

FIG. 4 shows a schematic plan view of a TFT substrate manufactured by the above method. A plurality of gate bus lines 6 as scanning lines are formed in the horizontal direction on the glass substrate 1,
The source bus line 7 intersects with the gate bus line 6
Are formed in plural. A pixel electrode 10 is formed in a region surrounded by the gate bus line 6 and the source bus line 7, and the pixel electrode 10 is a thin film provided near the intersection of the gate bus line 6 and the source bus line 7. It is connected to the drain electrode 8 of the MOS transistor T. Further, outside the gate bus line 6 and the source bus line 7,
Short ring 1 connected to both ends of each bus line 6 and 7.
1 is formed. The short ring 11 has a large amount of static electricity on the glass substrate 1 and is thin film MOS.
Since the transistor T and the bus lines 6 and 7 are easily damaged by static electricity, they are formed to prevent electrostatic charge and damage, and are left until just before the completion of manufacturing of the liquid crystal display device in which electrostatic charge and damage are less likely to occur. An insulating layer 9 is formed at a place where it is difficult to short-circuit, for example, between the gate bus line 6 and the source bus line 7.

As a material for each portion, generally, metal such as Al, Ta, Ti, Mo is used for the gate bus line 6, the source bus line 7 and the drain electrode 8. For the insulating layer 9 and the protective layer 5, an oxide film or a nitride film such as SiO ₂ or Si ₃ N ₄ is used, and the pixel electrode 10 and the counter electrode 3 are used.
For this, a transparent conductive material such as an ITO film (indium oxide film) is often used. As a material of the short ring 11,
A low resistance material is used for that purpose.

[0006]

By the way, in recent years, liquid crystal display devices have been increasingly applied to OA equipment and AV equipment, and there has been a great demand for full color, large size, high definition, and high contrast. Challenges to these requirements include improvement of transistor characteristics, increase of effective pixel area (aperture ratio), miniaturization of bus lines 6 and 7 and improvement of yield.

However, while each of the above-mentioned problems can be achieved, fine defects such as disconnection and connection failure frequently occur in the bus lines 6 and 7 and the thin film MOS transistor T which have been miniaturized for high definition. However, there is a problem that the quality and the yield decrease.

Many of the above-mentioned fine defects can be relatively easily corrected by a correction technique such as a laser which is currently used. The problem is how to detect the fine defect portion during the manufacturing process of the TFT substrate. It is.

That is, precise detection of resistance values and leakage current values of the bus lines 6, 7 and the like is indispensable for detecting fine defects, but as described above, thin film MOS formed on the substrate 1 is used.
The transistor T and the fine bus lines 6 and 7 are easily broken by static electricity, and the glass substrate 1 is highly charged with static electricity. In addition, the bus lines 6 and 7 are provided with a short ring 11 which is a low resistance wiring. Just before the completion of the display device,
For example, since the rubbing process described below is performed until it is completed, it is not possible to perform precise measurement and accurate defect position identification during the manufacture of the TFT substrate.

Therefore, it is possible to use a high resistance material such as n ⁺ -Si for the short ring 11 in order to enable the above-mentioned measurement, but an alignment film is formed on the manufactured TFT substrate and a liquid crystal is formed. When the rubbing treatment for orientation is performed, a large amount of static electricity is generated due to friction generated during the rubbing treatment, so that there is a problem in that a complete electrostatic protection measure cannot be secured even though measurement and position identification can be performed.

The present invention has been made to solve such conventional problems, and an object of the present invention is to provide a thin film transistor substrate capable of ensuring not only measurement and position identification but also complete electrostatic protection measures. To do.

[0012]

A thin film transistor substrate according to the present invention has a region formed by a plurality of scanning lines and a plurality of signal lines intersecting each other on a transparent insulating substrate and surrounded by the scanning lines and the signal lines. In the thin film transistor substrate in which the pixel electrode provided on the substrate is driven by the thin film transistor formed in the vicinity of the intersection of the scanning line and the signal line, the scanning line is provided outside each end of each scanning line and each signal line on the substrate. And a short ring is formed apart from all of the signal lines, and a depletion type MOS transistor is formed between the short ring and both ends of the scanning line and the signal line, thereby achieving the above object. can do.

[0013]

In the present invention, the depletion type MOS transistor is provided between the scanning line and the signal line and the short ring. The depletion type MOS transistor, the scanning line (or signal line) and the insulating film and the n ⁺ -Si layer overlying control gate bus line which is wired between the short ring is formed, the n ⁺ -Si layer Has a structure in which one end side is connected to a scanning line (or a signal line) and the other end side is connected to a short ring. As an electrical action, when no voltage is applied to the control gate bus line, the short ring and the scanning line (or signal line) are in a conductive state due to the conductivity of the n ⁺ -Si layer. On the other hand, when a negative voltage is applied to the control gate bus line, an electric charge is generated along the contact surface with the n ⁺ -Si layer by the dielectric action generated in the insulating layer on the control gate bus line, and the electric charge causes n ^A depletion layer spreads on the ⁺ -Si layer, and a high resistance state is established between the short ring and the scanning line (or signal line), which is equal to a state in which the short ring is separated from the scanning line (or signal line).

[0014]

EXAMPLES Examples of the present invention will be described below.

FIG. 1 is a plan view showing a part of the thin film transistor substrate of this embodiment, and FIG. 2 is a sectional view thereof. Figure 2
1A is a sectional view taken along the line AA in FIG. 1, FIG. 1B is a sectional view taken along the line BB in FIG. 1, and FIG.
It is sectional drawing by a line.

In this TFT substrate, a plurality of gate bus lines 6 as horizontal scanning lines are formed on a transparent insulating glass substrate 1, and a signal long in the vertical direction intersects with the gate bus lines 6. A plurality of source bus lines 7 as lines are formed. A pixel electrode 10 is formed in a region surrounded by the gate bus line 6 and the source bus line 7, and the thin film MOS transistor T formed near the intersection of the gate bus line 6 and the source bus line 7 is formed in the above-mentioned picture. It is electrically connected to the element electrode 10.

The thin film MOS transistor T is formed on the gate electrode 6a branched from the gate bus line 6. Specifically, as shown in FIG. 2B, the insulating film 15 is formed so as to cover the gate electrode 6a, and the semiconductor layer 14 made of amorphous silicon (a-Si) is formed on the insulating film 15. ing. Part of the semiconductor layer 14 is placed on the semiconductor layer 14 to form n ⁺ -Si layers 13 and 13,
A drain electrode 16 is formed on one (left side of the figure) n ⁺ -Si layer 13, and a source electrode 7a branched from the source bus line 7 is formed on the other n ⁺ -Si layer 13. .. Further, the pixel electrode 10 is formed in connection with the drain electrode 16, and the protective layer 5 is formed on the uppermost layer.

Further, on the glass substrate 1, short-circuit rings 11 are formed outside both ends of each gate bus line 6 and each source bus line 7 so as to be separated from all the bus lines 6 and 7, and this short circuit is formed. Depletion type M between the ring 11 and both ends of all bus lines 6 and 7.
OS transistor (hereinafter referred to as depletion type FE
T. ) Has been formed.

The depletion type FET is shown in FIG.
As shown in (a) and (c), the gate bus line 6
(Or the source bus line 7) and the control gate bus line 12 wired between the short ring 11, and the insulating film 15 and the n ⁺ -Si layer 13 which are formed in sequence so as to cover the control gate bus line 12. Becomes n ⁺
-One end of the Si layer 13 is connected to the gate bus line 6 (or the source bus line 7), and the other end is connected to the short ring 1
It has a structure connected to 1. The electrical operation of this FET is such that when no voltage is applied to the control gate bus line 12, the short ring 11 and the gate bus line 6
(Or the source bus line 7) is in a conductive state due to the conductivity of the n ⁺ -Si layer 13. On the other hand, when a negative voltage is applied to the control gate bus line 12, an electric charge is generated along the contact surface with the n ⁺ -Si layer 13 by the dielectric action generated in the insulating layer 15 on the control gate bus line 12, A depletion layer spreads in the n ⁺ -Si layer 13 by this charge, and a high resistance state is established between the short ring 11 and the gate bus line 6 (or the source bus line 7), and the gate bus line 6 (or the source bus line 7).
Is equivalent to the state where the short ring 11 is separated from.

Next, a method of manufacturing the thin film transistor substrate having the above structure will be described.

First, on the glass substrate 1, the gate electrode 6a of the thin film MOS transistor T and the gate bus line 6, and the aluminum forming the control gate bus line 12 and the short ring 11 of the depletion type FET,
A metal film of tantalum, molybdenum, chromium, etc. with a thickness of 0.3
A film is formed with a sputtering device at a thickness of 0.4 μm. afterwards,
The resist is applied by a spin coater device, the pattern of the gate bus line is exposed by an exposure device and developed by a developing device, and the resist is left on the pattern portion. Subsequently, an unnecessary portion is removed by etching with an etching device, and the resist is removed with a peeling device. As a result, the gate electrode 6a and the gate bus line 6 of the thin film MOS transistor T, and the control gate bus line 12 and the short ring 11 of the depletion type FET are formed. In this embodiment, aluminum is used for the gate bus lines 6 and 12.

Next, an insulating film such as a silicon nitride film is formed to a thickness of 0.3 to 0.5 μm by a plasma CVD apparatus, and then resist coating, exposure, development and etching are sequentially performed to pattern unnecessary portions. Then, the control gate bus line 12 of the depletion type FET is covered with an insulating film 15.

Next, in order to form the thin film MOS transistor T, the semiconductor layer 14, the n ⁺ -Si layer 13 and the like are formed by repeating film formation and patterning. Depletion type FE
Regarding the T portion, the semiconductor layer 14 is removed, an n ⁺ -Si layer 13 is formed with a thickness of 50 to 80 nm, and patterned so that the bus lines 6 and 7 and the short ring 11 can be connected as shown in FIG. leave.

Next, the source electrode 7a, the source bus line 7 and the drain electrode 16 of the thin film MOS transistor T.
A metal film of molybdenum, titanium, tungsten, or the like forming the above is formed by a sputtering apparatus and patterned to form the source electrode 7a, the source bus line 7, and the drain electrode 16.

Next, an ITO film is formed and patterned to form the pixel electrode 10 in a state of being connected to the drain electrode 16. Finally, a protective film 5 is formed and patterned to form a TFT substrate. Is completed.

The TFT substrate manufactured in this way is
As described above, the depletion type FET is provided between the gate bus line 6 (or the source bus line 7) and the short ring 11, and when the voltage is not applied to the control gate bus line 12, the short ring 11 and the gate bus line. 6 (or the source bus line 7) becomes conductive, while the control gate bus line 12
When a negative voltage is applied to the gate bus line 6 (or source bus line 7), the short ring 11
Is equivalent to the disconnected state.

Therefore, the voltage is applied to the control gate bus line 12 only at the time of inspection to disconnect the short ring 11 from the bus lines 6 and 7, and the precise measurement and defect detection of the bus lines 6 and 7 and the thin film MOS transistor T are performed. .. When the voltage application is stopped, the short ring 11 returns to a state where the bus lines 6, 7 and the like are short-circuited.

Next, the effect of the short ring having such a structure will be described.

In this embodiment, the distance between the gate bus line 6 and the source bus line 7 and the short ring 11, the control gate bus line 1 of the depletion type FET.
The width of 2 and the width of the n ⁺ -Si layer 13 were set and processed as shown in Table 1.

[0030]

[Table 1]

Table 2 shows the results obtained in the case of this embodiment, and shows the resistance value between each bus line 6 and 7 and the short ring 11 depending on the voltage applied to the control gate bus line of the depletion type FET. Show.

[0032]

[Table 2]

On the other hand, Table 3 shows the resistance value between each bus line and the short ring in the prior art.

[0034]

[Table 3]

As can be seen from Tables 1 to 3, in the case of the short ring used in this embodiment, the resistance value is remarkably lower than that of the conventional one in the normal state in which no voltage is applied, and the short ring is resistant to breakdown by static electricity. The effect increases. Further, when a voltage is applied, a value equal to or higher than the conventional high resistance value can be obtained.

Further, Table 4 shows the yield due to the correction in the TFT substrate by the defect detection according to the present embodiment and the yield according to the prior art.

[0037]

[Table 4]

As can be seen from Table 4, in the case of this embodiment, the effect of the short ring for electrostatic breakdown protection and the effect of the measurement / defect inspection can be reduced, and the defect repair on the TFT substrate can be facilitated. In addition, the yield can be greatly improved, and it is of high value technically and industrially.

[0039]

As described above, according to the present invention, the depletion type FET is provided between the scanning line and the signal line and the short ring.
Is provided, the effect of the short ring for electrostatic breakdown protection and the effect of measurement and defect inspection can be reduced.
Defects on the FT substrate can be easily corrected and the yield can be greatly improved.

[Brief description of drawings]

FIG. 1 is a plan view showing a thin film transistor substrate of the present invention.

FIG. 2 is a cross-sectional view showing each part of the thin film transistor substrate of FIG.

FIG. 3 is a sectional view showing a liquid crystal display device using a conventional thin film transistor substrate.

FIG. 4 is a plan view showing a conventional thin film transistor substrate.

[Explanation of symbols]

 1 glass substrate 6 gate bus line 7 source bus line 10 pixel electrode T thin film MOS transistor 11 short ring

Claims (1)

[Claims] 1. A plurality of scanning lines and a plurality of signal lines are formed so as to intersect with each other on a transparent insulating substrate, and a pixel electrode provided in a region surrounded by the scanning lines and the signal lines is a scanning line. In a thin film transistor substrate driven by a thin film transistor formed near an intersection with a signal line, outside each end of each scanning line and each signal line on the substrate,
A thin film transistor substrate in which a short ring is formed apart from all of the scanning lines and the signal lines, and depletion type MOS transistors are formed between the short ring and all ends of the scanning lines and the signal lines.