JP2772495B2 - Capacity measuring device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a capacitance measuring device used for simultaneously measuring respective capacitances between a plurality of electrodes and one common electrode.

[0002]

2. Description of the Related Art As one method of evaluating a process of a semiconductor having a MIS structure, an evaluation method based on CV measurement is used. In the conventional CV measurement, it was necessary to form electrodes for electrical measurement on the surface of an oxide film on a semiconductor substrate. However, the process of forming electrodes only affects the electrical characteristics of the semiconductor wafer itself. No. There is a problem that it takes time and effort to form the electrode itself. . Accordingly, the present applicant has developed a semiconductor wafer electric measurement device capable of performing electric characteristic evaluation such as CV measurement and Ct method without forming electrodes on the surface of the semiconductor wafer. FIG. 1 is a conceptual diagram showing an outline of a semiconductor electric measurement device developed by the present applicant. 1A, an oxide film 102 is formed on a front surface of a semiconductor substrate 101, and an electrode 202 is formed on a back surface. Oxide film 1
Above the measuring electrode 20 with a gap Ge therebetween.
1 is held by the electrode holding unit 300.
The gap Ge between the oxide film 102 and the measurement electrode 201 is
As will be described later, the thickness is controlled by the electrode holding unit 300 so as to be about 1 μm or less.

The capacitance Ct between the two electrodes 201 and 202 is, as shown in FIG. 1B, a capacitance Cs of the semiconductor substrate 101, a capacitance Ci of the oxide film 102, a gap Ge. In series with the capacitance Cg. C
The -V curve shows the capacitance Cs of the semiconductor substrate 101 and the oxide film 1
12 shows the voltage dependence of the combined capacitance Cta with the capacitance Ci of No. 02. The value of the gap Ge is accurately measured by the electrode holding unit 300, and the capacitance Cg of the gap is calculated based on the value of the gap Ge. The combined capacitance Ct is measured by the measuring section 400, and the combined capacitance Ct
The CV curve is determined by calculating the capacitance Cta by subtracting the capacitance Cg of the gap from.

By the way, when electric measurement of a semiconductor is performed by using the above-mentioned apparatus, if the distance between the measurement electrode 201 and the surface of the semiconductor wafer is not parallel, the value of the capacitance Cg of the gap Ge is based on the gap Ge. It deviates from the calculated value, which is not desirable for accurate electrical measurement. Therefore, it is desirable that the electric measurement device be provided with a device for accurately adjusting the parallelism between the measurement electrode (or the holding surface) and the semiconductor wafer surface.

Therefore, the applicant of the present invention has provided a plurality of parallelism adjusting electrodes on an electrode holding surface for holding a measuring electrode, and has set the electrodes so that the capacitance between each parallelism adjusting electrode and the semiconductor wafer is equal to each other. A method has been developed to adjust the parallelism between the holding surface and the semiconductor wafer by adjusting the tilt between them.

[0006]

Generally, a measuring device for a capacity uses a bridge. However, when trying to measure the capacitance between a plurality of parallelism adjusting electrodes and the semiconductor wafer using a bridge, the terminals connected to the semiconductor wafer (the terminals connected to the electrodes 202 in the example of FIG. 1) are Since it is commonly used for the bridge of the parallelism adjusting electrodes, there is a problem that the measured values of the capacitances of the respective parallelism adjusting electrodes affect each other. This problem is a problem common in the case of measuring the capacitance values between the plurality of electrodes and one common electrode at the same time, the measurement object is a semiconductor weather
This was a problem that also occurred in cases other than c . SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem, and has the effect of changing the capacitance values (or measured values depending on the capacitance values) between a plurality of electrodes and one common electrode to each other's measured values. It is an object of the present invention to provide a capacity measuring device that can be obtained without being performed.

[0007]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, a capacity measuring apparatus according to the present invention is a capacity measuring apparatus for obtaining a measured value dependent on a capacity value of a measured capacity of an object to be measured. A first input terminal to which one electrode is connected to the other electrode of the capacitor to be measured, the second input terminal to which a power signal having a sine waveform is input;
A resistor element interposed between the first and second input terminals, and a power supply input to the second input terminal in a predetermined phase section of a measurement signal appearing at the first input terminal. and a product fraction means asking you to measurement value dependent on the capacitance value of the capacitance to be measured by signal products min.

[0008]

[Function] One of the capacitors to be measured is connected to the ground side,
Measurement can be performed in a mode in which the other is connected to the first input terminal (so-called single-ended mode). Therefore, when measuring the measurement values depending on the capacitance values of a plurality of capacitances to be measured, if the ground side terminal of the capacitances to be measured is a common electrode, the measurement is performed without being affected by the mutual measurement values. be able to. Further, since the detection and integration means obtains a measured value corresponding to the capacitance value by integrating the power supply signal in a predetermined phase section of the measured signal, the measured value is accurately obtained without being affected by the noise component of the measured signal. be able to.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 2 is a diagram showing a configuration of an electric measurement device MD as an embodiment of the present invention. The electric measurement device MD includes a sample table 7 on which the semiconductor wafer 100 is mounted, and a mount 3 having a trapezoidal cross section installed above the sample table 7.

An optical system comprising a laser oscillator 5, a prism 41, and a light receiving sensor 6 is installed on the gantry 3. The two slopes at the bottom of the gantry 3 are formed so that the angle between them is 90 °, and a prism 41 is fixed to the bottom of the gantry 3. A laser oscillator 5 such as a GaAlAs laser is fixed to one end of the slope of the gantry 3, and a light receiving sensor 6 such as a photodiode is fixed to the end of the other slope.

When electric measurement of the semiconductor wafer 100 is performed, the gap between the bottom surface 41a of the prism and the surface of the semiconductor wafer 100 is maintained at about 1 μm or less. The optical system including the laser oscillator 5, the prism 41, and the light receiving sensor 6 is an optical measurement system for accurately measuring the gap. This optical measurement system utilizes the tunneling phenomenon of laser light when the laser light emitted from the laser oscillator 5 is reflected on the bottom surface 41a of the prism 41 under geometric total reflection conditions. The value of the gap is measured based on the light amount measured by the light amount measuring device 12.
However, the details are omitted here.

The prism 41 is made of borosilicate glass (B
K7), on the bottom surface 41a of which are formed a measuring electrode 201 and parallelism adjusting electrodes 111 to 113 to be described later. Also, the bottom surface 41a of the prism 41
Is set substantially parallel to a plane (xy plane) parallel to the surface of the sample stage 7 on which the semiconductor wafer 100 is mounted. The prism 41 is formed so that its incident surface 41b and its outgoing surface 41c are at 90 ° to each other, and the angle between these surfaces 41b and 41c and the bottom surface 41a is 45 °. Below the prism 41, the semiconductor wafer 100 is held on the sample table 7 via a minute gap, and the surface of the semiconductor wafer 100 is set so as to be substantially parallel to the bottom surface 41a of the prism 41.

The sample stage 7 is supported by three piezoelectric actuators 21 to 23 erected on an xy table 31. The xy table 31 is driven by an x-axis drive motor 32x and a y-axis drive motor 32y, and moves on an xy plane. The xy table 31 is supported by a vertical column 34 erected on a base 33, and is driven by a z-axis drive motor 32z to move in the z-axis direction. A position controller 11 is connected to the piezoelectric actuators 21 to 23, a light amount measuring device 12 is connected to the light receiving sensor 6, and an LCR meter 13 is connected to each electrode on the bottom surface 41 a of the prism 41 and the metal sample table 7. Is connected. The LCR meter 13 is a device that measures the capacitance and conductance between each electrode and the sample table 7.

Position control device 11, light quantity measuring device 12, LC
The R meter 13 is connected to a host controller 14, which controls the entire measuring device and processes the obtained data. As the host controller 14, for example, a personal computer is used. The sample stage 7 is prism 41
, The sample stage 7 is first raised by the z-axis drive motor 32z, and once stopped when the surface of the sample stage 7 reaches the height of the initial position sensor 35. After that, the height of the sample stage 7 is finely adjusted using the piezoelectric actuators 21 to 23. The piezoelectric actuators 21 and 2
3 and the motors 32z, 32y, 32z are all controlled by the position control device 11.

FIG. 3 is a diagram showing a bottom surface 41a of the prism 41 of the electric measuring device MD. An electrode 201 for electric measurement and three electrodes 111 to 113 for adjusting parallelism are formed on the bottom surface 41 a of the prism 41. Also,
The conductor 201 is connected to the electrodes 201, 111 to 113, respectively.
a, 111a to 113a are connected. The piezoelectric actuators 21 to 23 are installed at positions outside the center of each of the electrodes 111 to 113, respectively, as indicated by broken lines in FIG. These piezoelectric actuators 21 to 23
Are driven independently of each other by the position control device 11,
As a result, the parallelism between the surface of the semiconductor wafer 100 placed on the sample table 7 and the surface of the measurement electrode 201 is adjusted.

Each of the parallelism adjusting electrodes 111 to 113 has an equally divided ring shape. Each of these electrodes may have a circular shape. However, if the electrodes are divided into ring shapes as shown in FIG. 3, there is an advantage that an electrode having a larger area can be formed in a smaller region.

The bottom surface 41a of the prism 41 corresponds to the electrode holding surface in the present invention. Further, the parallelism adjusting means according to the present invention comprises three piezoelectric actuators 2.
1 to 23, the position control device 11, and the LCR meter 13
And the host controller 14. FIG.
The electrode holding unit 300 is realized by the piezoelectric actuators 21 to 23, the gantry 3, the prism 41, the laser oscillator 5, the light receiving sensor 6, the position control device 11, the light quantity measuring device 12, and the host controller 14. Have been.

B. FIG. 4 is a schematic diagram showing an equivalent circuit including the parallelism adjusting electrodes 111 to 113, the measuring electrode 201, and the semiconductor wafer 100. FIG. 4A shows a parallelism adjusting electrode 1.
The equivalent circuit between the semiconductor wafer 100 (indicated by the letter W in the figure) and the semiconductor wafer 100 (indicated by the letters S, T, U in the figure) is shown. Since the distance between the parallelism adjusting electrodes 111 to 113 and the semiconductor wafer 100 is adjusted to be very short (to about 1 μm or less),
Each of the electrodes 111 to 113 and the semiconductor wafer 100 can be considered to be coupled by a conductance G and a capacitance C, respectively.

Similarly, as shown in FIG. 4B, the conductance G and the capacitance C are coupled between the measurement electrode 201 (indicated by the letter M in the figure) and the semiconductor wafer 100. Can be regarded as being. Therefore, the measuring electrode 201 and the parallelism adjusting electrodes 111 to
113, the equivalent circuit of (a) and (b)
Are connected in series at the semiconductor wafer 100. FIG. 4C shows an equivalent circuit between the measurement electrode 201 and the parallelism adjustment electrodes 111 to 113. That is, the measurement electrode 201 and the parallelism adjustment electrodes 111 to 113 are
Y coupled by conductance G and capacitance C
It constitutes a symmetrical load of the form connection.

The electrodes 111, 112, 113, 2
Since the distance between the electrodes 01 and 01 is also set to, for example, about 1 mm, these electrodes are also electrically connected directly (that is, not through a semiconductor wafer), but these electrical connections are also made in FIG. It can be represented by the equivalent circuit of (c).

When the CV measurement of a semiconductor wafer is performed, the capacitance of the parallelism adjusting electrodes 111 to 113 is determined by LC
By measuring with the R meter 13 and controlling the piezoelectric actuators 21 to 23 so that their values match,
The parallelism between the semiconductor wafer 100 and the measurement electrode 201 is maintained. Then, a CV curve is measured using the measurement electrode 201.

The capacitance measurement for adjusting the parallelism and the capacitance measurement for obtaining the CV curve are both measurements using the characteristics of the capacitance with respect to the AC applied signal. Therefore, when trying to measure the CV curve with the measuring electrode 201 while measuring the capacitance with the parallelism adjusting electrodes 111 to 113 and keeping the parallelism, usually the parallelism adjusting electrodes 111 to 113 are used.
The AC signal applied to 13 is applied as a disturbance to the measurement electrode 201 via the conductance G and the capacitance C described above. Therefore, it is difficult to perform an accurate CV measurement.

On the other hand, if the parallelism is not adjusted during the CV measurement, the above-described problem does not occur.
However, when an element having expansion and contraction characteristics according to an applied voltage, such as a piezo element, is used as the piezoelectric actuators 21 to 23, it is necessary to keep adjusting the parallelism during the CV measurement. This is because a transient phenomenon cannot be ignored in a piezo element, and the element may expand and contract in sub-micron units even when the applied voltage is constant.

This embodiment takes the above points into consideration,
It is designed so that even if an AC signal is applied to the parallelism adjusting electrodes 111 to 113, it does not cause disturbance to the measuring electrode 201. FIG. 5 shows the parallelism adjusting electrodes 111 to 11.
3 shows a basic connection relationship between the AC power supply 3 and the AC power supply 130. The AC power supply 130 is a power supply that generates a so-called Y-connection three-phase AC, has the same line voltage, and outputs three AC signals whose phases are different by 120 °. Parallelism adjusting electrodes 111-113 and measuring electrode 20
1 is also represented as a Y-shaped connection load as shown in FIG. Then, as shown in FIG.
0 output lines are connected to the respective parallelism adjusting electrodes 111 to 113.

Since the parallelism adjusting electrodes 111 to 113 have the same shape, the impedance between the measuring electrode 201 and each of the parallelism adjusting electrodes 111 to 113 is maintained when the parallelism is maintained. Are equal, and these equivalent circuits have symmetric Y-type loads. Therefore, if the connection is made as shown in FIG. 5, the measurement electrode 201 is kept when the parallelism is maintained.
Is the same as the neutral point NP of the AC power supply 130.
As a result, the AC signal applied to the parallelism adjusting electrodes 111 to 113 is not applied to the measuring electrode 201 as a disturbance.

FIG. 6 shows the parallelism adjusting electrodes 111 to 113.
FIG. 4 is a diagram showing an actual connection relationship between the power supply and the AC power supply 130. 3
The three power transmission lines 130a to 130c of the phase AC power supply 130 are respectively connected to the parallelism adjusting electrodes 111 to 11 via resistors R.
3 is connected. Further, the neutral point NP of the three-phase AC power supply 130 and the electrode 202 (see FIG. 1) on the back surface of the semiconductor wafer are grounded.

The signals Sm1 to Sm3 appearing on the parallelism adjusting electrodes 111 to 113 are given to the capacitance meters 131 to 133 as measurement signals, respectively. The signals Sa1 to Sa3 of the transmission lines 130a to 130c are also supplied to the capacity meters 131 to 133 as applied signals. Based on these measurement signals and applied signals, the capacity meters 131 to 133 are provided with the respective parallelism adjusting electrodes 111 to 1.
The capacitance between the semiconductor wafer 13 and the semiconductor wafer is measured.
The resistors R connected to the parallelism adjusting electrodes 111 to 113 are a part of the constituent elements of the capacitance meters 131 to 133. In order to clarify the correspondence with FIG.
It is drawn separately from the capacity meter. In addition, three-phase AC power supply 1
30 and the capacity meters 131 to 133 are the LCR shown in FIG.
It is a part of the components of the meter 13.

C. Outline of Capacity Measurement Method FIG. 7 is a conceptual diagram for explaining a capacity measurement method in the capacity meters 131 to 133. (A) of FIG.
It is sectional drawing which shows one parallelism adjustment electrode 111 and a semiconductor wafer. As described above, the parallelism adjusting electrode 11
1 and the electrode 202 on the back surface of the semiconductor wafer are represented by (e.g., the parallelism adjusting electrode 111-air gap-
Oxide film 102-depletion layer 103-substrate 101-electrode 202
(B) can be represented by a capacitance C and a conductance G connected in parallel between the parallelism adjusting electrode 111 and the electrode 202, as shown in FIG.

In FIG. 6, the electrode 202 and the measuring electrode 2 are shown.
Although the capacitance Ct is drawn between the capacitor Ct. 01 and the ground potential equal to the neutral point NP of the AC power supply 130, the capacitance Ct is measured as described above.
Can be ignored. Therefore, the circuit between the electrode 111 and the electrode 202 in FIG. 6 is equivalent to the circuit in FIG. 7B. The admittance Y of the circuit shown in FIG.

(Equation 1) The impedance Z of this circuit is represented by the following equation (2).

(Equation 2)

FIG. 7C is a circuit diagram showing a circuit portion including the parallelism adjusting electrode 111, the electrode 202, and the AC power supply 130. The measurement signal Sm1 appearing on the parallelism adjusting electrode 111 is expressed by the following equation (3).

(Equation 3) Further, the applied signal Sa1 is represented by the following Expression 4 by the measurement signal Sm1.

(Equation 4) That is, the phase of the applied signal Sa1 is advanced from that of the measurement signal Sm1. Assuming that this phase angle is ψ, the following Expression 5 is established.

(Equation 5)

In Equation 5, if ωCR and RG are sufficiently small, the value of K is almost constant at 1. In this case, sin
ψ is proportional to C, and cos す る is proportional to (1 + RG).
For example, the frequency of the applied signal Sa1 is 100 kHz, and C =
Assuming that 100 pF and R = 10 kΩ, 2 of (ωCR)
The power is about 0.004, and G = 0.1 μS (=
0.1 μ / Ω), the value of RG is 0.004 or less, so that K = 1 can be considered.

If the value of K is almost constant, sinψ is C
Therefore, if sinψ is obtained, the capacitance C
Can be determined. sinψ is
It can be obtained as follows. First, when the measurement signal Sm1 is represented by Sm0 · sin (ωt) as in the following Expression 6, the applied signal Sa1 is represented as in Expression 7 using the phase angle ψ. Here, Sm0 and Sa0 are constants.

(Equation 6)

(Equation 7)

Here, the term sin (ωt + ψ) is changed to (ω
By integrating from π / 2 to 3π / 2 in t), a value proportional to sinψ can be calculated as shown in Expression 8.

(Equation 8) In general, an integral value In proportional to sinψ can be obtained by integrating the applied signal Sa1 in each of two phase sections of the measurement signal Sm1 as follows. a. The first phase section [(π / 2 + 2n) of the measurement signal Sm1
π) to (3π / 2 + 2nπ)]: The integral value In is obtained by integrating the applied signal Sa1 (Equation 9).

(Equation 9) b. The second phase section of the measurement signal Sm1 [(3π / 2 + 2
nπ) to (5π / 2 + 2nπ)]: Integrate (Equation 10) the signal -Sa1 obtained by inverting the applied signal Sa1, and obtain an integral value In.
Ask for.

(Equation 10)

As described above, by integrating the applied signal Sa1 in each of the two phase sections with reference to the measurement signal Sm1, an integral value In proportional to the sine sin 正弦 of the phase angle に お い て is obtained in each phase section. Can be. Note that, as is clear from Equations 9 and 10,
Since the integral value In in the two phase sections is equal,
Find the integral value In only in one of the phase sections
You may do so. Since this integral value In is proportional to sinψ, if the values of the integral values In for the three parallelism adjusting electrodes 111 to 113 are equal to each other, the values of sinψ for the respective parallelism adjusting electrodes are also equal to each other. Also, si
Since the value of nψ is proportional to the capacitance C as described in Equation 5, the value of s for each parallelism adjusting electrode is
If the values of inψ are equal to each other, the capacity of the gap between each parallelism adjusting electrode and the semiconductor wafer is equal to each other.
Since the gap capacity is inversely proportional to the gap size,
If the capacities are equal to each other, it can be said that the sizes of the gaps are also equal to each other. Therefore, the three parallelism adjusting electrodes 111 to
If the piezoelectric actuators 21 to 23 are adjusted so that the integrated value In of 113 becomes equal to each other, the parallelism between the bottom surface 41a of the prism and the semiconductor wafer can be adjusted.

In practice, the value of K in Equation 5 is not constant but depends on the capacitance C. Therefore, the relationship between the integral value In and the capacitance C deviates from a linear proportional relationship as shown by a solid line in FIG. However,
It is not necessary to accurately measure the value of the capacitance C for the adjustment of the parallelism. If the value of the monotonic function of the capacitance C can be measured, the measured values at the respective electrodes for adjusting the parallelism are made equal to each other. , Parallelism can be adjusted. Therefore, as the capacity meter for adjusting the parallelism, it is sufficient to use a device that can obtain the above-described integral value In.

D. FIG. 9 is a block diagram showing the internal configuration of the capacity meter 131 shown in FIG. FIG. 10 is a timing chart showing main signals in the circuit of FIG. In FIG. 6 described above, the transmission line 130a and the parallelism adjusting electrode 111 are used.
Is an internal circuit of the capacity meter 131 as described above, and is inserted between the two input terminals T1 and T2 in FIG. As can be seen from Equation 5, the resistor R has a role to delay the phase of the measurement signal Sm1 appearing at the first input terminal T1 from the phase of the applied signal Sa1. Note that the first input terminal T
1 is connected to the parallelism adjusting electrode 111, and the second input terminal T2 is connected to the transmission line 130a.

The capacitance meter 131 includes a first buffer amplifier 51, a detection unit 52, an integrator 53, a second buffer amplifier 54, and a voltmeter 55, in addition to the resistance R.
And The other parallelism adjusting electrodes 112,
The capacity meters 132 and 133 for 113 have the same configuration as the capacity meter 131 in FIG. Note that the detection integration means in the present invention is realized by the detection unit 52 and the integrator 53.

The applied signal S appearing at the second input terminal T2
a1 is a clean sine wave as shown at the top of FIG. The applied signal Sa1 corresponds to the power supply signal in the present invention. The measurement signal Sm appearing at the first input terminal T1
1 is amplified by a buffer amplifier 51 and multiplied by α.
The signal α · Sm1 shown in FIG. This signal is a sine wave including a noise component, and its phase is delayed from the applied signal Sa1 by the above-described phase angle ψ.

The signal α output from the buffer amplifier 51
Sm1 is the applied signal Sa applied to the second input terminal
1 is input to the detector 52. The detection unit 52 detects (a) two phase sections of the measurement signal Sm1 and (b) each of the two phase sections so that the integrator 53 can perform the integration of Equations 9 and 10 described above. And the waveforms of the applied signals Sa1 and -Sa1 corresponding to (1) are extracted, and (c) a signal SM having this waveform is output. The detection unit 52 includes 9
It has a 0 ° phase shifter 52a, a switching signal generator 52b, a switch 52c, and a 180 ° phase shifter 52d. 90
The phase shifter 52a generates the signal Sms shown in FIG. 10 by delaying the phase of the signal α · Sm1 supplied from the buffer amplifier 51 by 90 °.

This signal Sms is supplied to a switching signal generator 52b, and the switching signal generator 52b generates two switching signals SS1 and SS2 based on the signal Sms. The first switching signal SS1 is a signal that goes high when the value of the signal Sms is positive and goes low when the value of the signal Sms is negative. On the other hand, the second switching signal SS2 is a signal that becomes L level when the value of the signal Sms is positive and becomes H level when the value of the signal Sms is negative. Since the phase of the signal Sms is delayed by 90 ° (= π / 2) from the phase of the measurement signal Sm1, as shown in FIG. 10, the first switching signal SS1 is the first switching signal SS1 of the signal Sms.
Phase section [(π / 2 + 2nπ) to (3π / 2 + 2n)
π)], and the second switching signal SS2 becomes the second phase section [(3π / 2 + 2nπ)-(5)] of the signal Sms.
.pi. / 2 + 2n.pi.)]. These switching signals SS1 and SS2 are provided to a switch 52c.

As described above, as a result of switching the levels of the switching signals SS1 and SS2 at the zero cross point of the signal Sms, the periods of the H level and the L level may not be equal. In this case, the switching signal generator 5
By adjusting the signal level (slice level) at which switching is performed in 2b, the periods of the H level and the L level may be equalized (that is, the duty may be 50%).

The switching signal 52 is supplied to the switch 52c.
1, SS2, the applied signal Sa1 and its inverted signal
Sa1 (shown by a broken line at the top of FIG. 10) is input. The inverted signal -Sa1 is generated by delaying the phase of the applied signal Sa1 by 180 ° by the 180 ° phase shifter 52d. The switch 52c outputs the applied signal Sa1 as the output signal SM of the detector 52 during the period when the first switch signal SS1 is at the H level, and the second switch signal SS2 is at the H level. During the period, the inverted signal -Sa1 is output as the output signal SM of the detector 52. As a result, as shown in FIG. 10, the output signal SM has two phase sections [(π / 2 + 2nπ) 〜] of the measurement signal Sm1.
(3π / 2 + 2nπ)], [(3π / 2 + 2nπ) ~
(5π / 2 + 2nπ)].

The integrator 53 outputs the output signal SM of the detector 52.
To each phase section [(π / 2 + 2nπ) to (3π / 2 + 2n)
π)], [(3π / 2 + 2nπ) to (5π / 2 + 2n
π)] to generate an integrated signal SI. This integrated signal SI is multiplied by β in the buffer amplifier 54, and the signal β · SI multiplied by β is supplied to the voltmeter 55. The other terminal of the voltmeter 55 is grounded. The level of the integration signal SI is determined by the integration value In given by Expressions 9 and 10.
Therefore, the voltage value measured by the voltmeter 55 is a value represented by a monotonic function of the capacitance C between the parallelism adjusting electrode 111 and the semiconductor wafer.

The signal Sc1 indicating the value measured by the voltmeter 55 is given to the position control device 11 (see FIG. 2).
By being compared with the measured values of the other capacity meters 132 and 133, the bottom surface 41a of the prism and the semiconductor wafer 10 are compared.
The parallelism between 0 and 0 is adjusted.

As described above, the capacity meter 1 of this embodiment
31 integrates the applied signal Sa1 with reference to a predetermined phase section of the measurement signal Sm1 to obtain a capacitance C.
The value proportional to is calculated. As also shown in FIG.
The applied signal Sa1, which is a power signal, is a clean sine wave, whereas the measurement signal Sm1 has a distorted waveform including a noise component. Contrary to the above embodiment, the applied signal Sa
There is also a method of integrating the measurement signal Sm1 with reference to one phase section, but in this method, the integrated value is easily affected by the noise component of the measurement signal Sm1. On the other hand, in the above embodiment, since the clean sine wave applied signal Sa1 is integrated, there is an advantage that the integrated value In is hardly affected by the noise of the measurement signal Sm1.

In the above-described capacitance meter, the electrode 202 as one electrode of the capacitance to be measured is grounded, and an application signal is applied to the parallelism measurement electrode as the other electrode via the resistor R. In other words, if this capacitance meter is used, a measurement value dependent on the capacitance value of the capacitance to be measured can be obtained in the single-ended mode, so that the measurement values dependent on multiple capacitance values affect each other's measurement values. There is an advantage that measurement can be performed at the same time.

E. FIG. 11 is a graph showing the relationship between the inclination of the bottom surface of the prism 41 and the capacitance Ce of each of the parallelism adjusting electrodes 111 to 113. Electrodes 111 to 11 for adjusting parallelism shown in FIG.
The dimensions of No. 3 are as follows. Inner diameter r0 = 0.08cm Outer diameter r1 = 0.12cm Gap between electrodes Δg = 0.07cm

The results of FIG. 11B are obtained by calculating the capacitance of each electrode under the condition that the bottom surface of the prism is tilted about the axis α, as shown in FIGS. . The axis α is an axis of mirror symmetry between the electrodes 112 and 113. When the prism 41 is tilted by the angle θ, the surfaces of the electrodes 111 to 113 deviate from positions where the surfaces of the electrodes 111 to 113 are parallel to the surface of the semiconductor wafer 100 (the positions indicated by broken lines in the drawing), as shown in FIG. At this time, the distance Δd at which the ends of the electrodes 111 to 113 deviate from their parallel positions is taken as the horizontal axis in FIG.

The capacitance C of the parallelism adjusting electrodes 111 to 113
e is the capacity meter 1 of the LCR meter 13 as described above.
It measures using 31-133. The accuracy of the capacity measurement system including the LCR meter 13 and the host controller 14 is set to 0.
It is relatively easy to make it about 1 pF. Assuming that the accuracy of the capacitance measuring system is 0.1 pF, it can be seen from FIG. 11B that the parallelism can be adjusted so that the distance Δd is 0.01 μm or less. When the distance Δd is 0.01 μm, the inclination angle θ of the prism surface is about 0.0005 °, which is negligible.

FIG. 12 is a graph showing the relationship between the distance Δd and the capacitance Ce of each parallelism adjusting electrode when the prism 41 is tilted about an axis β perpendicular to the axis α. In this case, as in the case of FIG. 11, if the accuracy of the capacitance measuring system is 0.1 pF, the distance Δd is 0.01 μm.
The parallelism can be adjusted as follows.

As described above, three electrodes for adjusting the degree of parallelism are provided on the bottom surface of the prism, a three-phase AC signal is applied thereto, and the capacitance is measured. When the piezoelectric actuators 21 to 23 are driven, the parallelism between the bottom surface of the prism (that is, the surface of the measurement electrode 201) and the surface of the semiconductor wafer 100 can be adjusted with high accuracy. At this time, it is not necessary to accurately determine the capacitance value of each parallelism adjusting electrode, and it is sufficient to control the piezoelectric actuator so that these values become equal to each other.

As described above, the parallelism adjusting electrodes 111 to 1
When a three-phase AC signal is applied to the electrode 13, the potential of the measuring electrode 201 is maintained at the same potential as the neutral point NP of the three-phase AC power supply. There is no disturbance to. Therefore, there is an advantage that electrical measurement such as CV measurement can be accurately performed while adjusting the parallelism.

Further, in the above embodiment, since the neutral point NP of the three-phase AC power source and the electrode 202 on the back surface of the semiconductor wafer are both grounded, if the parallelism is maintained, the electrode 202 and the measuring electrode 201 are maintained. (Ie, through the semiconductor wafer). This is also an advantage in performing accurate electrical measurement using the measurement electrode.

Further, since no current flows between the electrode 202 and the measuring electrode 201, the conductive sample stage 7
When the semiconductor wafer 100 is used as the electrode 202,
The parallelism can be accurately adjusted without reducing the impedance between the back surface of the sample and the sample table 7. That is, there is an advantage that the conductive sample stage 7 can be used as the electrode 202 without paying much attention to the adhesion between the semiconductor wafer 100 and the sample stage 7.

Further, since the capacitance meters 131 to 133 can measure in the single-end mode without using a bridge, the measurement values depending on the capacitance values of the plurality of parallelism adjusting electrodes are affected by the mutual measurement values. There is an advantage that measurement can be performed without any problem. Further, since a measured value corresponding to the capacitance value is obtained by integrating the applied signals Sa1 to Sa3 in a predetermined phase section of the measured signals Sm1 to Sm3, the measured values are not affected by noise components of the measured signals Sm1 to Sm3. There is also an advantage that can be obtained.

F. Modifications The present invention is not limited to the above embodiment,
The present invention can be implemented in various modes without departing from the gist of the present invention. For example, the following modifications can be made.

(1) As the parallelism adjusting electrodes, generally, N (N is an integer of 3 or more) electrodes having the same shape may be provided at symmetrical positions with respect to the measuring electrodes. In this case, the AC applied signal applied to each electrode is a symmetric N-phase signal having the same frequency and electromotive force and different phases by 2π / N. This has the same effect as the above embodiment.

(2) If there is no concern that the parallelism will be lost during the electrical measurement, N AC signals having no phase difference (ie, having the same phase) are applied to the N parallelism adjusting electrodes. It may be applied. In this case, the parallelism is first adjusted using the parallelism adjusting electrode, and the parallelism is maintained.
Electrical measurement is performed using the measurement electrode without applying a signal to the parallelism adjustment electrode. However, if the symmetrical N-phase signal is used as described above, no disturbance is applied to the measuring electrode, and no current due to the applied signal for the parallelism adjustment flows through the semiconductor wafer. There is an advantage that the electrical measurement can be performed with high accuracy while adjusting the temperature. When an AC signal having the same phase is applied to the parallelism adjusting electrode, if the shape of the measuring electrode and the shape of the parallelism adjusting electrode are made equal, the parallelism adjusting electrode can be used as the measuring electrode. Since it can be used, one of the N parallelism adjusting electrodes can be used as a measuring electrode.

(3) The present invention is not limited to the CV measurement,
In general, the present invention can be applied to a parallelism adjusting device used for a device for measuring electric characteristics between a measurement electrode and a semiconductor substrate.
As another electrical measurement, for example, there is a method of evaluating the characteristics near the semiconductor surface by examining the time dependency of the combined capacitance Cta by the Zerubst method. Also, L
If the conductance is measured by the CR meter 13,
It is also possible to evaluate an interface state and the like at an interface between the semiconductor substrate 101 and the oxide film 102. Furthermore, if CV measurement is performed in a state where an oxide film is not formed on a semiconductor wafer during each process such as a cleaning process of a semiconductor substrate, a thermal oxidation process, and a heat treatment for stabilizing an oxide film, each of these processes can be performed. The quality of the processing can be determined.

[0060]

As described above, according to the present invention, there is provided a mode in which one electrode of the capacitance to be measured is connected to the ground side and the other electrode is connected to the first input terminal (so-called single-ended mode). ), It is possible to measure the measurement value depending on the capacitance value of a plurality of capacitances to be measured. If the ground electrode of the capacitance to be measured is a common electrode,
There is an effect that the measurement can be performed without being affected by the mutual measurement values. In addition, since the detection and integration means obtains a measurement value depending on the capacitance value by integrating the power supply signal in a predetermined phase section of the measurement signal, the measurement value is accurately obtained without being affected by the noise component of the measurement signal. There is an effect that can be.

[Brief description of the drawings]

FIG. 1 is a conceptual diagram showing an outline of a method for measuring electricity of a semiconductor. ,

FIG. 2 is a diagram showing a configuration of an electricity measuring device as one embodiment of the present invention.

FIG. 3 is a diagram showing an arrangement of electrodes in the embodiment.

FIG. 4 is an explanatory diagram showing an equivalent circuit between electrodes.

FIG. 5 is a diagram showing a basic connection relationship between an AC power supply and a parallelism adjusting electrode.

FIG. 6 is a diagram showing a connection relationship between an AC power supply, a parallelism adjustment electrode, and a capacitance meter.

FIG. 7 is an explanatory diagram showing an equivalent circuit between an AC power supply, a resistance and a parallelism adjustment electrode, and an electrode of a semiconductor wafer.

FIG. 8 is a graph showing a relationship between an integral value and a measured capacity in a capacity meter.

FIG. 9 is a block diagram showing an internal configuration of the capacity meter.

FIG. 10 is a timing chart showing main signals in the capacity meter.

FIG. 11 is a graph showing the relationship between the inclination of the bottom surface of a prism and the capacitance of a parallelism adjusting electrode.

FIG. 12 is a graph showing the relationship between the inclination of a prism and the capacitance of each parallelism adjusting electrode.

FIG. 13 is a diagram showing another arrangement of electrodes.

[Explanation of symbols]

 Reference Signs List 3 base 41 prism 41a bottom surface 5 laser oscillator 6 light receiving sensor 7 sample table 21-23 piezoelectric actuator 100 semiconductor wafer 101 semiconductor substrate 102 oxide film 111-113 parallelism adjusting electrode 130 three-phase AC power supply 131-133 capacity meter 201 measurement electrode

Claims (1)

(57) [Claims] 1. A capacitance measuring device for obtaining a measurement value dependent on a capacitance value of a capacitance to be measured of an object to be measured, wherein one electrode is connected to the other electrode of the capacitance to be measured connected to the ground side. A first input terminal connected thereto, a second input terminal to which a power signal having a sine waveform is input, a resistance element interposed between the first and second input terminals, in one input terminal appears in a predetermined phase interval of the measurement signal, the second product asking you to measurement value dependent on the capacitance value of the capacitance to be measured by the product minute input the power source signal to the input terminal A capacity measuring device comprising: