JP2640586B2 - Semiconductor wafer electrical measuring device and parallelism adjusting device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electric measuring device for measuring electric characteristics of a semiconductor wafer such as a CV curve, and a parallelism adjusting device used in the electric measuring device.

[0002]

2. Description of the Related Art As one method of evaluating a process of a semiconductor having a MIS structure, an evaluation method based on CV measurement is used. In the conventional CV measurement, it was necessary to form electrodes for electrical measurement on the surface of an oxide film on a semiconductor substrate. However, the process of forming electrodes only affects the electrical characteristics of the semiconductor wafer itself. No. There is a problem that it takes time and effort to form the electrode itself. . Accordingly, the present applicant has developed a semiconductor wafer electric measurement device capable of performing electric characteristic evaluation such as CV measurement and Ct method without forming electrodes on the surface of the semiconductor wafer. FIG. 1 is a conceptual diagram showing an outline of a semiconductor electric measurement device developed by the present applicant. 1A, an oxide film 102 is formed on a front surface of a semiconductor substrate 101, and an electrode 202 is formed on a back surface. Oxide film 1
Above the measuring electrode 20 with a gap Ge therebetween.
1 is held by the electrode holding unit 300.
The gap Ge between the oxide film 102 and the measurement electrode 201 is
As will be described later, the thickness is controlled by the electrode holding unit 300 so as to be about 1 μm or less.

The capacitance Ct between the two electrodes 201 and 202 is, as shown in FIG. 1B, a capacitance Cs of the semiconductor substrate 101, a capacitance Ci of the oxide film 102, a gap Ge. In series with the capacitance Cg. C
The -V curve shows the capacitance Cs of the semiconductor substrate 101 and the oxide film 1
12 shows the voltage dependence of the combined capacitance Cta with the capacitance Ci of No. 02. The value of the gap Ge is accurately measured by the electrode holding unit 300, and the capacitance Cg of the gap is calculated based on the value of the gap Ge. The combined capacitance Ct is measured by the measuring section 400, and the combined capacitance Ct
The CV curve is determined by calculating the capacitance Cta by subtracting the capacitance Cg of the gap from.

[0004]

By the way, when electrical measurement of a semiconductor is performed using the above-described apparatus, unless the measurement electrode 201 and the surface of the semiconductor wafer are not parallel to each other, the capacitance Cg of the gap Ge is reduced. The value deviates from the calculated value based on the gap Ge, which is not desirable for accurate electrical measurement. Therefore, it is desirable that the electric measurement device be provided with a device for accurately adjusting the parallelism between the measurement electrode (or the holding surface) and the semiconductor wafer surface.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and has as its object to provide an apparatus capable of accurately adjusting the parallelism between an electrode holding surface and a semiconductor wafer surface. And

[0006]

According to a first aspect of the present invention, there is provided an apparatus for measuring electric power of a semiconductor wafer, wherein the electric power is held on a predetermined electrode holding surface with a gap between the semiconductor wafer and the surface of the semiconductor wafer. A measuring electrode to be measured, measuring means for measuring electric characteristics between the measuring electrode and the semiconductor wafer, and equal means provided on the electrode holding surface at symmetrical positions with respect to the measuring electrode. Symmetry N having the same frequency and the same electromotive force and different phases by 2π / N with respect to the N (N is an integer of 3 or more) parallelism adjusting electrodes and the N parallelism adjusting electrodes having the same shape. The capacitance between each of the N parallelism adjusting electrodes and the semiconductor wafer and the AC power supply for applying a phase AC signal is expressed by the symmetric N
And a parallelism adjusting means for measuring parallelism signals and adjusting the parallelism between the electrode holding surface and the surface of the semiconductor wafer based on a comparison result of the capacitance.

According to a second aspect of the present invention, there is provided a parallelism adjusting device provided at an electrode holding surface held with a gap between the electrode holding surface and a surface of a semiconductor wafer, and at symmetrical positions on the electrode holding surface. And N (N is an integer of 3 or more) parallelism adjusting electrodes having the same shape and N parallel electrodes having the same frequency and the same electromotive force with respect to the N parallelism adjusting electrodes. An AC power source for applying an AC signal, and the capacitance between each of the N parallelism adjusting electrodes and the semiconductor wafer are measured based on the AC signal, and a comparison result of the capacitance is measured. And a parallelism adjusting means for adjusting the parallelism between the electrode holding surface and the surface of the semiconductor wafer based on the above. In the device of claim 2, one of the N parallelism adjusting electrodes may be used as a measuring electrode.
A measuring electrode may be provided separately from the parallelism adjusting electrode.

[0008]

According to the first aspect of the present invention, the N parallelism adjusting electrodes have the same shape and are provided at positions symmetrical to each other with respect to the measuring electrode. An equivalent circuit composed of N parallelism adjusting electrodes is
A symmetrical load with a star connection centered on the measurement electrode. Since a symmetrical N-phase AC signal is applied to the N parallelism adjusting electrodes, the measurement conditions of the capacitance at each parallelism adjusting electrode are equal, and the potential of the measuring electrode is equal to that of the AC power supply. It is kept equal to the potential of the gender point. Therefore, even if an AC signal for adjusting the parallelism is applied, it does not disturb the measuring electrode. Therefore, it is necessary to adjust the parallelism by the parallelism adjusting means while performing accurate electrical measurement with the measuring electrode. Can be.

According to the second aspect of the present invention, since N alternating current signals having the same phase are applied to the N parallelism adjusting electrodes, the measurement condition of the capacitance of each parallelism adjusting electrode is applied. Are equal. Therefore, the parallelism can be accurately adjusted by the parallelism adjusting means comparing the capacitances of the respective parallelism adjusting electrodes.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 2 is a diagram showing a configuration of an electric measurement device MD as an embodiment of the present invention. The electric measurement device MD includes a sample table 7 on which the semiconductor wafer 100 is mounted, and a mount 3 having a trapezoidal cross section installed above the sample table 7.

An optical system including a laser oscillator 5, a prism 41, and a light receiving sensor 6 is installed on the gantry 3. The two slopes at the bottom of the gantry 3 are formed so that the angle between them is 90 °, and a prism 41 is fixed to the bottom of the gantry 3. A laser oscillator 5 such as a GaAlAs laser is fixed to one end of the slope of the gantry 3, and a light receiving sensor 6 such as a photodiode is fixed to the end of the other slope.

When electric measurement of the semiconductor wafer 100 is performed, the gap between the bottom surface 41a of the prism and the surface of the semiconductor wafer 100 is kept at about 1 μm or less. The optical system including the laser oscillator 5, the prism 41, and the light receiving sensor 6 is an optical measurement system for accurately measuring the gap. This optical measurement system utilizes the tunneling phenomenon of laser light when the laser light emitted from the laser oscillator 5 is reflected on the bottom surface 41a of the prism 41 under geometric total reflection conditions. The value of the gap is measured based on the light amount measured by the light amount measuring device 12.
However, the details are omitted here.

The prism 41 is made of borosilicate glass (B
K7), on the bottom surface 41a of which are formed a measuring electrode 201 and parallelism adjusting electrodes 111 to 113 to be described later. Also, the bottom surface 41a of the prism 41
Is set substantially parallel to a plane (xy plane) parallel to the surface of the sample stage 7 on which the semiconductor wafer 100 is mounted. The prism 41 is formed so that its incident surface 41b and its outgoing surface 41c are at 90 ° to each other, and the angle between these surfaces 41b and 41c and the bottom surface 41a is 45 °. Below the prism 41, the semiconductor wafer 100 is held on the sample table 7 via a minute gap, and the surface of the semiconductor wafer 100 is set so as to be substantially parallel to the bottom surface 41a of the prism 41.

The sample stage 7 is supported by three piezoelectric actuators 21 to 23 erected on an xy table 31. The xy table 31 is driven by an x-axis drive motor 32x and a y-axis drive motor 32y, and moves on an xy plane. The xy table 31 is supported by a vertical column 34 erected on a base 33, and is driven by a z-axis drive motor 32z to move in the z-axis direction. A position controller 11 is connected to the piezoelectric actuators 21 to 23, a light amount measuring device 12 is connected to the light receiving sensor 6, and an LCR meter 13 is connected to each electrode on the bottom surface 41 a of the prism 41 and the metal sample table 7. Is connected. The LCR meter 13 is a device that measures the capacitance and conductance between each electrode and the sample table 7.

Position control device 11, light quantity measuring device 12, LC
The R meter 13 is connected to a host controller 14, which controls the entire measuring device and processes the obtained data. As the host controller 14, for example, a personal computer is used. The sample stage 7 is prism 41
, The sample stage 7 is first raised by the z-axis drive motor 32z, and once stopped when the surface of the sample stage 7 reaches the height of the initial position sensor 35. After that, the height of the sample stage 7 is finely adjusted using the piezoelectric actuators 21 to 23. The piezoelectric actuators 21 and 2
3 and the motors 32z, 32y, 32z are all controlled by the position control device 11.

FIG. 3 is a diagram showing the bottom surface 41a of the prism 41 of the electric measuring device MD. An electrode 201 for electric measurement and three electrodes 111 to 113 for adjusting parallelism are formed on the bottom surface 41 a of the prism 41. Also,
The conductor 201 is connected to the electrodes 201, 111 to 113, respectively.
a, 111a to 113a are connected. The piezoelectric actuators 21 to 23 are installed at positions outside the center of each of the electrodes 111 to 113, respectively, as indicated by broken lines in FIG. These piezoelectric actuators 21 to 23
Are driven independently of each other by the position control device 11,
As a result, the parallelism between the surface of the semiconductor wafer 100 placed on the sample table 7 and the surface of the measurement electrode 201 is adjusted.

Each of the parallelism adjusting electrodes 111 to 113 has an equally divided ring shape. Each of these electrodes may have a circular shape. However, if the electrodes are divided into ring shapes as shown in FIG. 3, there is an advantage that an electrode having a larger area can be formed in a smaller region.

The bottom surface 41a of the prism 41 corresponds to the electrode holding surface in the present invention. Further, the parallelism adjusting means according to the present invention comprises three piezoelectric actuators 2.
1 to 23, the position control device 11, and the LCR meter 13
And the host controller 14. FIG.
The electrode holding unit 300 is realized by the piezoelectric actuators 21 to 23, the gantry 3, the prism 41, the laser oscillator 5, the light receiving sensor 6, the position control device 11, the light quantity measuring device 12, and the host controller 14. Have been.

B. FIG. 4 is a schematic diagram showing an equivalent circuit including the parallelism adjusting electrodes 111 to 113, the measuring electrode 201, and the semiconductor wafer 100. FIG. 4A shows a parallelism adjusting electrode 1.
The equivalent circuit between the semiconductor wafer 100 (indicated by the letter W in the figure) and the semiconductor wafer 100 (indicated by the letters S, T, U in the figure) is shown. Since the distance between the parallelism adjusting electrodes 111 to 113 and the semiconductor wafer 100 is adjusted to be very short (to about 1 μm or less),
Each of the electrodes 111 to 113 and the semiconductor wafer 100 can be considered to be coupled by a conductance G and a capacitance C, respectively.

Similarly, as shown in FIG. 4B, the conductance G and the capacitance C are coupled between the measurement electrode 201 (indicated by the letter M in the figure) and the semiconductor wafer 100. Can be regarded as being. Therefore, the measuring electrode 201 and the parallelism adjusting electrodes 111 to
113, the equivalent circuit of (a) and (b)
Are connected in series at the semiconductor wafer 100. FIG. 4C shows an equivalent circuit between the measurement electrode 201 and the parallelism adjustment electrodes 111 to 113. That is, the measurement electrode 201 and the parallelism adjustment electrodes 111 to 113 are
Y coupled by conductance G and capacitance C
It constitutes a symmetrical load of the form connection.

The electrodes 111, 112, 113, 2
Since the distance between the electrodes 01 and 01 is also set to, for example, about 1 mm, these electrodes are also electrically connected directly (that is, not through a semiconductor wafer), but these electrical connections are also made in FIG. It can be represented by the equivalent circuit of (c).

When the CV measurement of a semiconductor wafer is performed, the capacitance of the parallelism adjusting electrodes 111 to 113 is determined by LC
By measuring with the R meter 13 and controlling the piezoelectric actuators 21 to 23 so that their values match,
The parallelism between the semiconductor wafer 100 and the measurement electrode 201 is maintained. Then, a CV curve is measured using the measurement electrode 201.

The capacitance measurement for adjusting the parallelism and the capacitance measurement for obtaining the CV curve are both measurements using the characteristics of the capacitance with respect to the AC applied signal. Therefore, when trying to measure the CV curve with the measuring electrode 201 while measuring the capacitance with the parallelism adjusting electrodes 111 to 113 and keeping the parallelism, usually the parallelism adjusting electrodes 111 to 113 are used.
The AC signal applied to 13 is applied as a disturbance to the measurement electrode 201 via the conductance G and the capacitance C described above. Therefore, it is difficult to perform an accurate CV measurement.

On the other hand, if the parallelism is not adjusted during the CV measurement, the above-described problem does not occur.
However, when an element having expansion and contraction characteristics according to an applied voltage, such as a piezo element, is used as the piezoelectric actuators 21 to 23, it is necessary to keep adjusting the parallelism during the CV measurement. This is because a transient phenomenon cannot be ignored in a piezo element, and the element may expand and contract in sub-micron units even when the applied voltage is constant.

This embodiment takes the above points into consideration,
It is designed so that even if an AC signal is applied to the parallelism adjusting electrodes 111 to 113, it does not cause disturbance to the measuring electrode 201. FIG. 5 shows the parallelism adjusting electrodes 111 to 11.
3 shows a basic connection relationship between the AC power supply 3 and the AC power supply 130. The AC power supply 130 is a power supply that generates a so-called Y-connection three-phase AC, has the same line voltage, and outputs three AC signals whose phases are different by 120 °. Parallelism adjusting electrodes 111-113 and measuring electrode 20
1 is also represented as a Y-shaped connection load as shown in FIG. Then, as shown in FIG.
0 output lines are connected to the respective parallelism adjusting electrodes 111 to 113.

Since the parallelism adjusting electrodes 111 to 113 have the same shape, the impedance between the measuring electrode 201 and each of the parallelism adjusting electrodes 111 to 113 is maintained when the parallelism is maintained. Are equal, and these equivalent circuits have symmetric Y-type loads. Therefore, if the connection is made as shown in FIG. 5, the measurement electrode 201 is kept when the parallelism is maintained.
Is the same as the neutral point NP of the AC power supply 130.
As a result, the AC signal applied to the parallelism adjusting electrodes 111 to 113 is not applied to the measuring electrode 201 as a disturbance.

FIG. 6 shows the parallelism adjusting electrodes 111 to 113.
FIG. 4 is a diagram showing an actual connection relationship between the power supply and the AC power supply 130. 3
The three power transmission lines 130a to 130c of the phase AC power supply 130 are respectively connected to the parallelism adjusting electrodes 111 to 11 via resistors R.
3 is connected. Further, the neutral point NP of the three-phase AC power supply 130 and the electrode 202 (see FIG. 1) on the back surface of the semiconductor wafer are grounded.

The signals Sm1 to Sm3 appearing on the parallelism adjusting electrodes 111 to 113 are given to the capacitance meters 131 to 133 as measurement signals, respectively. The signals Sa1 to Sa3 of the transmission lines 130a to 130c are also supplied to the capacity meters 131 to 133 as applied signals. Based on these measurement signals and applied signals, the capacity meters 131 to 133 are provided with the respective parallelism adjusting electrodes 111 to 1.
The capacitance between the semiconductor wafer 13 and the semiconductor wafer is measured.
The resistors R connected to the parallelism adjusting electrodes 111 to 113 are a part of the constituent elements of the capacitance meters 131 to 133. In order to clarify the correspondence with FIG.
It is drawn separately from the capacity meter. In addition, three-phase AC power supply 1
30 and the capacity meters 131 to 133 are the LCR shown in FIG.
It is a part of the components of the meter 13.

C. FIG. 7 is a graph showing the relationship between the inclination of the bottom surface of the prism 41 and the capacitance Ce of each of the parallelism adjusting electrodes 111 to 113. Parallelism adjusting electrodes 111 to 113 shown in FIG.
Are as follows. Inner diameter r0 = 0.08cm Outer diameter r1 = 0.12cm Gap between electrodes Δg = 0.07cm

The results of FIG. 7 (b) are obtained by calculating the capacitance of each electrode under the condition that the bottom of the prism is tilted about the axis α, as shown in FIGS. 7 (a) and 7 (c). . The axis α is an axis of mirror symmetry between the electrodes 112 and 113. When the prism 41 is tilted by the angle θ, the surfaces of the electrodes 111 to 113 deviate from positions where the surfaces of the electrodes 111 to 113 are parallel to the surface of the semiconductor wafer 100 (the positions indicated by broken lines in the drawing), as shown in FIG. At this time, the distance Δd at which the ends of the electrodes 111 to 113 deviate from their parallel positions is taken as the horizontal axis in FIG.

The capacitance C of the parallelism adjusting electrodes 111 to 113
e is the capacity meter 1 of the LCR meter 13 as described above.
It measures using 31-133. The accuracy of the capacity measurement system including the LCR meter 13 and the host controller 14 is set to 0.
It is relatively easy to make it about 1 pF. Assuming that the accuracy of the capacitance measurement system is 0.1 pF, it can be seen from FIG. 7B that the parallelism can be adjusted so that the distance Δd is 0.01 μm or less. When the distance △ d is 0.01 μm,
The inclination angle θ of the prism surface is about 0.0005 °, which is negligible.

FIG. 8 is a graph showing the relationship between the distance Δd and the capacitance Ce of each parallelism adjusting electrode when the prism 41 is tilted about an axis β perpendicular to the axis α.
In this case, as in the case of FIG. 7, if the accuracy of the capacitance measuring system is set to 0.1 pF, the parallelism can be adjusted so that the distance Δd is 0.01 μm or less.

As described above, three electrodes for adjusting the degree of parallelism are provided on the bottom surface of the prism, a three-phase AC signal is applied thereto, and the capacitance is measured. The three electrodes are adjusted so that their capacitance values become substantially equal to each other. When the piezoelectric actuators 21 to 23 are driven, the parallelism between the bottom surface of the prism (that is, the surface of the measurement electrode 201) and the surface of the semiconductor wafer 100 can be adjusted with high accuracy. At this time, it is not necessary to accurately determine the capacitance value of each parallelism adjusting electrode, and it is sufficient to control the piezoelectric actuator so that these values become equal to each other.

As described above, the parallelism adjusting electrodes 111 to 1
When a three-phase AC signal is applied to the electrode 13, the potential of the measuring electrode 201 is maintained at the same potential as the neutral point NP of the three-phase AC power supply. There is no disturbance to. Therefore, there is an advantage that electrical measurement such as CV measurement can be accurately performed while adjusting the parallelism.

In the above embodiment, since the neutral point NP of the three-phase AC power supply and the electrode 202 on the back surface of the semiconductor wafer are both grounded, if the parallelism is maintained, the electrode 202 and the measuring electrode 201 are maintained. (Ie, through the semiconductor wafer). This is also an advantage in performing accurate electrical measurement using the measurement electrode.

Further, since no current flows between the electrode 202 and the measuring electrode 201, the conductive sample stage 7
When the semiconductor wafer 100 is used as the electrode 202,
The parallelism can be accurately adjusted without reducing the impedance between the back surface of the sample and the sample table 7. That is, there is an advantage that the conductive sample stage 7 can be used as the electrode 202 without paying much attention to the adhesion between the semiconductor wafer 100 and the sample stage 7.

D. Modifications The present invention is not limited to the above embodiment,
The present invention can be implemented in various modes without departing from the gist of the present invention. For example, the following modifications can be made.

(1) As the electrodes for adjusting the parallelism, generally N (N is an integer of 3 or more) electrodes having the same shape may be provided at symmetrical positions with respect to the measurement electrodes. In this case, the AC applied signal applied to each electrode is a symmetric N-phase signal having the same frequency and electromotive force and different phases by 2π / N. This has the same effect as the above embodiment.

(2) If there is no concern that the parallelism will be lost during the electrical measurement, N AC signals having no phase difference (ie, having the same phase) are applied to the N parallelism adjusting electrodes. It may be applied. In this case, the parallelism is first adjusted using the parallelism adjusting electrode, and the parallelism is maintained.
Electrical measurement is performed using the measurement electrode without applying a signal to the parallelism adjustment electrode. However, if the symmetrical N-phase signal is used as described above, no disturbance is applied to the measuring electrode, and no current due to the applied signal for the parallelism adjustment flows through the semiconductor wafer. There is an advantage that the electrical measurement can be performed with high accuracy while adjusting the temperature. When an AC signal having the same phase is applied to the parallelism adjusting electrode, if the shape of the measuring electrode and the shape of the parallelism adjusting electrode are made equal, the parallelism adjusting electrode can be used as the measuring electrode. Since it can be used, one of the N parallelism adjusting electrodes can be used as a measuring electrode.

(3) The present invention is not limited to CV measurement,
In general, the present invention can be applied to a parallelism adjusting device used for a device for measuring electric characteristics between a measurement electrode and a semiconductor substrate.
As another electrical measurement, for example, there is a method of evaluating the characteristics near the semiconductor surface by examining the time dependency of the combined capacitance Cta by the Zerubst method. Also, L
If the conductance is measured by the CR meter 13,
It is also possible to evaluate an interface state and the like at an interface between the semiconductor substrate 101 and the oxide film 102. Further, during the respective processes such as the cleaning process of the semiconductor substrate, the thermal oxidation process, and the heat treatment for stabilizing the oxide film, if the CV measurement is executed in a state where the oxide film is not formed on the semiconductor wafer, each of these processes can be performed. The quality of the processing can be determined.

[0041]

As described above, in the electric measuring apparatus according to the first aspect, the N parallelism adjusting electrodes have the same shape as each other and are located at positions symmetrical to each other with respect to the measuring electrodes. Since it is provided, an equivalent circuit composed of the measuring electrode and the N parallelism adjusting electrodes has a symmetric load of a star connection centering on the measuring electrode. Since a symmetric N-phase AC signal is applied to the N parallelism adjusting electrodes,
The measurement condition of the capacitance in each parallelism adjusting electrode becomes equal, and the potential of the measuring electrode is kept equal to the potential of the neutral point of the AC power supply. Therefore, even if an AC signal for adjusting the parallelism is applied, it does not disturb the measuring electrode. Therefore, it is necessary to adjust the parallelism by the parallelism adjusting means while performing accurate electrical measurement with the measuring electrode. There is an effect that can be.

Also, in the parallelism adjusting device according to the second aspect, N
Since N AC signals having the same phase are applied to the parallelism adjusting electrodes, the measurement conditions of the capacitances at the respective parallelism adjusting electrodes are equal. Therefore, there is an effect that the parallelism can be accurately adjusted by the parallelism adjusting means comparing the capacitances of the respective parallelism adjusting electrodes.

[Brief description of the drawings]

FIG. 1 is a conceptual diagram showing an outline of a method for measuring electricity of a semiconductor. ,

FIG. 2 is a diagram showing a configuration of an electricity measuring device as one embodiment of the present invention.

FIG. 3 is a diagram showing an arrangement of electrodes in the embodiment.

FIG. 4 is an explanatory diagram showing an equivalent circuit between electrodes.

FIG. 5 is a diagram showing a basic connection relationship between an AC power supply and a parallelism adjusting electrode.

FIG. 6 is a diagram showing a connection relationship between an AC power supply, a parallelism adjustment electrode, and a capacitance meter.

FIG. 7 is a graph showing the relationship between the inclination of the bottom surface of a prism and the capacitance of a parallelism adjusting electrode.

FIG. 8 is a graph showing the relationship between the inclination of a prism and the capacitance of each parallelism adjusting electrode.

FIG. 9 is a diagram showing another arrangement of electrodes.

[Explanation of symbols]

 Reference Signs List 3 base 41 prism 41a bottom surface 5 laser oscillator 6 light receiving sensor 7 sample table 21-23 piezoelectric actuator 100 semiconductor wafer 101 semiconductor substrate 102 oxide film 111-113 parallelism adjusting electrode 130 three-phase AC power supply 131-133 capacity meter 201 measurement electrode

Claims (2)

(57) [Claims] An apparatus for measuring electrical characteristics of a semiconductor wafer, comprising: a measurement electrode held on a predetermined electrode holding surface with a gap between the semiconductor electrode and a surface of the semiconductor wafer; Measuring means for measuring electric characteristics between the semiconductor wafer and N pieces of the same shape (N is an integer of 3 or more) provided at symmetrical positions with respect to the measuring electrode on the electrode holding surface; And the N parallelism adjusting electrodes, the frequency and the electromotive force are equal to each other and the phases are different by 2π / N.
An AC power source for applying a phase AC signal, and the capacitance between each of the N parallelism adjusting electrodes and the semiconductor wafer are measured based on the symmetric N-phase AC signal. An electrical measurement apparatus for a semiconductor wafer, comprising: a parallelism adjusting unit that adjusts the parallelism between the electrode holding surface and the surface of the semiconductor wafer based on a comparison result of the capacitance. 2. A parallelism adjusting device for a semiconductor wafer electric measuring device, wherein an electrode holding surface held with a gap between the electrode holding surface and a surface of the semiconductor wafer, and a symmetry between the electrode holding surface and the electrode holding surface. (N is an integer of 3 or more) having the same shape and having the same frequency and the same electromotive force with respect to the N parallelism adjusting electrodes provided at different positions. An AC power supply for applying N AC signals of the phase and capacitance between each of the N parallelism adjusting electrodes and the semiconductor wafer are measured based on the AC signal, and the static electricity is measured. A parallelism adjusting device comprising: a parallelism adjusting unit that adjusts the parallelism between the electrode holding surface and the surface of the semiconductor wafer based on a comparison result of the capacitance.