JP2770335B2 - Method of manufacturing MOS type semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a memory cell region including a MOS semiconductor memory cell and a self-substrate potential generating circuit (hereinafter abbreviated as BBG;
ias generator).

[Prior Art] Conventionally, in a MOS type semiconductor memory device, an oxide film for element isolation (hereinafter referred to as a field oxide film) and a gate between the BBG region and the memory cell region on a semiconductor substrate are formed. A MOS transistor (hereinafter referred to as VT2) serving as an oxide film is formed.

FIG. 4 is a sectional view showing a memory cell and a field oxide film in a memory cell region in a conventional MOS type semiconductor memory device.

On the display of the P-type silicon substrate 6, an N ⁺ diffusion layer 9 to which the output electrode 8 in the BBG formation region is connected is formed. The BBG injects carriers from the N ⁺ diffusion layer 9 into the semiconductor substrate 6 to keep the substrate potential constant. On the other hand, in the memory cell region, N ⁺ diffusion layers 15 are formed on the side surfaces and the bottom surface of the trench 13 of the memory cell, and the inside of the trench 13 is filled with the polycrystalline silicon region 12. Reference numeral 14 denotes a transfer gate of the memory cell, and reference numeral 18 denotes a protective film. A field oxide film 10 and a VT2 having the field oxide film as a gate oxide film are formed between the BBG region and the memory cell region.
The region and the memory cell region are insulated and separated.

[Problems to be Solved by the Invention] However, recently, high-speed and high-density semiconductor devices have been promoted, so that the BBG region and the memory cell region are arranged closer to each other. became. For this reason, the conventional insulation separation using the field oxide film and VT2 is not sufficient, and carriers injected into the substrate 6 from the output of the BBG via the diffusion layer 9 may reach the memory cell region. When such a situation occurs, the information stored in the memory cell will be lost.

The present invention has been made in view of such a problem, and is arranged even when the BBG and the memory cell area are close to each other, and the VT2
The threshold voltage of the memory cell is reduced and the information of the memory cell is not lost by the carrier injected from the BBG output.
It is an object of the present invention to provide a MOS semiconductor memory device suitable for high integration.

[Means for Solving the Problems] A method of manufacturing a MOS semiconductor memory device according to the present invention is directed to a MOS semiconductor memory device in which a trench memory cell and a self-substrate potential generation circuit are formed in a semiconductor substrate of one conductivity type. Forming a plurality of trenches at predetermined intervals using the same pattern as the trenches of the memory cell between the memory cell forming region and the self-substrate potential generating circuit, Forming a diffusion layer of the opposite conductivity type on the side and bottom surfaces of the plurality of trenches; and forming a wiring connected to the diffusion layer of the opposite conductivity type and holding the diffusion layer at a constant potential. In the present invention, a trench is arranged in a semiconductor substrate between a BBG formation region and a memory cell formation region, and a diffusion layer is formed on the side and bottom surfaces of the trench. Then, the diffusion layer is maintained at a constant voltage via a wiring connected to the diffusion layer. As a result, of the carriers injected into the substrate from the output of the BBG, those going to the memory cell region are captured by the diffusion layers on the side and bottom surfaces of the trench, and do not reach the memory cell. Therefore, BBG
Thus, loss of information stored in the memory cell can be prevented.

Example Next, an example of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a plan view showing a pattern according to a first embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along a line II-II in FIG.

In the MOS semiconductor memory device 1 according to the present embodiment,
A groove region 4 is arranged between the memory cell formation region 2 and the BBG 3.

The output electrode 8 of the BBG 3 is connected to an N ⁺ diffusion layer 9 formed on the surface of the P-type silicon substrate 6. The BBG 3 injects carriers from the N ⁺ diffusion layer 9 The potential is kept constant. This potential is usually -3 to
4V.

The trench type memory cell in the memory cell region 2 has N ⁺ diffusion layers on the side and bottom surfaces of the trench 13 formed in the substrate 6.
15 is formed and driven by the transfer gate 14. The inside of trench 13 is filled with polycrystalline silicon region 12. A trench 7 is formed in the substrate 6 between the trench 13 and the N ⁺ diffusion layer 9 in addition to the field oxide film 10. The trench 7 is formed at a predetermined depth on the surface of the substrate 6, and an N ⁺ diffusion layer 15a is formed in a region of the trench 7 on the substrate 6 side. The N ⁺ diffusion layer 15a is formed so as to extend slightly to the surface of the substrate 6 in addition to the side and bottom surfaces of the trench 7. On the other hand, an oxide film 17 is formed on the side and bottom surfaces of the trench 7, and the inside of the trench 7 is filled with a polycrystalline silicon region 16.

Further, a metal wiring 11 is formed on the substrate 6,
This metal wiring 11 is connected to N ⁺ diffusion layer 15a. The metal wiring 11 is connected to a constant power supply (for example, GND), so that the N ⁺ diffusion layer 15a is kept at a constant potential (GND). Reference numeral 18 denotes a protective film of each element.

In the MOS type semiconductor memory device thus configured, the carriers injected into the substrate 6 from the output electrode 8 of the BBG via the N ⁺ diffusion layer 9 toward the memory cell region 2 N ⁺ held at a constant potential (GND)
It is captured by the diffusion layer 15. Therefore, the carrier does not reach the memory cell region 2. Therefore, the information stored in the trench memory cell is not destroyed.

FIG. 3 is a plan view showing a second embodiment of the present invention.
The structure of the cross section indicated by the line II-II in FIG. 3 is the same as that of FIG. 2 of the first embodiment.

In the first embodiment, the groove region 4 disposed between the memory cell region 2 and the formation region of the BBG3 has a rectangular planar pattern, and is orthogonal to the line connecting the memory cell region 2 and the BBG3. Direction, but this second
In the embodiment, the groove region 5 having a short length is
A plurality (three in the illustrated example) are arranged at regular intervals between each other in a direction perpendicular to the line connecting BBG3.

By forming the groove region 5 in such a shape and arrangement, for example, when each memory cell in the memory cell region 2 is a trench memory cell, the same pattern as each memory cell in the memory cell region is used. The trench 7 for insulating separation can be formed.

Also in this embodiment, the same effect as in the first embodiment can be obtained for the insulating and isolating effect of the trench region 5, and the size of the trench of the trench region 5 is the same as that of the trench of each memory cell in the memory cell region 2. And there is an advantage that the formation of the pattern of the groove region 5 is easy.

[Effects of the Invention] As described above, according to the present invention, even if the BBG and the memory cell region are arranged close to each other and the threshold voltage of VT2 is reduced, carriers injected from the BBG output to the substrate are reduced. As a result, loss of information in the memory cell 1 is reliably avoided, which is extremely useful for high integration of the MOS semiconductor memory device.

[Brief description of the drawings]

FIG. 1 is a pattern plan view showing a first embodiment of the present invention,
FIG. 2 is a cross-sectional view of a portion indicated by line II-II in FIG.
FIG. 3 is a pattern plan view showing a second embodiment of the present invention,
FIG. 4 is a sectional view showing a part of a conventional MOS type semiconductor memory device. 1; semiconductor memory device, 2; memory cell region, 3; BBG, 4, 5; trench region, 6; P-type silicon substrate, 7; trench, 8; BBG output electrode, 9, 15, 15a; N ⁺ diffusion layer Field oxide film, 11; metal wiring, 12, 16; polycrystalline silicon region, 13; memory cell trench, 14; transfer gate, 17; oxide film, 18; protective film

Claims (1)

(57) [Claims] 1. A method of manufacturing a MOS type semiconductor memory device in which a trench type memory cell and a self-substrate potential generating circuit are formed on a semiconductor substrate of one conductivity type. Forming a plurality of trenches at predetermined intervals using the same pattern as the trenches of the memory cell, and forming opposite conductivity type diffusion layers on side and bottom surfaces of the plurality of trenches. A method for manufacturing a MOS type semiconductor memory device, comprising: a step of forming a wiring connected to the opposite conductivity type diffusion layer and holding the diffusion layer at a constant potential.