JP2769296B2 - Semiconductor die package and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to integrated circuit (IC) package design. In particular, it relates to an apparatus and method for providing a package that effectively connects an integrated circuit die (semiconductor die) to a printed circuit board (PCB).

[0002]

Has BACKGROUND ART IC is more circuits, using a wider silicon area, becomes to operate at a higher clock frequency, accordingly, the package to be surface mounted on the IC, the more and more It is necessary to have leads, smaller footprints and higher electrical / thermal properties, while at the same time having at least previously accepted standard reliability. Conventional TAB (tape automated b)
A package using the method of bonding or a lead frame exhibits sufficient thermal / electrical characteristics at about 10 watts with about 300 leads and can operate at 50 MHz. However, when the number of leads exceeds 300, the lead pitch (that is, the distance between leads) must be shorter than 0.5 mm in order to avoid an increase in footprint (area occupied on the board). . As the footprint increases, high-density mounting of the board becomes impossible. This is important for many products, but especially for portable, consumer-oriented products, where in such products, functioning in a limited space is a competitive issue. This is a great advantage for Conversely, reducing the lead pitch requires expensive positioning equipment and difficult assembly methods.
Furthermore, from a product design point of view, PCBs require more signal layers and vias to use packages with shorter lead pitch. These factors reduce the yield in the manufacturing process,
This leads to an increase in the cost of CB.

In response to a demand for an IC package having a larger number of leads and a smaller footprint, a ball grid array (Ball Grid Array) has been developed.
Array: BGA) was developed. The BGA package eliminates the need for shorter lead pitches and reduces the package footprint. The BGA package is a surface mount package and is incorporated into an external PCB or "mother PCB" using a two-dimensional array of solder balls instead of in-line leads with short lead pitch, which are susceptible to damage during assembly. The advantages of a BGA package are a small footprint, a large ball grid array pitch, and a relatively simple mounting process to an external PCB, which is almost self-alignable. For example, the number of leads is 208 and the thickness is 2 m
The typical footprint size of a m QFP (Quad FlatPack) is 32 × 32 mm and the lead pitch is 0.5 mm. On the other hand, a 212-pin BGA
Package thickness is 1.5mm, footprint is 2
It is 7 × 27 mm and a ball pitch of 1.5 mm is used. At least BGA packages require a double-sided metal layer PCB substrate instead of a lead frame or TAB. Such a BGA package is typically a "cavity-up package", which is mounted such that the backside of the semiconductor die is adhered to the top surface of the substrate (ie, the upward facing surface). A typical substrate is a PCB. The die is wire bonded to the substrate traces and overmolded. When mounted on an external PCB, a two-dimensional array of solder balls is bonded to metal traces that originate a path on the top surface of the substrate on the exposed back surface of the substrate (ie, the downward facing surface of the substrate).

On August 4, 1992, Motorola (Mo)
torolla Inc. ) Attached to "Overmo
led Semiconductor Package
US Pat. No. 5,136,366 entitled "With Anchoring Means"
An example of a package is described. The main limitations of conventional BGA packages are low power dissipation, limited electrical properties, and susceptibility to moisture.

The power dissipation of conventional BGA packages is limited to 3 watts or less. This is because the heat generated by the semiconductor die is conducted from the back of the IC to the external PCB through the package substrate. A solder ball under the IC may be used to promote power dissipation. However, in order to dissipate the power using the solder ball, the external P
It is necessary for the CB to have a ground plane, which limits the signal routing space on the PCB and increases the cost of the board.

Further, the operating frequency, which is a measure of the electrical characteristics, is much lower than 50 MHz in the conventional BGA package. The poor electrical characteristics are due to the large inductance of the trace passing from the top surface of the substrate to the edge of the substrate and further to the back surface for connection with the solder balls. This wrap around of the traces is due to the inability of current PCB technology to provide sufficiently fine lines between the ball pads to pass the traces, and to connect the substrate to the plating bars around the package. And the need to electroplate the traces.

[0007] Conventional BGA packages are more susceptible to moisture than traditional plastic molded packages, because the PCB substrate of the BGA package absorbs more moisture, and therefore the board Cracking may occur in the package during the assembly process. This is due to the rapid expansion of moisture trapped in the package during or after incorporation of the BGA package during the high temperature (typically above 200 ° C.) process of incorporating the BGA package into an external PCB board. . Such expansion may cause cracking of the molded article, which is usually caused by the "popcorn phenomenon (p.
known as "opcorning" and can cause package failure. To minimize the amount of moisture that enters the BGA package prior to mounting on an external PCB board, the mounting of the board requires the BGA package to be moisture proof. It is preferable to carry out within several hours after taking out from the bag.

[0008] The electrical properties and heat dissipation of the BGA package can be significantly improved, although the cost is greatly increased by the "cavity down" BGA package. The cavity-down BGA package uses a multilayer PCB substrate having a cavity and capable of reducing electrical parasitic impedance. Such a package improves the electrical characteristics to about 100 MHz. When there is solid metal slag at the bottom of the cavity, the heat dissipation rises to 25 watts. “Cavity down” BGA packaging technology is a well-established printed circuit pin grid array (Printed Circ)
uit Pin Grid Array: PCPGA)
, But the PCPGA package pins are BG
The difference is that the A package is replaced with a solder ball. A major disadvantage of BGA packages is that they are expensive.

Both "cavity up" and "cavity down" BGA packages use wire bonds to electrically connect the die to the substrate. The size of the IC die increases, especially when the die size is limited by the pads, because the wirebond limits how short the pad pitch can be on the IC. ICs whose size is limited by pads become more frequent as circuit density increases, and their typical size is 10 × 10 mm. As the size of the die increases, so does the price. This can be avoided by simply shortening the wire bond pitch,
The current wire bond pitch is about 100 microns,
It looks as if the limit has been reached.

[0010]

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a semiconductor die which is relatively inexpensive, has high electrical characteristics and heat dissipation capability, is resistant to moisture, has high reliability and is small in size. And a method of manufacturing the same.

[0011]

According to the present invention, there is provided a TAB tape, a reinforcing member structure,
An integrated circuit package is provided having a semiconductor die connected via conductive traces on a TAB tape and solder balls for external connection. In one preferred embodiment, the TA
The B tape has an upper (first) dielectric layer and a lower (second) dielectric layer, each dielectric layer having a hole for receiving a semiconductor die. Further, the lower dielectric layer is TA
It has an array of openings that match the conductive pad array of the B-tape so that the solder balls can be bonded to the conductive pads. Semiconductor dies can be connected to a TAB tape by either internal lead bonding or wire bonding.

In the present invention, the reinforcement also plays the role of a heat dissipation plate. Typically, the stiffener has a cavity for receiving a semiconductor die. This cavity is aligned with a hole in the TAB tape for receiving the semiconductor die. The semiconductor die is the back wall of this cavity.
1) and bonded using a heat conductive adhesive. The TAB tape is adhered to the surface of the reinforcement using a thin layer of adhesive, which is similar to the adhesive that bonds the upper and lower dielectric layers of the TAB tape. preferable.

Each semiconductor ball is approximately the same size as the opening in the lower dielectric layer of the TAB tape so that the semiconductor ball can be bonded to a conductive pad. At selected locations in the array of conductive pads, openings are provided in both the conductive pads and the first dielectric layer, and the solder balls at these locations are also joined to the surface of the stiffener to provide grounding. Connection is possible. Such a ground connection provides a small, predictable impedance with low electrical parasitics and extends package performance to 100 MHz.

According to another aspect of the present invention, there is provided a method of manufacturing a package for an integrated circuit. In one embodiment, the conductive traces on the TAB tape are first connected to the corresponding conductive pads on the semiconductor using internal lead bonds.
Subsequently, a semiconductor die is bonded to the back wall of the cavity of the heat dissipation plate using a thermally conductive adhesive. At the same time, the TAB tape is bonded to the heat dissipating plate using a TAB adhesive similar to the adhesive bonding the dielectric layers of the TAB tape together. Both the thermally conductive adhesive and the TAB adhesive cure before the encapsulant is applied to protect the semiconductor die and the internal lead bonds. After the flux is applied, the solder balls are bonded to the conductive pads of the TAB tape. The solder balls are fixed by heat during the reflow process. afterwards,
The use of a cleaning agent removes excess flux from the conductive pads and the integrated circuit package is dried / fired.

In accordance with another aspect of the present invention, there is provided a second method for fabricating an integrated circuit package.
In this method, the conductive pads of the semiconductor die and the conductive traces of the TAB tape are connected by wire bonding. Prior to wire bonding, the semiconductor die and T
The AB tape is adhered to the reinforcement. The ground connection to the stiffener is made by connecting the stiffener to the semiconductor die by wire bonding.

The TAB grid array (TG) according to the present invention
A) The package solves the problem of the conventional BGA package.

The present invention also includes a method and apparatus for connecting a die to an external PCB. A TAB grid array is a high performance, highly reliable two-dimensional array package that overcomes the shortcomings of conventional TAB and BGA packages.

[0018]

The TAB grid array (TGA) according to the present invention
According to the package, the pitch can be shortened by the TAB tape, so that all signals can be routed to the solder balls on the same surface of the tape, thereby shortening the trace and reducing the electric parasitic impedance. can do.

In the present invention, when TAB internal lead bonding is used instead of wire bonding, the pad pitch can be reduced to 50 microns,
The die size has been significantly reduced and the cost has been reduced. By placing the semiconductor die directly on the heat spreader, the thermal properties are greatly improved, reaching up to 25 watts / device.

The sensitivity of a TGA package to moisture is significantly smaller than that of a package using a conventional PCB substrate, because TAB absorbs moisture relatively little. TGA packages are also thinner than conventional BGA packages,
The tape is thinner than the PCB board of the BGA package. Overall, the TGA package according to the present invention also has improved reliability because fewer contacts are used to connect signals from the IC to the wiring board than conventional BGA packages. .

After reading the detailed description using the following examples,
By reference to the accompanying drawings, the objects of the claims and embodiments of the present invention will be appreciated.

[0022]

1 is a sectional view of a TAB grid array (TGA) package 100 according to an embodiment of the present invention. As shown in FIG.
It has closely spaced contacts 102 at a pitch of 0 microns or slightly wider and is embedded in a cavity of a metal heat radiating plate 106. The cavity 125 is filled with a sealing material 104 such as an epoxy resin, which is well known in the art. Semiconductor die 101 is provided with a heat dissipating plate 10 by a thin layer 105 of thermally conductive epoxy resin.
6 is adhered. Contact 102 is conductively connected to the TAB tape 103 by using the inner lead bonding technique. TAB tape 103 has two dielectric layers 1
It includes a signal trace and pad ("conductor") layer 103a held between 09 and 110. The dielectric layer 109 is bonded to the heat dissipation plate 106 by a thin adhesive layer 108. The heat radiation plate 106 also supports the TAB tape 103 and plays a role as a reinforcing material of the TAB tape 103. The TGA package 100 uses a plurality of solder balls (eg, solder balls 111 and 112) to electrically connect the integrated circuit to metal traces on an external printed wiring board (PCB) 150 (not shown). By providing the opening in the dielectric layer 110, the metal trace of the conductor layer 103a of the TAB tape 103 and the external P
Electrical connection with the metal traces of the CB 150 is enabled. For example, the solder ball 112 is connected to the external PCB 150 and T
It is used to connect the conductive pads of the AB tape 103 through the openings in the dielectric layer 110. As another example, openings 114 extend through both dielectric layers 109 and 110, thereby forming a ground connection between external PCB 150 and heat dissipation plate 106 via solder balls 113.

FIG. 2 shows a partially cut-away view of the TAB tape 103. In this embodiment, TAB tape 103 includes a 30 micron thick conductive layer 103a, and two 50 micron thick dielectric layers 109 and 110 on either side of conductive layer 103a. FIG. 2, which is a partially cutaway view, is a top view of the TAB tape 103. For example, at one corner, the dielectric layer 109 is removed and the conductor layer 103 a is exposed. Conductor layer 10
3a extends radially from the central device hole area 120 and includes a number of conductive traces 119 that connect to an array 121 of conductive pads. In this embodiment, the pitch of the pad array 121 is between 600 and 1500 microns and the diameter of each pad is between 100 and 750 microns, depending on the number of pins required by the semiconductor die. Most of the pads in the pad array 121 are fully packed like the pad 117, for example.
Used for signal connection. Other pads, such as 114, have a hole in the center and are used for ground connections.

FIG. 6 shows a method of manufacturing the TGA package 100.
Will be described with reference to FIG. In step 301, the pads of the die are replaced by conventional ultrasonic welding.
Alternatively, it is connected to a free standing tape trace, ie, trace 119, by TAB internal lead bonding by thermocompression. Such techniques are well known in the art and are described, for example, in U.S. Pat. No. 4,878, issued to Jacobi on 27 June 1989.
42,662 "Bumpless Inner Le
In the method shown in "ad Bonding", the bumpless ultrasonic welding method (b) is applied to both the semiconductor die and the TAB tape.
umpress thermosonic bondi
ng). The dielectric layer 109 holds the conductive traces 119 and is perforated only in the pad array 121 at the location of the ground pad. At the position where the ground pad is located, a hole having the same size as the ground pad is provided in the dielectric layer 109. Hole 116 in FIG. 2 is an example of such a hole. The dielectric layer 110 is a conductor layer 103a.
Has an array of openings corresponding to the pads of the pad array 121 of FIG. Each of the dielectric layers 109 and 110 has an internal hole in the central device hole region 120 as shown in FIG. The internal hole receives the semiconductor die, but leaves the internal lead or trace 119 unsupported by a small length for connection.

FIG. 3 is a partially cutaway view of the TGA package 100 of FIG. In this partial cutaway view, the cavity 125 of the heat dissipation plate 106 is exposed for illustration. The heat dissipation plate 106 is made of a thermally conductive material, such as copper, for example, to remove heat dissipated in the semiconductor die. Other suitable materials may be used for the heat dissipation plate 106. Such materials include thin layers of copper / tungsten /
Copper, laminar copper / molybdenum / copper, beryllium oxide, and metallized aluminum nitride. Such aluminum nitride can be metallized with a thin film such as chromium / gold, titanium / gold, nickel / gold. All of these materials have high thermal conductivity and a coefficient of thermal expansion (TCE) about the same as silicon. Heat dissipation plate 106
And TCE of silicon are almost the same,
The occurrence of stress-induced cracking of the die, which tends to occur particularly on large dies (ie dies larger than 10 mm × 10 mm), can be minimized. For small semiconductor dies, the heat dissipation plate 106 may be made of a material with a large TCE difference from silicon (eg, aluminum). As shown in FIGS. 1 and 3, the heat dissipation plate 106 has a cavity 125 surrounding the semiconductor die 101. In this embodiment, the downward surface of the heat dissipation plate 106 (that is, the side opened toward the cavity 125) is covered with a thin film of a metal such as silver or gold, and the metal is coated with solder. Has the property. With this thin film,
After the reflow process, the ground solder balls are mechanically / electrically joined to the heat dissipation plate 106.

In step 302 (FIG. 7), the semiconductor die 1
01 is adhered to the back wall of the cavity 125 via a thin thermally conductive adhesive layer 105. The heat dissipating plate 10 is separated from the semiconductor die 101 by the heat conductive adhesive layer 105.
Heat is transferred to 6 by conduction. The TAB 103 is bonded to the bottom surface of the heat dissipation plate 106 using an appropriate adhesive capable of withstanding a conventional environmental stress test usually performed on an electronic component package. Usually, such an adhesive is T
This is the same as the adhesive used for bonding the conductor layer 103a of the AB tape 103 and the dielectric layers 109 and 110. The hole 120 of the die of the TAB tape 103 is aligned with the cavity 125 with the dielectric layer 109 fixed to the bottom surface of the heat dissipation plate 106. In this embodiment, the semiconductor die 101 and the TAB tape 103 are connected to the heat dissipation plate 106.
The steps of bonding are performed simultaneously in step 302, and the adhesive is simultaneously cured. If desired, four struts, such as struts 128 shown in FIG. 3, are provided at the corners of the heat dissipating plate 106 so that after the reflow process (see below), the height of the solder balls is properly maintained.

In step 303, the encapsulant 104 fills the internal lead bonds on the front side of the semiconductor die and the remaining space in the cavity of the heat dissipation plate. The encapsulant 104 is typically applied in a syringe fashion and surrounds the semiconductor die 101.
The gap between the internal leads allows the encapsulant to flow and fill the die cavity 125 completely and without voids. As a result, the sealing material 104
This protects both the internal lead bonds and the semiconductor die 101 from mechanical and environmental damage. According to this embodiment, the encapsulant cures at 150 ° C. in 3 hours, during which the temperature is ramped up in three stages.

In this embodiment, at step 304, solder balls are bonded to the pads of the pad array 121 exposed by the openings provided in the dielectric layer 110. To join the solder balls to the TGA package 100, a flux is first added to each solder ball, and then the solder balls are placed using a pick-place equipment. Subsequently, the placed solder balls are reflowed at that position by heating to about 200 ° C. using a conventional reflow means using infrared rays or high-temperature air. Excess flux is removed by cleaning the TGA package 100 with a suitable cleaning agent, for example, a water-based cleaning agent. In this process, the solder balls placed on the pads of the pad array 121 in which the holes are also provided in the dielectric layer 109 are reflowed on the heat dissipation plate 106,
A ground connection is established directly between the solder ball and the heat dissipation plate 106. On the other hand, the solder balls placed on the pads of the pad array 121 that are completely packed are connected only to the device pads, and connect signals and power between the solder balls and the traces 119 of the TAB tape. The corresponding pads of the semiconductor die 101 are connected by internal lead bonds. The TGA package 100 is subsequently heated at 120 ° C. for at least 1 hour,
Dry / fired.

The TGA package 100 can be mounted on an external PCB by any suitable conventional surface mounting method and apparatus. In an example of such a surface mounting method, paste-like solder is connected to a connection pad (con
Connection pads, align the solder balls of the TGA package 100 with these connection pads of the PCB, and reflow the solder balls to establish the desired mechanical / electrical connection with the PCB.

This embodiment has many advantages over the conventional BGA package. For example, in this embodiment using a single metal layer (single-metal) TAB tape 103, thereby enabling more frequency characteristic 100 MHz. In addition, the single metal layer TAB tape 103 and the conductive heat dissipating plate 106 form an electrical signal path with low impedance and minimize the uncompensated trace inductance. Such properties are usually achieved only in relatively expensive double metal layer tapes. TAB tape 103 to semiconductor die 10
1 and the external PCB can be mounted on the same side as the TAB tape 103, resulting in a shorter trace length. Further, it is not necessary to wrap around the trace from the back to the front of the substrate, which is required in the conventional BGA package. The combination of TAB tape and connection to the same side of the external PCB and short traces results in significantly lower inductance than conventional BGA packages.

By using TAB internal lead bonding, the present embodiment achieves a shorter pitch compared to wire bonding, thereby making the die designed for an IC whose size is limited by pads smaller. be able to. The smaller die size means lower manufacturing costs. Further, in the TGA package according to the present invention, the electrical connection between the semiconductor die and the external PCB substrate is realized by two contacts, whereas the conventional BGA package requires four contacts. Due to the small number of contacts, the production yield is increased and the reliability of the package is also improved. Furthermore, the TAB tape of the TGA package is a conventional BGA tape.
Because it absorbs only a little moisture compared to the package,
Unlike conventional BGA packages, it is not as sensitive to "popcorn" failures and has higher reliability.

The heat dissipation capacity of the TGA package according to the present invention is much larger than that of the BGA package. In such a TGA package, even if the power dissipated from the semiconductor die is 10 watts without using a heat sink, there is no problem. If a heat sink is used with the TGA package according to the present invention, it is safe to dissipate more than 25 watts under forced air cooling. This heat dissipation capacity indicates that the junction and case have a thermal impedance of less than 0.4 ° C / watt, because the semiconductor die is directly bonded to the heat dissipation plate by a thermally conductive epoxy resin. by.

Another embodiment of a TGA package 200 is shown in FIGS. FIG. 4 is a sectional view of the TGA package 200, and FIG.
2 is a top view of the TAB tape 203 of FIG. The TGA package 200 is generally similar to the TG shown in FIG.
It is the same as the A package 100 except for the following points. In order to facilitate mutual reference between the TGA packages 100 and 200, generally the same parts have the same reference numerals.

In the TGA package 200, the pads of the pad array 121 correspond to the traces of the TAB tape 203,
The connection is made by wire bonding instead of TAB internal lead bonding. Wire bond 21 of FIG.
0a and 210b are examples. In this second embodiment,
The hole 220 (FIG. 5) for the semiconductor die 101 of the TAB tape is slightly larger than the die cavity 125 of the heat dissipation plate 106, thereby slightly exposing the periphery of the heat dissipation plate surrounding the cavity 125. . Instead of internal lead bonding, wire bonding is used, and wire bond 210b is
The semiconductor die 101 is directly grounded to the heat dissipation plate 106 because the semiconductor die 101 is connected to the peripheral portion of the heat dissipation plate 106 surrounding the heat dissipation plate 106.

As shown in FIG.
The internal leads 9 are completely supported by the dielectric layer 109. Unlike the TAB tape 103 of the TGA package 100 in which the internal leads around the die hole 120 are not protected by the dielectric layer 109, the dielectric layer 109 of the TGA package 200 protects the trace 119 all the way to the die hole 220. And the resulting metal trace 11
9 is mechanically supported to establish the necessary support for wire bonding. 10 to 14 show TGA package 2
00 is shown. As shown in FIG.
In step 351, the TAB tape 203 is applied to the thin adhesive layer 12 as described above with reference to the manufacturing method of FIGS.
4 adheres to the heat dissipation plate 106. Step 35
In FIG. 2, after the thin adhesive layer 124 has cured, the semiconductor die 101 is moved into the cavity 125, also as described above.
Is bonded using a heat conductive epoxy resin 105.

In step 353, after the heat conductive epoxy resin 105 is cured, the pads of the semiconductor die 101 are
Trace 1 of TAB tape 203 by wire bond
19 is connected. In this step, the pads of the semiconductor die 101 are also connected to the die holes 220 of the TAB tape 203.
Is connected to the heat dissipating plate 106 by a wire bond. This wire bond is shown in FIG.
Shown as 10a. In step 354, a sealant is applied in a syringe manner to fill the cavity 125 and form a coating that protects both the semiconductor die 101 and the wire bond. The encapsulant 104 of the TGA package can be cured in the same manner as the corresponding encapsulant of the TGA package 100. The solder balls are joined at step 355. Step 355 is substantially the same as step 304 shown in FIG. 9 in the method of manufacturing the TGA package 100.

The main performance difference between TGA packages 100 and 200 stems from the wire bonding of TGA package 200. With the wire bonding of the TGA package 200, the short pitch achieved by the TAB internal bonding of the TGA package 100 cannot be realized. Therefore, semiconductor dies designed by wire bonding and limited in size by pads tend to be larger and have higher manufacturing costs. In addition, the uncompensated impedance of the wire bond is larger than that of the TAB internal lead bond, and the characteristics of the TGA package 200 at the high frequency limit are different from those of the corresponding TGA package 100.
Is inferior in frequency characteristics.

The above detailed description is intended to describe certain embodiments of the invention, and is not intended to limit the invention. Many modifications are possible within the scope of the invention. The invention is defined by the claims.

[0039]

[Brief description of the drawings]

FIG. 1 shows a TAB grid array (TG) using internal bonding of TAB, which is one of the embodiments according to the present invention.
FIG. 1A is a sectional view of a package 100.

FIG. 2 is a partially cutaway view of the TAB tape 103 of FIG.

FIG. 3 is a partially cutaway view of the TGA package of FIG. 1;

FIG. 4 is a sectional view of a TGA package 200 using wire bonding according to a second embodiment of the present invention.

FIG. 5 shows a free-standing (free) TGA package 100;
FIG. 5 is a conceptual diagram of the TAB tape 203 of FIG. 4 without using internal leads.

FIG. 6 is a diagram showing a manufacturing process of the TGA package 100 shown in FIG.

FIG. 7 is a diagram showing a manufacturing process of the TGA package 100 shown in FIG.

FIG. 8 is a diagram showing a manufacturing process of the TGA package 100 shown in FIG.

FIG. 9 is a diagram showing a manufacturing process of the TGA package 100 shown in FIG.

FIG. 10 is a view illustrating a manufacturing process of the TGA package 200 illustrated in FIG. 4;

FIG. 11 is a view showing a manufacturing process of the TGA package 200 shown in FIG. 4;

FIG. 12 is a diagram showing a manufacturing process of the TGA package 200 shown in FIG.

FIG. 13 is a diagram showing a manufacturing process of the TGA package 200 shown in FIG.

FIG. 14 is a diagram showing a manufacturing process of the TGA package 200 shown in FIG.

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 TGA package 101 Semiconductor die 102 Contact 103 TAB tape 103 a Conductive layer 104 Sealant 105 Adhesive layer 106 Heat dissipation plate 108 Adhesive layer 109 Dielectric layer 110 Dielectric layer 111 Solder ball 112 Solder ball 113 Solder ball 114 Opening 116 Hole 117 Pad 119 Trace 120 Center device hole area 121 Pad array 124 Adhesive layer 125 Cavity 128 Support 150 External printed wiring board (PCB) 200 TGA package 203 TAB tape 210a Wire bond 210b Wire bond 220 Hole

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-8-64635 (JP, A) JP-A-6-236940 (JP, A) JP-A-7-297236 (JP, A) JP-A-4- 286145 (JP, A) JP-A-3-297152 (JP, A) JP-A-8-88293 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) H01L 21/60 301- 311 H01L 23/12

Claims (21)

(57) [Claims] 1. A package for a semiconductor die, comprising: (a) a first dielectric layer (109) and a second dielectric layer (11) each having a hole for receiving the semiconductor die.
0) and a TAB tape (103) having a conductive layer (103a) disposed between the first dielectric layer and the second dielectric layer, wherein the second dielectric layer has a plurality of layers. A conductive array comprising a plurality of conductive pads provided such that the conductive layer is aligned with each of the opening arrays of the second dielectric layer. A pad array (121) and conductive traces (119) extending from the hole locations of the first and second dielectric layers to the conductive pad array.
(B) a cavity (1) for receiving the semiconductor die;
25), wherein the cavity is aligned with each of the holes in the first and second dielectric layers for receiving the semiconductor die; and (c) (D) a first adhesive layer (108, 124) for bonding the surface of the first dielectric layer to the reinforcing material in order to bond the TAB tape and the reinforcing material; A plurality of solder balls (112) substantially equal to said openings in said second dielectric layer and bonded to said conductive pads through said openings in said second dielectric layer;
And (e) a second adhesive layer (105) for bonding the semiconductor die to the reinforcing material, wherein the reinforcing material includes a heat conductive material, and the second adhesive layer is A semiconductor die package comprising a conductive epoxy resin. 2. The conductive trace has a free-standing end protruding into the cavity, the semiconductor die has a plurality of connection pads, and the connection pads are the conductive traces of the conductive layer. Having a sealant (104) connected to the free-standing end by a TAB internal lead bonding connection (102) and further filling the cavity of the stiffener and surrounding the semiconductor die and the TAB internal lead bonding connection. The package for a semiconductor die according to claim 1, wherein: 3. The semiconductor die has a plurality of connection pads, the connection pads being connected to the conductive traces of the conductive layer by wire bonding connections (210a), and further comprising the cavities of the stiffener. The package of claim 1, further comprising an encapsulant (104) filling the semiconductor device and the wire bonding connection. 4. A package for a semiconductor die, comprising: (a) a first dielectric layer (109) and a second dielectric layer (11) each having a hole for receiving the semiconductor die.
0) and a TAB tape (103) having a conductive layer (103a) disposed between the first dielectric layer and the second dielectric layer, wherein the second dielectric layer has a plurality of layers. A conductive array comprising a plurality of conductive pads provided such that the conductive layer is aligned with each of the opening arrays of the second dielectric layer. A pad array (121) and conductive traces (119) extending from the hole locations of the first and second dielectric layers to the conductive pad array.
(B) a cavity (1) for receiving the semiconductor die;
25), wherein the cavity is aligned with each of the holes in the first and second dielectric layers for receiving the semiconductor die; and (c) (D) a first adhesive layer (108, 124) for bonding the surface of the first dielectric layer to the reinforcing material in order to bond the TAB tape and the reinforcing material; A plurality of solder balls (112) substantially equal to said openings in said second dielectric layer and bonded to said conductive pads through said openings in said second dielectric layer;
Wherein the reinforcing material comprises a material having a coefficient of thermal expansion substantially equal to that of silicon. 5. A package for a semiconductor die, comprising: (a) a first dielectric layer (109) and a second dielectric layer (11) each having a hole for receiving the semiconductor die.
0) and a TAB tape (103) having a conductive layer (103a) disposed between the first dielectric layer and the second dielectric layer, wherein the second dielectric layer has a plurality of layers. A conductive array comprising a plurality of conductive pads provided such that the conductive layer is aligned with each of the opening arrays of the second dielectric layer. A pad array (121) and conductive traces (119) extending from the hole locations of the first and second dielectric layers to the conductive pad array.
(B) a cavity (1) for receiving the semiconductor die;
25), wherein the cavity is aligned with each of the holes in the first and second dielectric layers for receiving the semiconductor die; and (c) (D) a first adhesive layer (108, 124) for bonding the surface of the first dielectric layer to the reinforcing material in order to bond the TAB tape and the reinforcing material; A plurality of solder balls (112) substantially equal to said openings in said second dielectric layer and bonded to said conductive pads through said openings in said second dielectric layer;
Wherein the reinforcing material comprises: (i) copper, (ii) layered copper / molybdenum / copper, (iii) layered copper / tungsten / copper, (i)
A semiconductor die package comprising: v) a material selected from beryllium oxide and (v) metallized aluminum nitride. 6. The semiconductor die package of claim 5, wherein the metallized aluminum nitride comprises a thin film selected from nickel / gold, chromium / gold, and titanium / gold. 7. A package for a semiconductor die, comprising: (a) a first dielectric layer (109) and a second dielectric layer (11) each having a hole for receiving the semiconductor die.
0) and a TAB tape (103) having a conductive layer (103a) disposed between the first dielectric layer and the second dielectric layer, wherein the second dielectric layer has a plurality of layers. A conductive array comprising a plurality of conductive pads provided such that the conductive layer is aligned with each of the opening arrays of the second dielectric layer. A pad array (121) and conductive traces (119) extending from the hole locations of the first and second dielectric layers to the conductive pad array.
(B) a cavity (1) for receiving the semiconductor die;
25), wherein the cavity is aligned with each of the holes in the first and second dielectric layers for receiving the semiconductor die; and (c) (D) a first adhesive layer (108, 124) for bonding the surface of the first dielectric layer to the reinforcing material in order to bond the TAB tape and the reinforcing material; A plurality of solder balls (112) substantially equal to said openings in said second dielectric layer and bonded to said conductive pads through said openings in said second dielectric layer;
Wherein the reinforcing material has a conductive surface, and the first dielectric layer is one opening selected from the plurality of openings of the second dielectric layer (115). An opening (116) aligned with
The corresponding pad (1 in the conductive pad array)
14), wherein the corresponding pad has an opening connecting the opening of the first dielectric layer and the opening of the second dielectric layer, whereby the second pad is connected to the second dielectric layer by a solder ball (113). A package for a semiconductor die, wherein a conductive path to the reinforcing member is formed through the opening of one dielectric layer and the opening of the second dielectric layer. 8. A package for a semiconductor die, comprising: (a) a first dielectric layer (109) and a second dielectric layer (11) each having a hole for receiving the semiconductor die.
0) and a TAB tape (103) having a conductive layer (103a) disposed between the first dielectric layer and the second dielectric layer, wherein the second dielectric layer has a plurality of layers. A conductive array comprising a plurality of conductive pads provided such that the conductive layer is aligned with each of the opening arrays of the second dielectric layer. A pad array (121) and conductive traces (119) extending from the hole locations of the first and second dielectric layers to the conductive pad array.
(B) a cavity (1) for receiving the semiconductor die;
25), wherein the cavity is aligned with each of the holes in the first and second dielectric layers for receiving the semiconductor die; and (c) (D) a first adhesive layer (108, 124) for bonding the surface of the first dielectric layer to the reinforcing material in order to bond the TAB tape and the reinforcing material; A plurality of solder balls (112) substantially equal to said openings in said second dielectric layer and bonded to said conductive pads through said openings in said second dielectric layer;
Wherein the reinforcing material has a conductive surface plated with a metal having solder wettability. 9. The package of claim 8, wherein said metal is selected from the group consisting of silver or gold. 10. A package for a semiconductor die, comprising: (a) a first dielectric layer (109) and a second dielectric layer (11) each having a hole for receiving the semiconductor die.
0) and a TAB tape (103) having a conductive layer (103a) disposed between the first dielectric layer and the second dielectric layer, wherein the second dielectric layer has a plurality of layers. A conductive array comprising a plurality of conductive pads provided such that the conductive layer is aligned with each of the opening arrays of the second dielectric layer. A pad array (121) and conductive traces (119) extending from the hole locations of the first and second dielectric layers to the conductive pad array.
(B) a cavity (1) for receiving the semiconductor die;
25), wherein the cavity is aligned with each of the holes in the first and second dielectric layers for receiving the semiconductor die; and (c) (D) a first adhesive layer (108, 124) for bonding the surface of the first dielectric layer to the reinforcing material in order to bond the TAB tape and the reinforcing material; A plurality of solder balls (112) substantially equal to said openings in said second dielectric layer and bonded to said conductive pads through said openings in said second dielectric layer;
Wherein the thickness of the first adhesive layer and the first dielectric layer is such that an electrical path whose impedance is reduced by the conductive trace and the reinforcing material is formed. A package for a semiconductor die, which is selected. 11. The method of claim 1, wherein the size of the opening in the second dielectric layer is selected to maintain a predetermined diameter of the solder ball after a reflow process. A semiconductor die package as described. 12. The hole for receiving the semiconductor die is slightly larger than the opening in the cavity of the stiffener, thereby providing a ground connection between the semiconductor die and the stiffener by a wire bond (210b). The semiconductor die package according to claim 1, wherein the semiconductor die package can be formed. 13. The package of claim 1, wherein said first dielectric layer has inner and outer edges that fully support said conductive traces. 14. The package of claim 1, wherein said second dielectric layer has an inner edge exposing said conductive traces by a small length. 15. A method of manufacturing a package for a semiconductor die, comprising: a conductive trace (119) held between a first dielectric layer (109) and a second dielectric layer (110) of a TAB tape (103). A) connecting the semiconductor die to the conductive pad of the corresponding semiconductor die (101) using an internal lead bond (102); and applying the semiconductor die to the back wall (125) of the cavity of the heat dissipation plate (106). Bonding with a conductive adhesive (105); and attaching the TAB tape to the heat dissipation plate with a TAB adhesive (10).
8, 124), curing the thermally conductive adhesive and the TAB adhesive, filling the cavity with the die and the internal lead bond, and covering the semiconductor die and the internal lead bond. (10
4) a sealing step of sealing, a step of curing the sealing material, a step of applying a solder flux to one or more solder balls (111, 112, 113), and a step of attaching the solder balls to the TAB tape. Conductive pad (12
1) bonding, reflowing the solder balls by applying heat, cleaning excess flux from the conductive pads by using an appropriate cleaning agent, and drying / baking the package. And manufacturing the semiconductor die package. 16. The method according to claim 15, wherein a conventional ultrasonic welding method is used in the connecting step. 17. The method according to claim 15, wherein a bumpless internal lead bonding method is used in the connecting step. 18. The method according to claim 1, wherein the sealing step is performed using a sealing material applied in a syringe manner.
6. The method for manufacturing a semiconductor die package according to item 5. 19. A method of manufacturing a package for a semiconductor die, comprising: a heat dissipating plate (1) having a cavity (125) for receiving a TAB tape (103) in a semiconductor die (101);
06) using a TAB adhesive (108, 124); attaching a semiconductor die to the back wall of the cavity of the heat dissipation plate with a thermally conductive adhesive (105); Adhesive and the TAB adhesive (108, 12)
4) curing the TAB tape (103) held between the heat dissipation plate, the first dielectric layer (109) and the second dielectric layer (110).
A conductive trace (119) and a semiconductor die (101)
Wire bond (2) to the corresponding conductive pad (121).
10a, 210b), and filling the cavity with the die and the internal lead bond and covering the semiconductor die and the internal lead bond (10a, 210b).
4) a sealing step of sealing, a step of curing the sealant, a step of applying a solder flux to one or more solder balls, and joining the solder balls to the conductive pads of the TAB tape. A step of reflowing the solder balls by applying heat; a step of cleaning excess flux from the conductive pads by using a suitable cleaning agent; and a step of drying / baking the package. A method of manufacturing a package for a semiconductor die. 20. The method according to claim 1, wherein the sealing step is performed using a sealing material applied in a syringe manner.
10. The method for manufacturing a semiconductor die package according to item 9. 21. The method according to claim 20, wherein the encapsulant is cured in three hours by increasing the temperature in a ramp shape in three stages.