JP2766304B2 - Digital electronic control unit - Google Patents

Description

Description: Object of the Invention (Field of Industrial Application) The present invention relates to a digital electronic control device of a stored program type used for a control device for a spacecraft mounted in an extremely severe power situation. It relates to the object of reduction.

(Prior Art) In general, a digital electronic control device mounted on a spacecraft such as an artificial satellite having severe power consumption restrictions is greatly restricted by the selection of a circuit configuration and elements of a CPU (central processing unit) and a memory portion. . For this reason, the power-on on / off control is performed in a fixed control cycle without constantly supplying power to the core CPU block of the device, thereby lowering the ratio of the control cycle to the CPU operation cycle, thereby reducing the average of the entire system. Techniques for reducing power consumption have been devised.

FIG. 4 shows an example of a digital electronic control unit mounted on a spacecraft. In FIG. 4, a CPU block 11 connects a memory block 12, first to n-th functional blocks 131 to 13n, and a power supply control block 14 through a data bus to an internal RA.
Control is performed according to an instruction program stored in M (read only memory). For such a CPU block 11, the power control block 14 turns on the power switch 15 in response to a start trigger input of a fixed period, and turns off the power switch 15 in response to a power cutoff command issued by the CPU block 11 by itself. The power supply block 16 is selectively connected to the CPU block 11. The power-off command is issued a fixed time after power-on. The blocks 12, 131 to 13n, 14 other than the CPU block 11 receive power supply from the power supply block 16 as needed.

Shows the start trigger is input to each control cycle T ₀ in FIG. 5 (a), CPU for the start trigger in FIG. (B)
The power P _D during the operation period T ₁ of the block 11 and the power during the non-operation period
P _Q, shows the relationship between the average power P _A. In this case, the average power P _A
Is Becomes If designed so that T ₁ / T ₀ ≪1, the average power P
It is possible to reduce the influence of the power P ₀ of the CPU block busy period on _A.

Incidentally, in the above CPU block, it is repeated several tens of thousand steps thousands instruction execution cycles that is determined by the machine cycle during operation period T _1. Therefore, the ROM (read only memory) storing various instruction programs is not operating at the time of instruction execution. From this, even when the CPU block is in operation, the ROM is not
It is desired to switch (strobe) the power supplied to the OM and further reduce the average power during the operation of the CPU block.

(Problems to be Solved by the Invention) As described above, the conventional digital electronic control device merely lowers the average power by operating the CPU block for a certain period in the control cycle, and reduces the average power during the operation period. Power is supplied to the inactive ROM. Therefore, the power consumption of the CPU block during the operation period is high,
In order to reduce the average power, the ratio of the operation period to the control cycle must be further reduced, and the operation period is further reduced.

The present invention has been made in order to solve the above-mentioned problems, and has been made to reduce the average power consumption while reducing the power consumption during the operation period of the CPU block and securing a certain operation period for the control cycle. An object is to provide an electronic control device.

[Structure of the Invention] (Means for solving the problem) In order to achieve the above object, a digital electronic control device according to the present invention has a plurality of instruction data stored therein, and is read-only for reading and outputting designated instruction data. A memory; instruction data designating means for sequentially designating instruction data in the read-only memory during a specific period in a control cycle; and temporarily storing instruction data read from the read-only memory and reading the next instruction data Instruction data holding means for holding instruction data, instruction processing means for decoding and executing the instruction data held by the instruction data holding means,
After the start of the specific period, power is supplied to the read-only memory for a certain period shorter than the specific period, and the instruction data holding unit is supplied with power during a power supply period of the read-only memory, and the instruction processing is performed. The means is provided with a central processing unit including a power supply means for supplying power until the end of the specific period after the power supply to the instruction data holding means is started.

(Operation) In the digital electronic control device having the above-described configuration, in each instruction execution cycle within the operation period of the central processing unit, the power supply period to the read-only memory is described as being smaller than the instruction execution cycle time. The average power consumption within the device can be reduced.

(Embodiment) An embodiment of the present invention will be described below with reference to FIGS.

FIG. 1 shows a CPU of a digital electronic control unit according to the present invention.
The block configuration is shown. CP is a basic clock having a period τ ₀ generated by turning on the power of the CPU block. This basic clock CP is supplied to the program counter 21 and the pulse generator 22. The program counter 21 generates a read address of the ROM 23 according to the basic clock CP, and advances the read address of the ROM 23 by one step at the rising edge of the CP. Pulse generator
Reference numeral 22 is for generating _{first to} third pulses φ ₁ , φ ₂ , φ ₃ having the timing relationship shown in FIG. 2 from the basic clock CP.

In FIG. 2, the first pulse phi ₁ is the basic clock CP
Is generated during the period τ ₁ from the rise of τ ₀ to τ 0/4 and supplied to the ROM 23. Second pulse phi ₂ are supplied to the instruction register 24 is generated in the period tau ₂ to fall of phi ₁ delayed from the rise of phi _1. The third pulse φ ₃ is generated during a period τ ₃ from the fall of φ _{2 to} the fall of CP, and is supplied to the instruction decoder 25.

The ROM 23 stores various control command data for controlling the operation of other functional blocks, and includes a first pulse φ ₁
The power is turned on during the input period of
Instruction data specified by a read address from the program counter 21 is read and output. Instruction register 24 is an operational state with the power to the turned second input period of the pulse phi _2, takes in the instruction data from the ROM 23, the operation code (OP) jump if the field branch type instruction to the instruction decoder 25 ( Program counter 21 in the case of an address field
Is supplied to the preset input terminal of. The instruction decoder 25 becomes the third pulse phi ₃ and power is supplied to the input period operation state of, decodes the instruction data of the operation code input to be executed by the instruction execution cycle, and performs execution operation.

That is, when the basic clock CP rises, the generated address of the program counter 21 advances to the ROM 23 by one step. At this time, ROM 23 is because has an operating state by the first pulse phi _1, instruction data at the specified address is read from the ROM 23, is supplied while the instruction register 24 of tau _1. Here since the instruction register 24 becomes a slightly delayed operating state from ROM23 with the second pulse phi _2, instruction data read from the ROM23 are loaded into the instruction register 24 after stable enough, at the same time the instruction decoder
It is output to 25 or the program counter 21. When the above operations are completed, the ROM 23 stores the first pulse φ ₁
Falls, the power supply is cut off, and the system enters a rest state.

The instruction register 24 supplies the instruction data to the instruction decoder 25 when the loaded instruction data is an operation code, and supplies it to the program counter 21 when the loaded instruction data is a jump address, and presets the address. Once this operation is completed, the instruction register 24 becomes dormant since the second pulse phi ₂ falls, the power supply is cut off. At this time, since the instruction decoder 25 to the third pulse phi ₃ simultaneously rising and falling of the second pulse phi _3, receiving the instruction data from the instruction register 24, decodes the instruction, execution is carried out. When this operation is completed, the instruction decoder 25 outputs the third pulse φ
₃ falls and the power supply is cut off, resulting in a rest state. At the next rise of the basic clock CP, the program counter 21 further advances the read address by one step, so that the instruction data stored in the ROM 25 is sequentially and repeatedly executed.

FIG. 3 shows the relationship among the power P _D during the operation period T ₁ of the CPU block, the power P _Q during the non-operation period, and the average power P _A ′. As can be seen from the figure, the average power in this case is Next, it is possible to reduce the average power of the busy period T ₁ of the CPU block.

Therefore, the digital electronic control device using the CPU block having the above configuration not only reduces the average power by operating the CPU block for a certain period in the control cycle, but also stores instruction data during the operation period. ROM
Also supplies power only when necessary,
The average power consumption of the CPU block during the operation period can be kept low, and the overall average power can be reduced without reducing the ratio of the operation period to the control cycle.

[Effects of the Invention] As described above, according to the present invention, it is possible to reduce the power consumption during the operation period of the CPU block and to reduce the average power while securing a certain operation period for the control cycle. A control device can be provided.

[Brief description of the drawings]

FIG. 1 is a block circuit diagram showing an embodiment of a digital electronic control device according to the present invention, FIG. 2 is a timing diagram showing a timing relationship of pulses used in the embodiment, and FIG. 3 is a power supply of the embodiment. FIG. 4 is a block diagram showing the overall configuration of a digital electronic control unit to which the present invention can be applied, and FIG. 5 is a waveform diagram for explaining a conventional power consumption reducing means. 11… CPU block, 12… Memory block, 131 ~ 13n
... first to n-th functional blocks, 14 ... power control block, 15 ... power switch, 16 ... power block, 21 ...
… Program counter, 22… Pulse generator, 23… RO
M, 24 …… instruction register, 25 …… instruction decoder, CP ……
Basic clock, φ _{1 to} φ ₃ ...... Power-on timing pulse, P _D … Power during operation, P _Q … Power during non-operation, P _A , P
_A ': Average power.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G06F 1/26-1/32 G06F 1/04 G11C 7/00 G11C 11/34 G11C 17/00

Claims (1)

(57) [Claims] 1. A read-only memory for storing a plurality of instruction data and reading and outputting designated instruction data, and an instruction data designation for sequentially designating instruction data to the read-only memory during a specific period in a control cycle. Means, instruction data holding means for temporarily storing instruction data read from the read-only memory and holding it until the next instruction data is read, and decoding and executing the instruction data held by the instruction data holding means. An instruction processing means for supplying power to the read-only memory for a fixed period shorter than the specific period after the start of the specific period, and supplying the instruction data holding means with power during a power supply period of the read-only memory; After the power supply to the instruction data holding unit is started, the power is supplied to the instruction processing unit until the end of the specific period. A digital electronic control unit comprising a central processing unit having a power supply means.