JP2766177B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a structure of a source region, a drain region and a channel region and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, rapid integration and densification of semiconductor devices, particularly MOS transistors, have been remarkable, but this is largely due to advances in photolithography and etching techniques.

As shown in the cross-sectional view of FIG. 3, a conventional MOS transistor has a source 14A and a drain 14B made of an N-type diffusion layer on a surface of a P-type silicon substrate 1 having a crystal plane (100) or (511). Is formed thereon, and a gate electrode 9 made of metal such as aluminum, polysilicon or silicide is formed thereon via a gate insulating film 8A made of a silicon oxide film or the like, and a silicon oxide film or a silicon nitride film or the like is formed thereon. Is formed, an opening is formed in the insulating film, and then a source electrode 11 and a drain electrode 12 are formed.

In the MOS transistor thus formed, the channel length is reduced in order to improve the channel conductance and increase the driving capability of the device. That is, if the channel length is L, the channel width is W, the density of carriers induced on the silicon substrate surface is Q, and the carrier mobility of the channel is μ, the channel conductance g is expressed as g = [W / L] Qμ. Therefore, reducing the channel length L is important for improving the driving capability of the MOS transistor. For example, circuit delay time by Applying scaling law the channel length to 1 / K times becomes capable of high-speed operation becomes 1 / K times, also the power consumption is significantly reduced ^doubles 1 / K. For these reasons, the structure of the MOS transistor itself has been miniaturized.

[0005]

The channel length of a MOS transistor has been reduced with the progress of photolithography and etching techniques. For example, 0.6
The fine technology at the level of 0.3 μm is the lithography technology that employs i-line / excimer laser stepper, DUV reflection projection exposure, high NA lens, wide field size, and EC.
R, magnetron RIE, improved RIE, etc. However, these techniques require a great deal of cost and man-hours to achieve optimization and compounding, and have the disadvantage that the channel length of a MOS transistor cannot be easily reduced.

An object of the present invention is to provide a semiconductor device in which the channel length is simply reduced and the driving capability is improved, and a method of manufacturing the same.

[0007]

According to a first aspect of the present invention, there is provided a semiconductor device including a second conductivity type diffusion layer formed on one main surface of a first conductivity type semiconductor substrate and an end of the diffusion layer. A groove formed more deeply in the substrate, a first epitaxial layer of a first conductivity type formed on at least a side surface of the groove on the diffusion layer side and having an upper surface flush with the substrate; A second conductivity type second epitaxial layer formed on the first epitaxial layer and filling the groove and having a surface flush with the substrate; and a gate insulating film on the first epitaxial layer surface. And a formed gate electrode.

According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of: selectively forming a second conductivity type diffusion layer on a surface of a first conductivity type semiconductor substrate; Forming a groove deeper than the diffusion layer, and sequentially forming a thin first epitaxial layer of the first conductivity type and a thick second epitaxial layer of the second conductivity type on the entire surface including the groove, and filling the groove. Etching the second and first epitaxial layers on the substrate to expose one end of the first epitaxial layer and the diffusion layer and planarize the surface; and exposing the exposed first epitaxial layer. Forming a gate oxide film on the surface of the layer.

[0009]

Next, embodiments of the present invention will be described with reference to the drawings. 1A to 1D are cross-sectional views of a semiconductor chip for explaining a first embodiment of the present invention.

First, as shown in FIG. 1A, a buffer silicon oxide film 2 is formed on a P-type silicon substrate 1 having a crystal orientation plane (100). Next, a photoresist film 3 is formed, and then patterned to form a drain (or source).
An opening for forming is provided. Next, this photoresist film 3
Is used as a mask, and arsenic (As) as an N-type impurity is ion-implanted under the condition of a dose amount of 10 ¹² cm ⁻² .

Next, as shown in FIG. 1 (b), after removing the photoresist film, a heat treatment is performed to activate the introduced impurities and at the same time to push the same into the diffusion layer to a depth of 0.2 μm.
An N-type diffusion layer 4 having an impurity concentration of about 10 ²⁰ cm ⁻³ is formed. Next, using a photoresist film having an opening for forming a groove as a mask, the silicon oxide film 2 is removed with an HF solution, and then silicon is removed using an anisotropic etching solution composed of a mixed solution of ethylenediamine and pyrocatechol. The substrate 1 is etched to form a groove 5A having a depth of 1.0 μm and a width of about 3.0 μm, which is in contact with the end of the N-type diffusion 4 and is deeper than the diffusion layer 4. The slope of the groove 5A thus formed has a plane orientation (11
1), and a taper is formed.

Next, after removing the photoresist film used for forming the groove, the silicon oxide film 2 is removed with an HF solution. Next, a P-type epitaxial layer 6A having a thickness of 0.4 μm and an impurity concentration of 10 ¹⁵ cm ⁻³ and an N-type epitaxial layer 7A having a thickness of 1.0 μm and an impurity concentration of 10 ²⁰ cm ⁻³ are formed on the entire surface by molecular beam epitaxy (MBE). The method is performed to suppress auto doping and redistribution of impurities at a temperature of about 600 ° C. to fill the groove 5A. Since the MBE method enables film formation for each atomic layer, the film thickness can be sufficiently suppressed. The formation of these epitaxial layers is performed by a photo-excitation method and a low temperature (700 to 800).
C.), a growth method in which a CVD method in a high vacuum is combined, or the like can be used.

Next, as shown in FIG. 1C, an appropriate smooth surface forming technique, for example, reactive ion etching (RI)
E) or unnecessary epitaxial layers 7 and 6 on the surface of the silicon substrate 1 are removed by a chemical / physical polishing method. If a defect is introduced into the surface of the silicon substrate 1 by this step, a step of performing low-temperature heat treatment, for example, performing solid phase growth of a crystal at a temperature of about 700 ° C., and simultaneously performing thermal oxidation to remove the surface defect is provided. You may. Further, if necessary after this step, in order to obtain a sub-threshold and threshold voltage characteristic, a shallow ion implantation of a dose of about 10 ¹² cm ⁻² is performed to suppress the impurity concentration on the surface of the silicon substrate 1. Transistor characteristics can be obtained.

Next, a thin gate oxide film 8 having a thickness of 15 to 20 nm is formed on the surface of the silicon substrate 1 by a thermal oxidation method.
After that, an N-type polysilicon layer is formed while doping impurities such as phosphorus by a vapor phase growth method, and then patterned to form a gate electrode 9A.

As shown in FIG. 1D, a silicon oxide film 10 is formed on the entire surface, an opening is formed, an Al film or the like is formed, and patterning is performed to form a source electrode 11A and a drain electrode 12A. To complete the MOS transistor. In the present embodiment, the N-type diffusion layer 4 having a shallow diffusion depth is used as the drain and the N-type epitaxial layer 7A is used as the source because of the withstand voltage and hot electron resistance.

The MOS transistor thus configured in the first embodiment has the following features as compared with the prior art.

That is, the channel (gate) region of the MOS transistor is formed by epitaxial growth, and the thickness of this epitaxial layer 6A becomes the gate channel length. Thus, the size of the gate channel length is determined by the uniformity of the epitaxial growth rate, as opposed to being limited by the overlay accuracy by lithographic printing found in the prior art. As is well known, the thickness of the growth layer formed by the MBE method and the gas phase reaction method can be accurately controlled, so that the gate channel length can be easily reduced.

FIG. 2 is a sectional view of a semiconductor chip for explaining a second embodiment of the present invention.
A different point from the embodiment of the present invention is that a vertical groove is formed and this groove is
That is, a channel region and a source are formed by filling the channel region and the N-type epitaxial layer.

That is, after forming an N-type diffusion layer 4 having a depth of 0.2 μm on a P-type silicon substrate 1 in the same manner as in the first embodiment, RIE is performed using a mask made of a photoresist film.
The silicon oxide film 2 and the silicon substrate 1 are etched by a method, and a depth of 1.0 μm and a width of 2.0
A groove 5B of μm is formed in contact with the end of the diffusion layer 4. For example, gas of CF ₄ + H ₂ is used for etching the silicon oxide film 2, and CCl ₄ + O ₂ is used for etching the silicon substrate.
Gas is used.

Next, after removing the photoresist film used for forming the groove, the silicon oxide film 2 is removed with an HF solution. Next, vacuum degree 100-1000Pa, temperature 700-800 ° C
In addition, a P-type epitaxial layer 6B and an N-type epitaxial layer 7B are continuously formed on the entire surface by a chemical vapor deposition (CVD) method of irradiating an ultraviolet ray for exciting the reaction gas to fill the groove 5B. As in the first embodiment, the thickness of the P-type epitaxial layer 6B at this time is 0.4 μm, the impurity concentration is 10 ¹⁵ cm ⁻³ , the thickness of the N-type epitaxial layer 7B is about 1 μm, and the impurity concentration is 10 ²⁰ cm ^{−. 3} Hereinafter, similarly to the first embodiment, the gate oxide film 8, the silicon oxide film 10,
Gate electrode 9B, source electrode 11B and drain electrode 1
2A is formed to complete the MOS transistor.

In the second embodiment, since the groove 6B is formed vertically, there is an advantage that the element region can be reduced.

[0022]

As described above, according to the present invention, after a diffusion layer serving as a drain is formed in a semiconductor substrate, a groove is provided in a substrate including one end of the diffusion layer, and a channel region and a source are formed in the groove. By forming the epitaxial layer, the gate channel length of the MOS transistor can be easily reduced. For this reason, channel conductance can be increased, and a semiconductor device with improved driving capability can be obtained.

[Brief description of the drawings]

FIG. 1 is a sectional view of a semiconductor chip for explaining a first embodiment of the present invention.

FIG. 2 is a cross-sectional view of a semiconductor chip for explaining a second embodiment of the present invention.

FIG. 3 is a cross-sectional view of a semiconductor chip for describing a conventional semiconductor device.

[Explanation of symbols]

 Reference Signs List 1 P-type silicon substrate 2 Silicon oxide film 3 Photoresist film 4 N-type diffusion layer 5A, 5B groove 6A, 6B P-type epitaxial layer 7A, 7B N-type epitaxial layer 8 Gate oxide film 8A Gate insulating film 9, 9A, 9B Gate Electrode 10 Silicon oxide film 10A Insulating film 11, 11A, 11B Source electrode 12, 12A, 12B Drain electrode 14A Source 14B Drain

Claims (3)

(57) [Claims] A second conductivity type diffusion layer formed on one main surface of the first conductivity type semiconductor substrate; a groove formed on the substrate including an end of the diffusion layer and deeper than the diffusion layer; A first epitaxial layer of the first conductivity type formed on at least a side surface of the groove on the diffusion layer side and having an upper surface flush with the substrate;
A second epitaxial layer of a second conductivity type formed on the first epitaxial layer and filling the trench and having a surface flush with the substrate; and a gate insulating film on the surface of the first epitaxial layer. And a gate electrode formed through the semiconductor device. 2. The semiconductor device according to claim 1, wherein the second conductivity type diffusion layer is a drain of a MOS transistor. 3. A step of selectively forming a second conductivity type diffusion layer on a surface of a first conductivity type semiconductor substrate, and a step of forming a groove deeper than the diffusion layer in the substrate including an end of the diffusion layer. Forming a thin first epitaxial layer of a first conductivity type and a thick second epitaxial layer of a second conductivity type sequentially over the entire surface including the groove to fill the groove; Etching a first epitaxial layer to expose one end of the first epitaxial layer and the diffusion layer and to planarize the surface;
Forming a gate oxide film on the surface of the epitaxial layer.