JP2765588B2 - Encoding / decoding device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] Regarding an encoding / decoding device, a portion that can be shared between an encoding unit and a decoding unit is shared, and the processing capability of the encoding unit on the transmission side and the decoding unit on the reception side For the purpose of maximizing the effective use of the hardware of the entire device in accordance with the margin of the device and reducing the size of the hardware, the data signal to be transmitted is coded and transmitted, and the coded data signal is transmitted. In an encoding / decoding device that receives and decodes a data signal, a difference calculation unit, an encoding unit, first to third changeover switches, a control unit, a decoding unit, an addition unit, The control unit includes an encoding unit memory and a decoding unit memory, and switches the first and third changeover switches to a transmission side or a reception side during transmission and reception, respectively. At the time of transmission, A difference calculating unit for calculating a difference between the input signal and a value held in the coding unit memory, the coding unit coding the output of the difference calculation unit and outputting the result as coefficient data; A decoding unit that decodes the coefficient data, the adding unit obtains a sum of an output of the decoding unit and a value held in the encoding unit memory, and the encoding unit memory Holding the output of the unit, at the time of reception, the decoding unit decodes the received coefficient data, the addition unit, the addition unit of the output of the decoding unit and the value held in the decoding unit memory The sum is obtained as an output signal, and the decoding unit memory is configured to hold the output of the adding unit.

[Industrial applications]

 The present invention relates to an encoding / decoding device.

For example, in a low bit rate image coding transmission system, information transmission at a low bit rate is enabled by using various information compression systems.

In order to perform such information transmission, the transmission / reception device includes an encoding / decoding device. However, the complexity of the processing increases the hardware scale, and thus the power consumption is large. There is a problem that the calorific value is large.

Further, in general, the information amount of transmission and reception greatly fluctuates with time, but the maximum processing capacity of the encoding / decoding device depends on the maximum reception information processing amount input to the decoding unit of the encoding / decoding device. Therefore, when the amount of received information becomes small due to the above fluctuation,
This means that the capacity of the decoding unit of the decoding device is not being used effectively.

[Problems to be solved by conventional technology and invention]

In the conventional encoding / decoding device, the encoding process is performed independently on the transmitting side, and the decoding process is independently performed on the receiving side. there were.

FIG. 4 shows a schematic configuration of an example of an encoding unit in a conventional image encoding / decoding device, and FIG. 5 shows a schematic configuration of an example of a decoding unit in a conventional image encoding / decoding device. It is.

In FIG. 4, 60 is a subtraction circuit, 61 is an encoding circuit, 62
Is a quantization circuit, 63 is a decoding circuit, 64 is an inverse quantization circuit, 65
Is an addition circuit, and 66 is a memory.

The input signal is subtracted from the value held in the memory 66 by the subtraction circuit 60, encoded by an encoding circuit 61 (in this example, a cosine transform encoding circuit DCT), and quantized by a quantization circuit 62. And output as coefficient data. The coefficient data is decoded in a decoding circuit 63, inversely quantized in an inverse quantization circuit 64, and a sum with a value held in a memory 66 is obtained in an addition circuit 65. Is held.

In FIG. 5, 47 is a decoding circuit, 48 is an inverse quantization circuit, 49 is an addition circuit, and 50 is a memory.

The received coefficient data is decoded in a decoding circuit 47, inversely quantized in an inverse quantization circuit 48, a sum with a value held in a memory 50 is obtained in an addition circuit 49, and output as an image signal. You. This sum is stored in the memory 50.

As shown in FIGS. 4 and 5, in the conventional encoding / decoding device, the configurations of the encoding unit on the transmitting side and the decoding unit on the receiving side are provided independently of each other. It is necessary to provide a processing function corresponding to each maximum processing information amount on each of the transmission side and the reception side, so that the hardware scale becomes large, and each of the transmission side and the reception side has a capability due to the fluctuation of the processing information amount. However, there is a problem that each ability is not effectively used when there is a margin.

The present invention has been made in view of the above-described problems, and has been made in consideration of the above-described problem. Accordingly, it is an object of the present invention to provide an encoding / decoding device that makes the most of the hardware of the entire device to be used as efficiently as possible, and that has a reduced hardware scale.

[Means for solving the problem]

FIG. 1 is a basic configuration diagram of an encoding / decoding device according to the present invention.

In FIG. 1, 1 is a difference operation unit, 2 is an encoding unit,
7, 7 and 10 are changeover switches, 4 is a control unit, 5 is a decoding circuit unit, 6 is an addition unit, 8 is an encoding unit memory, 9 is a decoding unit memory, and 11 is a transmission / reception margin comparing unit. It is.

The transmission / reception margin comparing unit 11 compares the margins of the processing functions in the apparatus on the transmission side and the reception side to determine which of the encoding processing and the decoding processing should be performed with higher priority.

The control unit 4 switches the changeover switches 3, 7, and 10 to the transmission side or the reception side based on the determination result of the transmission / reception margin comparison unit 11.

At the time of transmission, the input signal is sent to
The difference from the value stored in the encoding unit memory 8 is obtained, encoded by the encoding unit 2, and output as coefficient data. The coefficient data is decoded by the decoding unit 5, and the sum with the value held in the coding unit memory 8 is calculated by the adding unit 6, and this sum is calculated by the coding unit memory 8.
Is held.

At the time of reception, the received coefficient data is decoded by the decoding unit 5, and the sum with the value held in the decoding unit memory 9 is obtained by the adding unit 6 to become an output signal. This sum is stored in the decoding unit memory 9.

[Action]

As described above, in the configuration of FIG. 1, in the configuration for encoding and the configuration for decoding, the configurations of the decoding unit and the addition unit are shared, and the configuration for encoding and decoding Other configurations required for
By switching 7, and 10, it is connected to the common unit.

In the above switching, the transmission / reception margin comparing unit 11 compares the margins of the processing functions in the apparatus on the transmission side and the reception side, and determines which of the encoding processing and the decoding processing should be performed with priority. Is performed based on the result of the determination.

Therefore, when there is a margin in the decoding processing capability (margin) of the receiving side according to the margin of the encoding processing and the decoding processing ability in each of the transmitting side and the receiving side, the encoding processing of the transmitting side is performed. In addition, the processing capacity of the sending side (margin)
And when the load on the decoding process on the receiving side is large, only the decoding process can be performed to always maximize the encoding / decoding processing capability, and a part of the hardware configuration is shared. By doing so, the hardware scale can be reduced.

In the configuration shown in FIG. 1, the above-mentioned switching can be performed in accordance with a command from a hardware switch or the like without depending on the transmission / reception margin comparing unit 11.

〔Example〕

FIG. 2 is an overall configuration diagram of a transmission / reception device including the encoding / decoding device of the present invention.

In FIG. 2, reference numeral 20 denotes a transmission buffer, 21 denotes a reception buffer, 22 denotes a comparator, and 23 denotes a transmission line interface.

After the transmission data is temporarily stored in the transmission buffer 23,
The received data transmitted on the transmission line via the transmission line interface 26 including the configuration for encoding and transmission, and conversely, received from the transmission line and decoded, is temporarily stored in the reception buffer 24, and Read in order for processing.

In the present invention, the transmission / reception margin comparing unit 11
In order to realize the above, each of the transmission buffer 23 and the reception buffer 24 compares the data accumulation amount,
Based on the comparison result, it is determined whether to perform the transmission-side processing or the reception-side processing. That is, it is determined that the reception process is performed when the storage amount of the reception buffer is larger than the storage amount of the transmission buffer, and that the transmission process is performed when the storage amount of the transmission buffer is larger than the storage amount of the reception buffer. .

For example, the transmission buffer 23 and the reception buffer 24
If constituted by a FIFO memory, information on the respective data storage amounts can be easily retrieved.

FIG. 3 shows the configuration of other parts in the embodiment of the encoding / decoding device of the present invention.

In FIG. 3, 29 is a subtraction circuit, 30 is a cosine transform coding circuit, 31 is a quantization circuit, 32, 37 and 39 are D flip-flop circuits, 33 is a decoding circuit, 34 is an inverse quantization circuit,
35 is an adder circuit, 36 is a RAM, 38 is a buffer, 40 is an inverter, 41 is a ROM, 42 is a register, and 43 is a counter.

As can be seen from a comparison with the configuration of the conventional encoding circuit in FIG. 4, the subtraction circuit 29, the encoding circuit 30, the quantization circuit 31,
The D flip-flop circuit 32, the decoding circuit 33, the inverse quantization circuit 34, the adding circuit 35, the RAM 36, and the D flip-flop circuit 37 constitute an encoding circuit, and the D flip-flop circuit 39, the decoding circuit 33, Quantization circuit 34, addition circuit 35,
RAM 36, D flip-flop circuit 37, and buffer 38
Constitutes a decoding circuit.

The switching between these two configurations is done in ROM4
1, controlled by a ROM sequencer including a register 42, a counter 43, and an inverter 41. That is,
The ROM sequencer corresponds to the control unit 4 in the configuration shown in FIG.

The ROM sequencer 41 receives the switching signal output from the comparator 22 in FIG. 2, the output of the counter 43 described below, and (a part of) the output of the register 42, and
A bit for outputting a signal for selecting one of the flip-flop circuits 32 and 39, the load value of the counter, the counter 43
Output the load signal.

The selection of one of the D flip-flop circuits 32 or 39 is
This is performed according to the switching signal.

The RAM 36 includes an area for implementing the encoder memory 8 and an area for implementing the decoder memory 9 shown in FIG. 1. The address at the time of transmission and the address at the time of reception are determined by the count output Q of the counter 43. That is, it is provided in response to the switching signal by the output of the ROM 41.

As apparent from the above description, in the configuration of FIG. 3, the decoding circuit 33, the inverse quantization circuit 34, the addition circuit 35,
The RAM 36 and the D flip-flop circuit 37 have a common configuration at the time of transmission that operates as an encoding circuit and at the time of reception that operates as a decoding circuit, and the encoding circuit and the decoding circuit are configured independently. Conventional encoding /
The hardware scale is reduced compared to the decryption device.

In the above-described configuration, the switching timing of the switching signal can be switched in units of blocks in a method in which one screen of an image is divided into a plurality of blocks and encoded.

〔The invention's effect〕

According to the present invention, the decoding processing capacity (margin) of the receiving side is set according to the margin of the coding processing and the decoding processing capacity at each of the transmitting side and the receiving side of the coding / decoding device.
When there is a margin, the transmitting side encoding process is performed to increase the transmitting side processing capability (margin), and when the load on the decoding process on the receiving side is large, only the decoding process is performed. Thus, each processing capability of decoding / decoding can always be extracted as effectively as possible, and the hardware scale can be reduced by sharing a part of the hardware configuration.

[Brief description of the drawings]

FIG. 1 is a basic block diagram of the present invention, FIGS. 2 and 3 are block diagrams of an embodiment of the present invention, and FIGS. 4 and 5 are diagrams of a conventional encoding / decoding apparatus, respectively. FIG. 3 is a diagram illustrating a schematic configuration of an encoding unit and a decoding unit. [Explanation of Codes] 1 ... Differential calculation unit, 2 ... Encoding unit, 3, 7, 10 ... Switch, 4 ... Control unit, 5 ... Decoding unit, 6 ... Addition unit, 8 ... Encoding unit memory, 9 ... Decoding unit memory, 11 ... Transmission / reception margin comparison unit, 29 ... Subtraction circuit, 30 ... Cosine transform coding circuit, 31 ... Quantization circuit, 32,37,39 ... D flip-flop circuit, 33 ... Decoding Circuit, 34 ... Inverse quantization circuit, 35 ... Addition circuit, 36 ... RAM, 38 ... Buffer, 40 ... Inverter, 41 ... RO
M, 42 register, 43 counter, 47 decoding circuit, 48
... inverse quantization circuit, 49 addition circuit, 50 memory, 60 subtraction circuit, 61 encoding circuit, 62 quantization circuit, 63 decoding circuit, 64 inverse quantization circuit, 65 addition circuit, 66… Memory.

Claims (2)

(57) [Claims] An encoding / decoding device that encodes and transmits a data signal to be transmitted, and receives and decodes the encoded data signal, comprising: a differential operation unit (1); 2), first to third changeover switches (3, 7, 10), control unit (4), decoding unit (5), adding unit (6), and encoding unit memory (8)
And a decoding unit memory (9), wherein the control unit (4) operates the first and third changeover switches (3, 7, 10) when transmitting and receiving, respectively. The difference calculation unit (1) calculates the difference between the input signal and the value held in the encoding unit memory (8) at the time of transmission. The decoding unit (2) encodes the output of the difference calculation unit (1) and outputs the result as coefficient data. The decoding unit (5) decodes the coefficient data. The adding unit (6) A sum of an output of the decoding unit (6) and a value held in the encoding unit memory (8) is obtained. The encoding unit memory (8) outputs an output of the adding unit (6). Holding, upon reception, the decoding unit (5) decodes the received coefficient data; 6) obtains the sum of the output of the decoding unit (5) and the value held in the decoding unit memory (9) to obtain an output signal, and the decoding unit memory (9) An encoding / decoding device which holds the output of (6). 2. An encoding / decoding device for encoding and transmitting a data signal to be transmitted and receiving and decoding the encoded data signal, comprising: a difference operation unit (1); 2), first to third changeover switches (3, 7, 10), control unit (4), decoding unit (5), adding unit (6), and encoding unit memory (8)
And a decoding unit memory (9), and a transmission / reception margin comparison unit (11), wherein the transmission / reception margin comparison unit (11) The control unit (4) compares the margins of the processing functions to determine which of the encoding process and the decoding process should be performed with higher priority.
Based on the determination result of 1), the first and third changeover switches (3, 7, 10) are switched to a transmission side or a reception side, and at the time of transmission, the difference calculation unit (1) A difference between a signal and a value held in the coding unit memory (8) is obtained. The coding unit (2) codes the output of the difference calculation unit (1) and outputs the result as coefficient data. The decoding unit (5) decodes the coefficient data, and the adding unit (6) outputs the output of the decoding unit (6) and the value held in the encoding unit memory (8). The encoding unit memory (8) holds the output of the addition unit (6). At the time of reception, the decoding unit (5) decodes the received coefficient data, The adding unit (6) stores the output of the decoding unit (5) and the output of the decoding unit memory (9). Value as an output signal calculates the sum of the decoder memory (9), the encoding / decoding apparatus characterized by holding the output of said adding unit (6).