JP2765466B2 - Substrate bonding method - Google Patents

Substrate bonding method

Info

Publication number
JP2765466B2
JP2765466B2 JP5322522A JP32252293A JP2765466B2 JP 2765466 B2 JP2765466 B2 JP 2765466B2 JP 5322522 A JP5322522 A JP 5322522A JP 32252293 A JP32252293 A JP 32252293A JP 2765466 B2 JP2765466 B2 JP 2765466B2
Authority
JP
Japan
Prior art keywords
substrate
separation layer
bonding
bonding method
substrate bonding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP5322522A
Other languages
Japanese (ja)
Other versions
JPH07176456A (en
Inventor
幹浩 梶田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP5322522A priority Critical patent/JP2765466B2/en
Priority to US08/357,935 priority patent/US5459081A/en
Publication of JPH07176456A publication Critical patent/JPH07176456A/en
Application granted granted Critical
Publication of JP2765466B2 publication Critical patent/JP2765466B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は異種材料どうしを直接接
合する際の接合方法およびこれを利用した素子作製の際
の接合方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a joining method for directly joining dissimilar materials and a joining method for fabricating a device using the same.

【0002】[0002]

【従来の技術】近年、光電子集積回路への関心がますま
す高まってきている。GaAsやInPを材料とした光
デバイスと、SiやGaAsを材料とした電子デバイス
とを集積化することにより、動作特性の飛躍的な向上や
新機能の実現が期待される。このような光電子集積回路
を実現するために、Si、GaAs、InPなどの格子
定数が異なる材料を直接結晶成長させる技術の研究が盛
んに行われている。例えば、秋山らの著によるジャーナ
ル・オブ・クリスタル・グロウス(Journal o
f Crystal Growth)第68巻21〜2
6頁の論文において詳しく記述されている。この格子不
整合系の結晶成長技術は近年めざましい進歩がある。し
かし、この種の結晶成長膜には格子不整合や熱膨張係数
の違いに起因する転位が導入されるといった問題があ
り、これらの緩和のためにバッファー層を厚く挿入する
必要があった。
2. Description of the Related Art In recent years, there has been an increasing interest in optoelectronic integrated circuits. By integrating an optical device made of GaAs or InP and an electronic device made of Si or GaAs, a dramatic improvement in operating characteristics and realization of new functions are expected. In order to realize such an opto-electronic integrated circuit, a technique for directly crystal-growing materials having different lattice constants such as Si, GaAs, and InP has been actively studied. For example, Journal of Crystal Grouse by Akiyama et al.
f Crystal Growth) Vol. 68, 21-2
This is described in detail in a six-page paper. In recent years, there has been remarkable progress in the crystal growth technology of the lattice mismatch system. However, this type of crystal growth film has a problem that dislocations due to lattice mismatch and differences in thermal expansion coefficients are introduced, and it is necessary to insert a thick buffer layer to alleviate these problems.

【0003】こうした異種材料同志の結晶成長とは別に
基板同志の直接接合という方法が広く行われ、実用化へ
の試みが進んでいる。これらの記述は例えば、古川らに
よる1991年の応用物理第60巻8号790〜793
頁に載っている。基板接合技術は比較的工数も少なく、
界面に対する条件が比較的緩やかである。したがって、
将来的には個々の基板上で最適化したデバイスどうしの
接合あるいは電子回路を集積してある基板上へ各々の基
板で最適化したデバイスを直接接合により転写すること
も可能になると考えられ、広い応用面からの期待が集め
られている。
[0003] Apart from such crystal growth of different materials, direct bonding of substrates has been widely performed, and attempts for practical use have been made. These descriptions are described, for example, in Furukawa et al., Applied Physics Vol. 60, No. 8, 790-793, 1991.
On the page. Substrate bonding technology requires relatively few steps,
The conditions for the interface are relatively mild. Therefore,
It is thought that in the future, it will be possible to bond devices optimized on individual substrates or transfer devices optimized on each substrate directly to a substrate on which electronic circuits are integrated by bonding. Expectations from applications are gathered.

【0004】[0004]

【発明が解決しようとする課題】しかしながら、こうし
たある基板上へのデバイスの転写の際にデバイスを転写
する側の基板のどこへ接合するのかといった目合わせの
問題があった。目合わせの方法としては、赤外光を用い
て目合わせパターンの照合を行うといったものもあった
が、種々の機器が必要となり接合ということに関しては
煩雑となってしまっていた。また、デバイス転写後、基
板のみを分離する際に分離に相当な時間を要するといっ
た問題があった。
However, when the device is transferred onto a certain substrate, there is a problem of coordination as to where to join the substrate to which the device is to be transferred. As a method of alignment, there was a method of matching an alignment pattern using infrared light. However, various devices were required, and the joining was complicated. In addition, there is a problem that it takes a considerable time to separate only the substrate after device transfer.

【0005】そこで、本発明においては上記事情に鑑み
て、接合時の簡易な目合わせと分離時の所要時間短縮と
を同時に満たす接合方法を提供することを目的とする。
In view of the above circumstances, it is an object of the present invention to provide a joining method that satisfies both simple alignment at the time of joining and reduction of required time at the time of separation.

【0006】[0006]

【課題を解決するための手段】前述の課題を解決するた
めに、本発明が提供する手段は、目合わせパターンを有
する基板と、基板上に空孔部と分離層を介して形成され
た素子とを有する基板を、前記空孔部側から前記目合わ
せパターンを目合わせして前記基板どうしを接合し、前
記分離層を選択的にエッチングして前記分離層が形成さ
れた基板を分離し、前記目合わせパターンを有する基板
に、前記素子を接合することを特徴とした基板接合方法
である。
Means for Solving the Problems In order to solve the above-mentioned problems, a means provided by the present invention has a registration pattern.
To be formed on the substrate via a hole and a separation layer
The substrate having the element having the
The substrates are joined together by matching the pattern
The separation layer is selectively etched to form the separation layer.
A substrate having the alignment pattern
To a substrate bonding method, characterized in that bonding the element.

【0007】[0007]

【作用】本発明によれば、基板に穴部を設けるといった
簡易な切削技術を追加するだけで、簡易な目合わせを行
うことができ、また、分離時には該穴部(空孔)よりエ
ッチング液が浸透し易くなり、分離時間が短縮される。
これにより、一連の基板接合を用いた素子作製が簡潔、
かつ短時間で行えるようになる。
According to the present invention, simple alignment can be performed only by adding a simple cutting technique such as providing a hole in a substrate, and the etching solution is removed from the hole (hole) at the time of separation. Are easily permeated, and the separation time is shortened.
As a result, device fabrication using a series of substrate bonding is simple,
And it can be done in a short time.

【0008】[0008]

【実施例】次に本発明の実施例について、図面を参照し
ながら詳細に説明する。図1に本発明で用いる基板の形
状を表す概略図を示す。そして、図2は本発明を用いた
基板接合方法の一例を示す断面図である。まず第一のS
i基板1を用意し、これに目合わせパターン2を形成し
ておく。これとは別に例えば第二のInP基板3を用意
する。このInP基板3に接合の目合わせにしたがって
空孔部4を形成する。次に、InP基板3上にレーザな
どの長波系デバイス(素子)5を分離層6を厚さ0.5
μm程度形成した後に作製する。分離層6としてはこの
場合、例えばInX Al1 X As(xは0〜0.5)
を用いる。
Next, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a schematic diagram showing the shape of a substrate used in the present invention. FIG. 2 is a cross-sectional view showing an example of a substrate bonding method using the present invention. First S
An i-substrate 1 is prepared, and a registration pattern 2 is formed thereon. Separately, for example, a second InP substrate 3 is prepared. The holes 4 are formed in the InP substrate 3 according to the joint alignment. Next, on the InP substrate 3, a long-wave device (element) 5 such as a laser is separated from the separation layer 6 to a thickness of 0.5.
It is produced after forming about μm. In this case, as the separation layer 6, for example, In X Al 1 - X As ( x is 0 to 0.5)
Is used.

【0009】InP基板3とSi基板1とを空孔部4か
らSi基板1の目合わせパターン2を見込みながら目合
わせを行い、双方の基板同志を重ね合わせ、そのまま6
00℃60分間H2 雰囲気中でアニール処理を行う。こ
れにより両者の接合を行なうことができる。更に、もし
異なる第三のInP基板上に別に作製した素子も第一の
Si基板1上に転写したい場合は、同様の工程を繰り返
して行けばよい。
The InP substrate 3 and the Si substrate 1 are aligned from the hole 4 while observing the alignment pattern 2 of the Si substrate 1.
Annealing is performed in an H 2 atmosphere at 00 ° C. for 60 minutes. Thereby, both can be joined. Further, if it is desired to transfer an element separately manufactured on a different third InP substrate onto the first Si substrate 1, the same steps may be repeated.

【0010】次に、燐酸をエッチャントとして分離層6
のみを選択的に除去する。この際、空孔部4からもエッ
チャントが回り込んで分離層6をエッチングするため分
離に要する時間は短縮されることになる。こうして、第
一のSi基板1上に種々の光デバイスを形成できること
になる。ここで、個々の基板は目的に応じて材料を変え
ればよく、ここで示したものに限らない。そして、それ
に応じて分離層やそのエッチャントを適宜選択して行け
ばよい。また、第一の基板上に既に何らかの素子が作製
されていても構わない。素子はレーザに限らず、受光器
などの光デバイス一般に適用可能である。
Next, the separation layer 6 is formed using phosphoric acid as an etchant.
Only selective removal. At this time, since the etchant wraps around the holes 4 to etch the separation layer 6, the time required for separation is reduced. Thus, various optical devices can be formed on the first Si substrate 1. Here, the materials of the individual substrates may be changed according to the purpose, and are not limited to those shown here. Then, a separation layer and an etchant thereof may be appropriately selected in accordance therewith. In addition, some elements may be already formed on the first substrate. The element is not limited to a laser, but can be applied to optical devices such as a light receiver in general.

【0011】[0011]

【発明の効果】本発明によれば、デバイス(素子)と基
板の直接接合を行う際に、簡易に目合わせを行え、また
基板分離時に分離時間の短縮が可能になる。
According to the present invention, alignment can be easily performed when a device (element) is directly joined to a substrate, and the separation time can be reduced when the substrate is separated.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明を用いた基板の形状を表す概略図であ
る。
FIG. 1 is a schematic diagram showing the shape of a substrate using the present invention.

【図2】本発明を用いた基板接合方法を示す断面図であ
る。
FIG. 2 is a cross-sectional view showing a substrate bonding method using the present invention.

【符号の説明】[Explanation of symbols]

1 基板 2 目合わせパターン 3 基板 4 空孔部 5 デバイス 6 分離層 DESCRIPTION OF SYMBOLS 1 Substrate 2 Matching pattern 3 Substrate 4 Void part 5 Device 6 Separation layer

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 目合わせパターンを有する基板と、基板
上に空孔部と分離層を介して形成された素子とを有する
基板を、前記空孔部側から前記目合わせパターンを目合
わせして前記基板どうしを接合し、前記分離層を選択的
にエッチングして前記分離層が形成された基板を分離
し、前記目合わせパターンを有する基板に、前記素子を
接合することを特徴とする基板接合方法。
A substrate having a 1. A pitch alignment pattern, a substrate having an element which is formed via the the pores part separating layer on a substrate, and combined eye the eye alignment pattern from the pore portion Bonding the substrates to each other, selectively etching the separation layer to separate the substrate on which the separation layer is formed, and bonding the element to a substrate having the alignment pattern. Method.
JP5322522A 1993-12-21 1993-12-21 Substrate bonding method Expired - Fee Related JP2765466B2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP5322522A JP2765466B2 (en) 1993-12-21 1993-12-21 Substrate bonding method
US08/357,935 US5459081A (en) 1993-12-21 1994-12-16 Process for transferring a device to a substrate by viewing a registration pattern

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5322522A JP2765466B2 (en) 1993-12-21 1993-12-21 Substrate bonding method

Publications (2)

Publication Number Publication Date
JPH07176456A JPH07176456A (en) 1995-07-14
JP2765466B2 true JP2765466B2 (en) 1998-06-18

Family

ID=18144606

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5322522A Expired - Fee Related JP2765466B2 (en) 1993-12-21 1993-12-21 Substrate bonding method

Country Status (1)

Country Link
JP (1) JP2765466B2 (en)

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6221277A (en) * 1985-07-19 1987-01-29 Nec Corp Electrostatic bonding method
JPH0729783A (en) * 1993-07-13 1995-01-31 Aging Tesuta Kaihatsu Kyodo Kumiai Method for joining two semiconductor wafers

Also Published As

Publication number Publication date
JPH07176456A (en) 1995-07-14

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Effective date: 19980303

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