JP2764945B2 - Digital demodulator - Google Patents

Description

Description: FIELD OF THE INVENTION The present invention relates to a digital demodulator used on the receiving side of a digital communication system, and more particularly to a digital demodulator comprising a transversal equalizer and a demodulator. About.

(Prior Art) As is well known, in a digital communication system, 16QAM (Quadrature Amplitude Modulati
on), the development and commercialization of multi-level QAM modulation schemes such as 64QAM are in progress.

However, such a multi-level QAM modulation scheme has poor resistance to various types of distortion in the transmission system, and its effect becomes more serious as the number of levels increases. Therefore, in a digital demodulator in a conventional digital communication system, for example, as shown in FIG. 3, a transversal type equalizer 1 (illustrated in the IF band) is arranged in front of a demodulator 2. Has become. This transversal type equalizer is an effective means for various distortions in the transmission system, and is indispensable in a high-value digital modulation system (QAM modulation system).

In FIG. 3, an input signal 105 is, for example, a 16QAM modulated signal, and the input signal 105 enters the transversal filter 4 of the transversal equalizer 1 in the IF band, where it undergoes optimal waveform equalization processing. It is output to the demodulator 2 (details will be described later).

The output (digital modulated signal after equalization) 107 of the transversal equalizer 1 enters the quadrature detector 6 of the demodulator 2 and
Here, quadrature detection is performed based on the reproduced carrier signal 109,
Two-sequence demodulated baseband signals with different π / 2 phases
108 and 108. And this demodulated baseband signal
108 and 108 are converted into digital signals by the corresponding 3-bit A / D converters 7 and 8, and the main data signals (D _1p , D _2p , D _1q ,
D _2q ), the error signals (E _p , E _q ) and the clock signal CLK are reproduced and output. These are the demodulated outputs 101 of the demodulator 2, all of which are supplied as control signals to the weighted control signal generator 3 of the transversal equalizer 1, and
A part thereof is supplied to a carrier recovery circuit 9 in the demodulator 2.

The carrier recovery circuit 9 reproduces and outputs the recovered carrier signal 109 required for synchronous detection, and generates a carrier synchronization state display signal (hereinafter, referred to as an “ALARM signal”) 106. The ALARM signal 106 is a binary signal indicating whether the carrier recovery circuit 9 is in a synchronous state or an asynchronous state. For example, the level is "1" in the asynchronous state, and is "0" in the synchronous state. This ALARM signal 106 is also supplied to the weighted control signal generator 3 as a control signal. The configuration and operation of the carrier recovery circuit 9 are described in, for example,
Since it is described in detail in JP-A-131151, the restatement is omitted.

The transversal equalizer 1 is composed of the weighted control signal generator 3, the transversal filter 4, and an integrating circuit 5 'interposed therebetween and provided for each tap. The basic operation of this transversal type equalizer is described, for example, in 1984, IEICE Communication Division National Convention No.628, "4 / 5GHz 16QAM 200Mb / s Demodulator with Transversal Equalizer". Therefore, detailed description is omitted, but the outline is as follows.

The weighted control signal generator 3 outputs the demodulated output 101 and the ALARM signal
A 5-tap digital control signal 102 is formed based on 106, and is supplied to a corresponding integration circuit 5 '. Specifically, when the signal state of the ALARM signal 106 is “0” level,
A digital control signal is formed based on the main data signal and the error signal. The signal state of the ALARM signal 106 is “1”
At the time of the level, the main data signal and the error signal are separated from the internal circuit, and a signal (for example, a clock signal CLK) in which the “1” level and the “0” level occur with equal probability is output as the digital control signal 102. .

The digital control signal 102 is averaged by the integration circuit 5 'to become an analog control signal 103, which is applied to a corresponding tap of the transversal filter 4 as a tap control voltage.

The transversal filter 4 includes a delay circuit and a weighting circuit, and the weighting circuit is controlled by a corresponding one of the analog control signals 103. as a result,
The intersymbol interference included in the input signal 105 is compensated, and the output 107 subjected to the optimal waveform equalization processing is formed.

Here, the integration circuit 5 'is configured around an OP amplifier 41 as shown in FIG. 4, for example. This OP amp 41
, Together with the capacitor C ₀ and resistor R _s are connected in parallel between its inverting input terminal and an output terminal, said digital control signal 102 to the inverting input terminal via the resistor R ₀ is, also to the non-inverting input terminal _Are adapted to apply a reference voltage V _ref 104 respectively.

That is, the integrating circuit 5 'includes the resistor _R0 and the capacitor _R0 in the output variable range DC-offset by the reference voltage _Vref.
An analog control signal 103 is formed by integrating the digital control signal 102 with a time constant determined by the product of C ₀ .

(Problems to be Solved by the Invention) As described above, the transversal type equalizer in the digital demodulator includes the integration circuit, and the integration time constant of the integration circuit depends on the bit error rate characteristics and the synchronization pull-in time of the carrier recovery circuit. Is one of the deciding factors, and the relationship can be explained as follows.

First, it can be said that a larger integration time constant is better in relation to the bit error rate. That is, if the integration time constant is sufficiently large, the jitter component included in the analog control signal, which is the output signal of the integration circuit, is suppressed, so that the digital modulation signal itself subjected to waveform equalization processing in the transversal filter based on the analog control signal. Is also suppressed, and the bit error rate caused by jitter is improved.

Next, it can be said that a smaller integration time constant is better in relation to the synchronization pull-in time. That is, the carrier recovery circuit
When the ALARM signal is at “1” level, the digital modulation signal and the reproduced carrier signal are asynchronous, but
At this time, the digital control signal output from the weighted control signal generator becomes the clock signal CLK, so that the output of the integration circuit has a constant intermediate voltage value in the output variable range.
When a transition is made from the asynchronous state to the synchronous state, the output of the integration circuit is an optimum tap from which the transversal filter can perform control to minimize the intersymbol interference of the digital modulation signal from the constant intermediate voltage value. Although the voltage changes to a voltage, the time required for this change, that is, the time required for synchronization pull-in, is shorter as the integration time constant is smaller.

Then, in the integrating circuit in the conventional transversal type equalizer, as described above, the integration time constant is set to be constant and invariable, so that the conventional digital demodulator improves the bit error rate characteristics and shortens the synchronization pull-in time. There is a problem that the two conditions cannot be optimized together.

The present invention has been made in view of such a conventional problem, and an object thereof is to enable an integration time constant of an integration circuit to be changed and set, thereby improving a bit error rate characteristic and shortening a synchronization pull-in time. To provide a digital demodulation device.

(Means for Solving the Problems) In order to achieve the above object, a digital demodulation device of the present invention has the following configuration.

That is, the digital demodulation device of the present invention comprises a demodulator and a transversal equalizer preceding the demodulator, and the transversal type equalizer performs a multi-level digital modulation signal as an input signal. In response to the demodulated output of the demodulator and outputting it as an input multi-level digital modulation signal to the demodulator; the transversal equalizer comprises: An integrating circuit for generating a control signal for each tap of the transversal filter has a different integration time constant depending on a signal state as a synchronous or asynchronous state designated by a carrier synchronous state display signal generated by the demodulator. Switching to a large value or a small value.

(Operation) Next, the operation of the digital demodulation device of the present invention configured as described above will be described.

The integration circuit provided in the transversal equalizer of the present invention switches its integration time constant to a different value according to the signal state of the carrier synchronization state indication signal. That is,
The integration time constant can be switched to a small value when the carrier synchronization state indication signal indicates an asynchronous state, and to a large value when the synchronization state indicates a synchronous state.

As a result, it is possible to optimize both the improvement of the bit error rate characteristic and the reduction of the synchronization pull-in time.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows a digital demodulator according to one embodiment of the present invention. Note that the same components as those of the conventional example are denoted by the same reference numerals, and description thereof is omitted.

In the digital demodulator according to the present invention, the integration circuit 5 of the transversal equalizer 1 sets the integration time constant to the ALARM signal 1
Switching is performed according to the signal state of 06. The integration circuit 5 is configured as shown in FIG. 2, for example.

In Figure 2, the integrating circuit 5, unlike the conventional integration circuit 5 'is connected a series circuit of a capacitor C ₁ and the switch SW in parallel with the capacitor C _0, to control the switch SW with the ALARM signal 106 It was made.

That is, the switch SW is opened (OFF) when the ALARM signal 106 is at the “1” level, that is, asynchronously, and the integration time constant (τ ₁ ) is C ₀ R ₀ . On the other hand, this switch SW is ALARM
When the signal 106 is at the “0” level, that is, at the time of synchronization, it is closed (O
N) and set the integration time constant (τ ₂ ) to R ₀ (C ₀ + C ₁ ). Therefore, by appropriately selecting and setting the values of the capacitors C ₀ and C ₁ , τ ₁ at the time of asynchronous operation is sufficiently reduced, τ ₂ at the time of synchronous operation is sufficiently increased, and the synchronization pull-in time and the bit error rate are increased. Can be optimized at the same time.

(Effects of the Invention) As described above, according to the digital demodulation device of the present invention, the integration time constant is switched to the signal state of the carrier synchronization state display signal, that is, different values between the asynchronous state and the synchronous state. In addition, an integration time constant for optimizing the synchronization pull-in time and the bit error rate characteristic can be set, and therefore, there is an effect that both the reduction of the synchronization pull-in time and the improvement of the bit error rate characteristic can be optimized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a digital demodulator according to an embodiment of the present invention, FIG. 2 is a circuit diagram of an integrating circuit of the present invention,
FIG. 3 is a block diagram showing the configuration of a conventional digital demodulator,
FIG. 4 is a circuit diagram of a conventional integration circuit. 1 ... IF band transversal equalizer, 2 ... demodulator, 3 ... weighted control signal generator, 4 ... transversal filter, 5, 5 '... integration circuit, 6 ... quadrature detection , 7,8 ... A / D converter, 9 ... Carrier recovery circuit, 41 ...
OP amplifier, R ₀ , R _s …… Resistance, C ₀ , C ₁ …… Capacitor, SW…
… Switch, V _ref …… Reference voltage.

Claims (1)

(57) [Claims] The present invention comprises a demodulator and a transversal type equalizer preceding the demodulator, wherein the transversal type equalizer optimally equalizes a multi-level digital modulation signal as an input signal. A digital demodulator for performing processing in response to a demodulated output of the demodulator and outputting the result as an input multi-level digital modulation signal to the demodulator; the transversal type equalizer includes a transversal filter; An integrating circuit that generates a control signal for each tap sets its integration time constant to a predetermined large value or a small value that differs according to the signal state as a synchronous or asynchronous state specified by the carrier synchronous state display signal generated by the demodulator. A digital demodulator characterized by being switched to: