JP2762519B2 - Information card - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention will be described in the following order.

A Field of application in industry B Outline of the invention C Conventional technology D Problems to be solved by the invention E Means for solving the problems (FIG. 1) F operation (FIG. 1) G embodiment (1st embodiment) (Figures 1 to 6) (G1) First Embodiment (Figs. 1 to 4) (G2) Other Embodiments (Figs. 5 and 6) Effects of Invention H The present invention relates to an information card, and more particularly, to improving the variation of the information reading clock frequency.

B. Summary of the Invention The present invention can effectively avoid the possibility that the transmission speed of read data varies due to the CR oscillation frequency being adjusted in the information card.

C Prior Art As a conventional information card, a response request signal using, for example, a microwave of 2.45 [GHz] as a carrier wave is radiated to an antenna composed of, for example, a 1/2 wavelength dipole antenna, and the reflectance of the antenna is read out. A method has been proposed in which a reflected wave is returned as a response information signal by performing change control in accordance with information data read from an information memory that performs a read operation in response to a clock signal (Japanese Patent Application No. 63-6292). issue).

D. Problems to be Solved by the Invention However, in this type of information card, the information reading clock signal generating means for generating the information reading clock signal is made small and thin by an integrated circuit (IC) manufacturing technique. It is considered preferable to apply a CR oscillator that can be used.

However, the CR oscillator actually formed inside the IC is practically an IC
There is a problem that it is unavoidable that the variation is considerably large (for example, about three times as large as the reference frequency) based on the variation of the pattern or the like at the time of manufacturing.

As a method of solving this problem, firstly, an information card dedicated to an information card reading system which measures the oscillation frequency of a CR oscillator of each information card at the time of shipment from a factory and divides the frequency into a plurality of frequency ranges and fits each rank. A method of specifying a use has been considered.

For example, an information card belonging to a rank that does not have high frequency accuracy is assigned so as to be used only for applications that do not require frequency accuracy.

In the case where the frequency of the information reading clock signal varies over a wide range, it is necessary to read the information transmitted while following the information card for all information cards whose data transmission speed varies over the wide range. In addition, it is necessary to apply a more complicated configuration as the receiving device of the information reading system, and it is inevitable that the configuration of the entire information card reading system becomes complicated.

The present invention has been made in view of the above points, for example, at the time of factory shipment, by allowing the frequency of the CR oscillator mounted on each information card can be easily adjusted to a predetermined reference allowable range, information An object of the present invention is to propose an information card that can further reduce the variation in transmission speed.

Means for Solving Problem E In order to solve this problem, the present invention provides an antenna 11 for receiving a reception signal W1, a clock signal generation circuit 14 comprising a CR oscillator, and an impedance variable for varying the impedance of the antenna 11. And an impedance variable circuit 12 for controlling the impedance of the antenna 11 in accordance with the information data S1 generated by the clock signal S2 obtained from the clock signal generation circuit 14. and the information card 4, based on the frequency adjustment signal S _CL supplied from an external information card 4, and to provide a clock oscillation frequency adjusting circuit 21 for adjusting the CR oscillation frequency of the clock signal generating circuit 14.

Function F Frequency adjustment signal S supplied from outside the information card 4
_The clock oscillation frequency adjustment circuit 21 for adjusting the CR oscillation frequency of the clock signal generation circuit 14 based on the _CL is provided, for example, when the information card 4 is shipped from a factory to the clock. Signal generation circuit
Variations in the 14 CR oscillation frequencies can be effectively suppressed.

G Example Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

(G1) First Embodiment In FIG. 1, reference numeral 1 denotes an information card reader as a whole, and a response request having a carrier wave composed of a microwave of 2.45 [GHz] from an information writing / reading device 2 via a transmitting antenna 3. The signal W1 is applied to the information card 4 composed of, for example, an IC card, and the response information signal W2 composed of the reflected wave can be taken into the information writing / reading device 2 via the receiving antenna 5.

The information card 4 has an antenna 11 composed of, for example, a 1/2 wavelength dipole antenna, and an impedance variable circuit 12 composed of, for example, a field effect transistor (FET) is connected between its feeding points P1 and P2.

At the control input terminal of the variable impedance circuit 12, information data stored in the information memory 13 is read by a read clock signal S2 supplied from a clock signal generation circuit 14, and supplied as an output information data signal S1. When the output information data signal S1 is at the logical "H" or "L" level, the impedance variable circuit 12 changes the reflection characteristic of the antenna 11 to change the reflected wave to the response information signal W2.
Will be returned.

In this case, the information writing / reading device 2 reads the information data of the output information data signal S1 based on the change in the phase of the carrier of the response information signal W2.

Thus, the information data stored in the information memory 13 is read out at a speed corresponding to the frequency of the read clock signal S2 given from the clock signal generation circuit 14, so that the information writing / reading device 2 operates at the frequency of the read clock signal S2. The data can be read continuously at a data transmission rate determined by the above.

In the case of this embodiment, information data to be written in the information writing / reading device 2 is superimposed on the response request signal W1 in the information memory 13 of the information card 4 at the time of shipment from the factory, so that the information data is In addition, the clock signal generation circuit 14 can superimpose the clock oscillation frequency adjustment data for adjusting the frequency of the clock signal generation circuit 14 on the response request signal W1. Can be supplied.

That is, while one feed point P1 of the antenna 11 is grounded, the received signal S3 obtained at the other feed point P2 is applied to the received signal detection circuit 16 having a half-wave rectification circuit configuration including a diode 16A and a capacitor 16B. The reception signal S4 corresponding to the change in the envelope of the reception signal S3 is thus obtained at the output terminal of the reception signal detection circuit 16.

Here information reading apparatus 2 when writing information to the information card 4, as shown in FIG. 2, the write clock signal S _CK carrier as a response request signal W1 (FIG. 2 (B)), writing transmits the bit information data S _DT and Niyotsu formed by pulse width modulation Te signal, the received signal detection circuit 16 sends the received detection signal S4 whose signal level varies in accordance with the envelope (Figure 2 (C)) I do.

In the case of this embodiment, the response request signal W1 (accordingly, the reception signal S
The write information superimposed on 3) is, as shown in FIG. 2A, a write bit clock signal during the first half of the bit cycle T _BIT corresponding to the write clock cycle of the information memory 13. and forming a transmission period T _CK, the second half of the form the write bit data transmission period T _DT 1/2 cycle period, clock signal by continuously emits a carrier wave during a write Bitsutokurotsuku signal transmission period T _{CK SCK} is transmitted to the information card 4,
For example, the falling edge indicates the write clock time.

Response request signal W1 In addition, the write in bit data transmission period T _DT, write clock signal S _CK write bit data period of time T ₂ from the time elapsed from clock time by a predetermined time T ₁ of the as the period, the transmitting bit data of "1" in the write data dATA _WT (FIG. 2 (a)) by emitting a carrier continuously between the write bit data period T _2, the write bit "0" by go-between write data dATA _WT to stop the radiation of between carriers of the data period T ₂
It is designed to transmit bit data.

Thus the response request signal W1 is write Bitsutokurotsuku signal transmission period T with repeatedly transmitting a pulse width modulated write clock signal S _CK in _CK, followed Similarly pulse width between the write bit data transmission period T _DT The modulated bit data signal _SDT is transmitted.

The received signal S2 has the same envelope as the envelope of the response request signal W1 (FIG. 2 (B)), which is converted into a received detection signal S4 (FIG. 2 (C)) by the received signal detection circuit 16, and thus received. with detection signal S4 to generate the write clock detection signal component S _CKX at the timing of the write Bitsutokurotsuku signal transmission period T _CK, the write bit data transmission period
Generating a write data detection signal component S _DTX at timing T _DT.

The reception detection signal S4 is supplied to the write data detection circuit 18, and the write data detection circuit 18 supplies the detection data S5 corresponding to the reception detection signal S4 to the data writing circuit 19, so that the write clock and the information Write data signal consisting of data
By supplying S6 to the information memory 13, the information data is taken into the information memory 13.

In addition to the above configuration, when the clock frequency adjustment mode information writing / reading device 2 needs to adjust the clock frequency of the clock signal generation circuit 14, a predetermined rising period as shown in FIG. a carrier between the information retrieval signal W1 of T ₁₀ to further increase the amplitude, to receive this information card 4 as a clock signal frequency adjustment signal S _CL.

The clock signal frequency adjustment signal S _CL is supplied to the reception signal detecting circuit 16 as a reception signal S3, supplied received detection signal S4 having the envelope waveform S _CLX a (FIG. 3 (B)) to the clock oscillator frequency adjusting circuit 21 I do.

As shown in FIG. 4, the clock oscillation frequency adjusting circuit 21 receives the reception detection signal S4 (FIG. 3 (B)) by the buffer amplifier circuit 21A and changes the signal level of the envelope waveform S _{CLX to} the threshold level L _SHC. Adjustment pulse P when exceeds
_CTL (FIG. 3 (C)) is sent to the adjustment data generation circuit 21B.

Here, the threshold level L of the buffer amplifier circuit 21A
_SHC is the threshold level L _SHD of the write data detection circuit 18.
While selected at a much higher level,
The signal level of the clock signal frequency adjustment signal S _CL (FIG. 3A) sent from the information writing / reading device 2 is determined by the write clock signal _SCK and the write data signal S sent in the information write mode. _DT (FIG. 2 (B)) has a signal level significantly higher than that of the signal level, so that the clock oscillation frequency adjusting circuit 21 generates the reception detection signal S4 in the information writing mode. Even if the clock detection signal component S _CKX and the write data detection signal component S _DTX are generated, the signal level is the threshold level L _SHC
Whereas not respond to this by not exceeding, it has been made to to generate an adjustment pulse P _CTL in response thereto when the clock signal frequency adjustment signal S _CL arrives.

Adjustment data generating circuit 21B is constituted for example by four bits counter, it adjusts the pulse P _CTL consisting of four bits of the count data B1~B4 by the by connexion counting operation, for example, the falling each time given the adjustment data S _CTL Is supplied to the resistance value setting circuit 14A of the clock signal generation circuit 14.

The resistance value setting circuit 14A includes four field-effect transistors TR1 to TR4 connected in parallel with each other as adjustable resistance elements.
And has a resistance value corresponding to the bit data B1 to B4 supplied to the gate.

This resistance value setting circuit 14A is connected to the CR oscillation circuit main body 14 as an oscillation constant circuit, whereby the CR oscillation circuit main body 14B
Is a read clock signal by oscillating at a frequency determined by the capacitance value of the capacitor provided inside and the combined resistance value viewed from the output terminal of the resistance value setting circuit 14A.
Generates S2.

In the above configuration, when the information card 4 is shipped from the factory, the oscillation frequency of the clock signal generation circuit 14 is adjusted by setting the information writing / reading device 2 to the clock frequency adjustment mode.

Here, the resistance value setting circuit 14A of the clock signal generation circuit 14
The resistance value of the clock oscillates at the oscillation frequency corresponding to the count in the adjustment data generation circuit 21B of the clock oscillation frequency adjustment circuit 21, and the information data in the information memory 13 is read by the read clock signal S2 obtained thereby. By reading continuously, the information data is transmitted to the information writing / reading device 2 as a response information signal W2.

At this time, the information writing / reading device 2 receives the response information signal.
The transmission speed of information data, that is, the oscillation frequency of the clock signal generation circuit 14 is detected from W2, and it is determined whether or not the oscillation frequency falls within a predetermined allowable range with respect to the reference frequency.

Here, upon detecting that the oscillation frequency of the clock signal generation circuit 14 does not fall within the allowable range, the information writing / reading apparatus 2 sets the clock signal frequency adjustment signal S _CL (FIG. 3 (A)).
Is transmitted, thereby causing the counter of the adjustment data generation circuit 21B of the clock oscillation frequency adjustment circuit 21 to perform a count operation, thereby changing the adjustment data _SCTL by one count operation.

At this time, when the resistance value of the resistance value setting circuit 14A changes, the oscillation frequency of the CR oscillation circuit body 14B is adjusted accordingly, whereby the information data reading speed of the information memory 13 (therefore, the information data transmission speed) is adjusted. ) Is adjusted.

Thus, the data transmission speed of the response information signal W2 transmitted from the information card 4 to the information writing / reading device 2 is adjusted, but the information writing / reading device 2 again controls the data transmission speed of the returned information data. Clock signal generation circuit
Determining an oscillation frequency of 14, which sends again clock signal frequency adjustment signal S _CL when not entering a port in the allowable range information card 4.

In the same manner, the information writing / reading device 2 returns the response information signal W2
Continue sending the clock signal frequency adjustment signal S _CL to enter a predetermined allowable range with respect to the oscillation frequency of the transmission rate of transmission has been coming information data reference as the adjustment data generator 21B is counting accordingly Subsequently, as a result, the resistance value of the resistance value setting circuit 14A and, accordingly, the oscillation frequency of the CR oscillation circuit body 14B are adjusted.

Note adjustment data generator 21B when the count content has decreased to the maximum value by which consists of 4 binary counter, cyclically continues counting by operating Yotsute overflow subsequent adjustment pulse P _CTL.

When the oscillation frequency of the clock signal generation circuit 14 enters a predetermined allowable range, it means that the clock frequency adjustment processing for the information card 4 has been completed. At this time, the information writing / reading device 2 will thereafter output the clock signal frequency adjustment signal. S _CL
Is not transmitted, whereby the adjustment data generation circuit 21B maintains the adjustment end state, and as a result, the oscillation frequency of the clock signal generation circuit 14 maintains the state at the end of adjustment.

According to the above configuration, the oscillation frequency of the clock signal generating circuit 14 having the CR oscillator configuration can be adjusted until it falls within a predetermined allowable range. For example, when the information card 4 is manufactured, the CR constant of the CR oscillator is set as an IC. Even if the oscillation frequency of the clock signal generation circuit 14 varies due to the variation in the formation, it can be surely adjusted to an allowable range.

Therefore, if the oscillation frequency of the clock signal generating circuit 14 is adjusted at the time of shipment from the factory, the data transmission speed of the response information signal W2 transmitted from the information card 4 thereafter can be made uniform for all information cards 4 in practical use. Accordingly, a device having a simple configuration can be applied as the information writing / reading device 2.

In general, when trying to read the information card 4 by the non-contact method as shown in FIG. 1, since the signal level of the response information signal W2 is weak, a filter having a filter characteristic as steep as possible to extract it is used. Although it is necessary to apply the filter, it is necessary to apply a filter having a considerably complicated configuration to extract the data when the data transmission speed actually fluctuates. You can lose sex.

(G2) Other Embodiments (1) In the above embodiment, the case where field effect transistors TR1 to TR4 as adjustable resistance elements are connected in parallel as the resistance value setting circuit 14A of the clock signal generation circuit 14 is described. As described above, instead of this, it may be configured to be connected in series as shown in FIG. 5, may be configured to be connected in series / parallel, or a resistor may be connected in series to each of the field-effect transistors TR1 to TR4. Various circuit configurations can be applied, such as weighting by inserting.

(2) In the above embodiment, the clock oscillation circuit 14
In the above, the case where the resistance constant R is changed when changing the oscillation frequency of the above is described, but the capacitance constant C may be changed instead.

(3) In the above-described embodiment, the case where a 4-bit counter is used as the adjustment data generation circuit 21B has been described. However, the number of bits is not limited to this, and various numbers of bits can be selected.

(4) In the embodiment described above, supplies the clock signal frequency adjustment signal S _CL to the information card 4 in the clock frequency adjustment mode, per reading information data read from the information memory 13, in a non-contact manner, transmission Although the antenna 3 supplies the response request signal W1 to the antenna 11 and receives the response information signal W2 from the antenna 11 to the reception antenna 5, the same reference numerals are given to the corresponding parts in FIG. 1 instead. As shown in FIG.
Adjustment signal connection holes 31A and 3 in antenna 11 of information card 4
1B is provided, and connection pins are provided in the adjustment signal connection holes 31A and 31B.
By inserting 32A and 32B, a signal line for transferring the adjustment signal S _ADJ to and from the adjustment device 33 is connected in a contact manner.

When adjusting device 33 of this embodiment supplies a clock signal frequency adjustment signal S _CL as described above for FIG. 3 (A) as a clock frequency adjusting mode adjustment signal S _ADJ, the read information data from the information memory 13 In response, a voltage change generated between the connection pins 32A and 32B is taken into the adjustment device 33 as information data.

In addition to this, in the case of this embodiment, the information writing mode adjustment device 33 supplies the information described above with reference to FIG. 2 to the information card 4 as the adjustment signal S _ADJ via the connection pins 32A and 32B. Information is written in the memory 13.

With the configuration as shown in FIG. 6, it is possible to realize an information card in which the clock signal of the clock signal generating circuit 14 can be adjusted by a contact method with respect to the information card 4.

(5) In the above embodiment, the response request signal W1 per superimposing a clock signal frequency adjustment signal S _CL, it has dealt with the case of modulating a carrier based on the pulse modulation method, the modulation scheme which The present invention is not limited to this and other modulation methods, for example, various modulation methods such as a frequency modulation method can be applied.

(6) In the above embodiment, as a means for irradiating the information card 4 with the response request signal W1 to obtain the response information signal W2, the reflectance of the 1/2 wavelength dipole antenna is changed according to the information data. Although the embodiment in which the configuration is applied has been described, other types of antennas such as a slit antenna may be applied as the antenna.

In addition, the method of generating the information good signal W2 is not limited to the reflection method.For example, after the response request signal W1 is once taken into the inside and subjected to predetermined processing, it is re-radiated from the antenna as the response information signal W2. For example, various types can be applied.

(7) In the information card 4 according to the above-described embodiment, the extraction of the clock signal and the extraction of the write data are executed by the hardware circuit means. You may do it.

(8) In the above, the embodiment using the IC card as the information card 4 has been described. However, the applicable information card 4 is not limited to this, and may be, for example, a tag for cargo, an identification tag for entrance and exit, a train The present invention can be widely applied to a case where a card-shaped thing such as a commuter pass or a shape other than the card-shaped is used.

(9) In the above embodiment, the adjustment data S _CTL (fourth
(FIG. 2), the case where the counter constituting the adjustment data generating circuit 21B is operated to count is described. Alternatively, the frequency division ratio of the read clock signal S2 may be changed.

H Effect of the Invention As described above, according to the present invention, a clock oscillation frequency adjustment circuit for adjusting the CR oscillation frequency of a clock signal generation circuit based on a frequency adjustment signal supplied from outside the information card is provided in the information card. As a result, when the information card is shipped from the factory, the CR
The oscillation frequency can be adjusted, so that an information card that can effectively suppress the variation in the transmission speed of the information data read from the information card in practice can be easily obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of an information card according to the present invention. FIGS. 2 and 3 are signal waveform diagrams for explaining a response request signal in an information data writing mode and a clock frequency adjusting mode. FIG. 5 is a block diagram showing a detailed configuration of the clock oscillation frequency adjusting circuit in FIG. 1, and FIGS. 5 and 6 are block diagrams showing another embodiment. 1 ... information card reading device, 2 ... information writing / reading device,
11 Antenna, 13 Information memory, 14 Clock signal generation circuit, 14A Resistance setting circuit, 14B CR oscillation circuit main body, 16 Received signal detection circuit, 21 Clock oscillation frequency adjustment Circuit, 21A: Buffer amplification circuit, 21B: Adjustment data generation circuit.

Claims (1)

(57) [Claims] 1. An antenna for receiving a received signal, a clock signal generating circuit comprising a CR oscillator, and an impedance variable circuit for varying the impedance of the antenna, wherein a clock signal obtained from the clock signal generating circuit is used. An information card configured to control the impedance variable circuit so as to change the impedance of the antenna according to the generated information data, based on a frequency adjustment signal supplied from outside the information card, An information card comprising a clock oscillation frequency adjustment circuit for adjusting a CR oscillation frequency of the clock signal generation circuit.