JPH02227792A - Information card - Google Patents

Abstract

PURPOSE:To prevent the dispersion of the transfer speed of read data from being generated by providing a regulating means, which can regulate the frequency of a read clock signal to read information from an information card, on the information card. CONSTITUTION:When an information card 4 is shipped from a factory, an information write/read device 2 is set in a clock frequency regulating mode, and the oscillating frequency of a clock signal generating circuit 14 is regulated. By a read clock signal S2 obtained from the circuit 14, the information data of an information memory 13 are read, and the data are transferred as a response information signal W2 to the information read device 2. When the device 2 detects that the oscillating frequency of the circuit is outside an allowable range, the device 2 sends a clock signal frequency regulating signal, and by the signal regulated data SCTL of a clock oscillating frequency regulating circuit 21 are altered. According to the alteration, the information data read speed of the memory 13 is regulated. Thus the transmission speed of the signal M2 transmitted from the card 4 to the device 2 is regulated.

Description

[Detailed description of the invention] The present invention will be explained in the following order.

A. Industrial field of application B. Overview of the invention C. Conventional technology Problems to be solved by the invention E. Means for solving the problems (Fig. 1) F. Effects (Fig. 1)
Figure) G Example (Figures 1 to 6) (G1) First Example (Figures 1 to 4) (G2) Other Examples (Figures 5 and 6) H Effects of the Invention A. Field of Industrial Application The present invention relates to an information card, particularly for information reading, and is intended to improve variations in clock frequency.

B. Summary of the Invention The present invention makes it possible to adjust the CR oscillation frequency in an information card, thereby effectively avoiding the possibility of variations in the transmission speed of read data.

C Conventional technology As a conventional information card, for example, 2.45 (C; Hz)
For example, a response request signal using a microwave as a carrier wave of 17
By irradiating the antenna to an antenna composed of a two-wavelength dipole antenna and controlling the reflectance of the antenna according to the information data read out from the information memory that is read out by the information output clock signal, the reflected waves are converted into response information. A method has been proposed in which the signal is sent back as a signal (Japanese Patent Application No. 63-6292).

D Problems to be Solved by the Invention However, in this type of information card, as a click signal generation means for generating information, which generates a clock signal for generating information, CR is used, which can be made small and thin using integrated circuit (IC) manufacturing technology. It is considered suitable to apply an oscillator.

However, in practice, the CR oscillator formed inside an IC has a fairly large variation (for example, about 3 times the reference frequency) due to variations in patterns during IC manufacturing.
There are problems that cannot be avoided.

Conventionally, the first method to solve this problem is to measure the oscillation frequency of each information card OCR oscillator at the time of shipment from the factory, rank it into multiple frequency ranges, and use the information card exclusively for the information card reading system to fit each rank. Methods are being considered to specify the use.

For example, information cards belonging to ranks that do not have high frequency accuracy are assigned to be used only for purposes that do not require frequency accuracy.

Incidentally, if the frequency of the clock signal for information output varies over a wide range, in order to read the transmitted information while following this for all information cards whose data transmission speed varies over the wide range, it is necessary to read the information transmitted while following this. , it is necessary to use a receiver with a more complicated configuration as the receiving device of the information reading system, and it is inevitable that the overall configuration of the information card reading system becomes more complicated.

The present invention has been made in consideration of the above points. For example, by making it possible to easily adjust the frequency of the CR oscillator installed in each information card to a predetermined standard tolerance range at the time of factory shipment, information This paper attempts to propose an information card that can further reduce variations in transmission speed.

Means for Solving Problem E In order to solve this problem, the present invention has a clock signal generation circuit 14 having a CR oscillator configuration, and successive clock signals S obtained from this clock signal generation circuit 14 are provided.
The information card 4 from which information data can be read out according to the method 2 is provided with a clock oscillation frequency adjustment means 21 for adjusting the CR oscillation frequency of the clock signal generation circuit 14.

By installing the clock oscillation frequency adjustment means 21 that can adjust the CR oscillation frequency of the clock signal generation circuit 14 in the F-effect information card 4, for example, when the information card 4 is shipped from the factory, the successive clock signals of the information card 4 can be adjusted. Variations in S2 can be effectively suppressed.

G example An embodiment of the present invention will be described in detail below with reference to the drawings.

(G1) First Embodiment In FIG. 1, ■ indicates the information card reading device as a whole, and a carrier wave consisting of a microwave of 2.45 (Gl(z)) is transmitted from the information writing/reading device 2 via the transmitting antenna 3. It is possible to irradiate a response request signal W1 having a response request signal W1 to an information card 4 made of, for example, an IC card, and to take in a response information signal W2 made of a reflected wave thereof into an information writing/reading bag W2 via a receiving antenna 5. ing.

The information card 4 has an antenna 11 made of, for example, a 172-wavelength dipole antenna, and a variable impedance circuit 12 made of, for example, a field effect transistor (FET) is connected between its feeding points P1 and 22.

To the control input terminal of the variable impedance circuit 12, the information data stored in the information memory 13 is read out by the successive clock signal S2 given from the clock signal generation circuit 14 and given as an output information data signal S1. Information data signal SL is logic rH or “L”
When the level is reached, the variable impedance circuit 12 changes the reflection characteristics of the antenna 11 and sends back the reflected wave as the response information signal W2.

In this case, the information writing/reading device 2 reads the information data of the output information data signal S1 based on the change in the phase of the carrier wave of the response information signal W2.

In this way, the information data stored in the information memory 13 is read out at a speed corresponding to the frequency of the read clock signal S2 given from the clock signal generation circuit 14, so that the information writing/reading device 2 can be read out at a speed corresponding to the frequency of the read clock signal S2 supplied from the clock signal generating circuit 14. It can be read continuously at a fixed data transmission rate.

In the case of this embodiment, the information data to be written in the information writing/reading device 2 is superimposed on the response request signal w1 in the information memory 13 of the information card 4 at the time of shipment from the factory via the antenna 11. Similarly, by superimposing clock oscillation frequency adjustment data for adjusting the frequency of the clock signal generation circuit 14 on the response request signal W1, the information card 4 is transmitted via the antenna 11. It is designed to be able to supply

That is, while one feeding point P1 of the antenna 11 is grounded, the received signal S3 obtained at the other feeding point P2 is supplied to the received signal detection circuit 16 having a half-wave rectifier circuit configuration consisting of a diode 16A and a capacitor 16B. Thus, a reception detection signal S4 corresponding to a change in the envelope of the reception signal S3 is obtained at the output end of the reception signal detection circuit 16.

Here, when the information reading device 2 writes information to the information card 4, as shown in FIG. The received signal detection circuit 16 sends out a signal pulse width modulated by the information data snt, and the received signal detection circuit 16 receives a received detection signal S4 whose signal level changes according to its envelope.
(FIG. 2(C)).

In this embodiment, the response request signal Wl (therefore, the received signal S
As shown in FIG. 2(A), the write information superimposed on 3) is transmitted during the write bit clock signal transmission period during the first 172 period period of the bit period TBIT corresponding to the write clock period of the information memory 13. Along with forming TCK, the second half
The clock signal SCK is transmitted to the information card 4 by forming a write bit data transmission period TDT in /2 cycle period and continuously emitting the problematic transmission wave of the write bit clock signal transmission period TCK, for example, the clock signal SCK is transmitted to the information card 4. The write clock time point is indicated by the downward direction.

In addition to this, the response request signal W1, in the write bit data transmission period TDo, sets a period of time T2 from the time when a predetermined time T has elapsed from the clock time of the write clock signal SCX as a write bit data period. By continuously emitting a carrier wave during the write bit data period T2, the write data D A T A wT (Fig. 2 (A)
), and at the same time transmits the "0" bit data of the write data DATA ur by stopping the emission of the problem transmission wave during the write bit data period T2. There is.

Thus, the response request signal W1 is transmitted during the write bit clock signal transmission period T. At K, the pulse width modulated write clock signal scK is repeatedly transmitted, and during the subsequent write bit data transmission period TIIT, the pulse width modulated bit data signal SDT is similarly transmitted.

The received signal S2 has the same envelope as the response request signal Wl (FIG. 2(B)), and this is detected by the received signal detection circuit 16 as the received detection signal 34 (FIG. 2(C)).
), and thus the reception detection signal S4 generates the write clock detection signal component SCKX at the timing of the write bit clock signal transmission period T''cK, and also generates the write clock detection signal component SCKX at the timing of the write bit data transmission period TDa. A data detection signal component S IITX is generated.

This reception detection signal S4 is given to the write data detection circuit 18, and the write data detection circuit 18 supplies the data write circuit 19 with detection data S5 corresponding to the reception detection signal S4, thereby generating a write clock and information. By supplying the write data signal S6 consisting of data to the information memory 13, the information data is taken into the information memory 13.

In addition to the above configuration, the information writing/reading device 2 in the clock frequency adjustment mode has a predetermined rising period as shown in FIG. TIO quantity information search signal W1
The amplitude of the carrier wave is further increased, and this is received by the information card 4 as a clock signal frequency adjustment signal ScL.

This clock signal frequency adjustment signal SCL is the received signal S3.
is given to the received signal detection circuit 16 as a reception detection signal S4 (see FIG.
B)) is supplied to the clock oscillation frequency adjustment circuit 21.

As shown in FIG. 4, the clock oscillation frequency adjustment circuit 21 receives the reception detection signal S4 (FIG. 3 (B)) from the amplifier circuit 21A and detects that the signal level of the envelope waveform SCLX exceeds the threshold level L5IIC. Then, the 8J1 adjustment pulse PctL (FIG. 3(C)) is sent to the adjustment data generation circuit 21B.

Here, the threshold level L of the buffer amplifier circuit 21A
S□. is selected to be a much higher level than the threshold level L SOD of the write data detection circuit 18, whereas the clock signal frequency adjustment signal S sent out from the information writing/reading device 2. The signal level L (FIG. 3(A)) is the write clock signal S sent out in the information write mode. K and the write data signal 5DT (FIG. 2 (B)) have a signal level envelope that is significantly higher than that of the signal level, so that the clock oscillation frequency adjustment circuit 21 can perform Even if the clock detection signal component SCXX and the write data detection signal component 5DTX are generated as the reception detection signal S4, the clock signal does not respond because the signal level does not exceed the threshold level LSHC. When the frequency adjustment signal Set arrives, the adjustment pulse PcA is generated in response to the arrival of the frequency adjustment signal Set.

The adjustment data generation circuit 21B is composed of, for example, a 4-bit counter, and performs a counting operation, for example, at the falling edge of each adjustment pulse PCTL, thereby generating adjustment data SCTL consisting of 4-bit count data B1 to B4. is supplied to the resistance value setting circuit 14A of the clock signal generation circuit 14.

The resistance value setting circuit 14A includes four field effect transistors TRI~ connected in parallel to each other as adjustable resistance elements.
Bit data B that has TR4 and is supplied to its gate
It is made to have a resistance value corresponding to 1 to B4.

This resistance value setting circuit 14A is connected to the CR oscillation circuit main body 14B as an oscillation constant circuit, so that the CR oscillation circuit main body 14B can be viewed from the capacitance value of the internal capacitor and the output end of the resistance value setting direction path 14A. The continuous clock signal S2 is generated by oscillating at a frequency determined by the combined resistance value.

In the above configuration, when the information card 4 is shipped from the factory, the oscillation frequency of the clock signal generation circuit 14 is adjusted by setting the information writing/reading device 2 to the clock frequency adjustment mode.

Here, the resistance value setting circuit 14 of the clock signal generation circuit 14
The resistance value of A continues to oscillate at an oscillation frequency according to the count contents in the adjustment data generation circuit 21B of the clock oscillation frequency adjustment circuit 21, and the information data in the information memory 13 is continuously generated by the successive clock signal S2 obtained thereby. The information data is then transmitted to the information writing/reading device 2 as a response information signal W2.

At this time, the information writing/reading device 2 receives the response information signal W.
2, the transmission speed of the information data, that is, the oscillation frequency of the clock signal generation circuit 14 is detected, and it is determined whether the oscillation frequency is within a predetermined tolerance range with respect to the reference frequency.

If it is detected that the oscillation frequency of the clock signal generation circuit 14 is not within the permissible range, the information writing/reading device 2 sends the clock signal frequency adjustment signal 5CL (see FIG. 3(A)).
), which causes the clock oscillation frequency adjustment circuit 2 to
The adjustment data S is generated by causing the counter of the adjustment data generation circuit 21B of No. 1 to perform a counting operation. Change TL by one force count operation.

At this time, as the resistance value of the resistance value setting circuit 14A changes, the oscillation frequency of the CR oscillation circuit main body 14B is adjusted accordingly, thereby increasing the information data successive output speed of the information memory 13 (therefore, the information data transmission speed). is adjusted.

In this way, the data transmission speed of the response information signal W2 transmitted from the information card 4 to the information writing/reading device 2 is adjusted, but the information writing/reading device W2 again adjusts the data transmission speed of the returned information data, thus Clock signal generation circuit 1
The oscillation frequency of the information card 4 is determined, and if it is not within the allowable range, the clock signal frequency adjustment signal ScL is sent to the information card 4 again.

In the same manner, the information writing/reading device 2 receives the response information signal W2.
The clock signal frequency adjustment signal SCL continues to be sent out until the transmission speed of the information data transmitted as oscillation frequency falls within a predetermined tolerance range with respect to the reference oscillation frequency, and in response, the adjustment data generation circuit 21B continues the counting operation. As a result, the resistance value of the resistance value setting circuit 14A and, therefore, the oscillation frequency of the CR oscillation circuit body 14B are adjusted.

Since the adjustment data generation circuit 21B is constituted by a quaternary counter, when the count reaches the maximum value, an overflow operation occurs due to the subsequent adjustment pulse PCTL, thereby continuing the cyclic counting operation.

When the oscillation frequency of the clock signal generation circuit 4 eventually falls within a predetermined tolerance range, it means that the clock frequency adjustment process for the information card 4 has been completed, and at this time the information writing/reading device 2 will no longer adjust the clock signal frequency. signal SC
This causes the adjustment data generation circuit 21B to maintain the adjustment completed state, and as a result, the oscillation frequency of the clock signal generation circuit 14 maintains the state at the time the adjustment was completed.

According to the above configuration, by making it possible to adjust the oscillation frequency of the clock signal generation circuit 14 having a CR oscillator configuration until it falls within a predetermined tolerance range, the CR oscillator OCR constant can be formed as an IC when manufacturing the information card 4, for example. Even if there are variations in the oscillation frequency of the clock signal generation circuit 14 due to variations in the timing, this can be reliably adjusted to an allowable range.

Therefore, if the oscillation frequency of the clock signal generation circuit 14 is adjusted at the time of shipment from the factory, the data transmission speed of the response information signal W2 sent from the information card 4 can be practically made the same for all information cards 4. , a simple configuration can be applied as the information writing/reading device 2.

Generally speaking, when trying to read the information card 4 using a non-contact method as shown in FIG. 1, the signal level of the response information signal W2 is weak, so in order to extract it, a filter with filter characteristics as steep as possible is used. However, in order to extract this data when the data transmission speed fluctuates, a filter with a fairly complex configuration is required. can have sex.

(G2) Other embodiments (1) In the above embodiment, the case where field effect transistors TRI to TR4 as adjustable resistance elements are connected in parallel as the resistance value setting circuit 14A of the clock signal generation circuit 14. However, instead of this, it is possible to connect them in series or in series and parallel as shown in Figure 5, or to connect them in series with each field effect transistor TR1 to TR4. Various circuit configurations can be applied, such as weighting by inserting .

(2) In the above embodiment, the clock oscillation circuit 14
Although the case has been described in which the resistance constant R is changed in order to change the oscillation frequency of the oscillation frequency, the capacitance constant C may be changed instead.

(3) Furthermore, in the above embodiment, a case has been described in which a 4-bit counter is used as the adjustment data generation circuit 21B, but the number of bits is not limited to this, and various numbers of bits can be selected.

(4) In the above embodiment, in the clock frequency adjustment mode, the clock signal frequency adjustment signal set is supplied to the information card 4, and when reading the information data read from the information memory 13, the transmission antenna is 3 to the antenna 11 as a response request signal W1, and received from the antenna 11 to the receiving antenna 5 as a response information signal W2. Instead, corresponding parts with those in FIG. 1 are given the same reference numerals. As shown in FIG. 6, the antenna 11 of the information card 4 is provided with adjustment signal connection holes 31A and 31B.
By inserting connection pins 32A and 32B into 1A and 31B, a signal line for receiving and passing the adjustment signal 5ADJ is connected to the adjustment device 33 in a contact manner.

In this embodiment, the adjustment device W33 supplies the clock signal frequency adjustment signal Set described above with reference to FIG. The voltage change occurring between the connecting pins 32A and 32B is taken into the adjustment device t33 as information data.

In addition, in this embodiment, the adjustment device 33 in the information write mode supplies the information card 4 with the signal described above with reference to FIG. Information is written in 13.

If configured as shown in FIG. 6, it is possible to realize an information card in which the clock signal of the clock signal generation circuit 14 can be adjusted by contacting the information card 14.

(5) In the above embodiment, the case was described in which the carrier wave was modulated based on the pulse modulation method when the clock signal frequency adjustment signal set was superimposed on the response request signal Wl. However, other modulation methods such as frequency modulation and other various modulation methods may be applied.

(6) In the above-mentioned embodiment, as a means to irradiate the information card 4 with the response request signal W1 and obtain the response information signal W2, the configuration is such that the reflectance of the 172-wavelength dipole antenna is changed according to the information data. Although an embodiment in which the present invention is applied has been described, other types of antennas such as a slit antenna may also be applied.

Furthermore, in order to generate the information reading signal W2, the method is not limited to the reflection method; for example, a method may be used in which the response request signal W1 is once internalized, subjected to predetermined processing, and then re-radiated from the antenna as the response information signal W2. Various methods can be applied.

(7) In the information card 4 in the above embodiment,
Although the clock signal extraction and the write data extraction are executed by hardware circuit means, instead of this, they may be realized using software means.

(8) In the above, an example in which an IC card is used as the information card 4 has been described, but the information card 4 that can be applied is not limited to this. It can also be widely applied to card-like objects such as commuter passes, and objects in shapes other than card-like objects.

(9) In the above embodiment, adjustment data 5CTL
(FIG. 4), the case has been described in which the counter constituting the adjustment data generation circuit 21B is operated to count, but instead of this, the successive clock signal S2
The frequency division ratio may be changed.

Effects of the Invention As described above, according to the present invention, the information card is provided with an adjustment means that can adjust the frequency of the continuous clock signal used when reading information from the information card. The frequency of the read clock signal can be adjusted when the information card is shipped from the factory, and thereby it is possible to easily obtain an information card that can effectively suppress variations in the transmission speed of information data read from the information card in practice.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of an information card according to the present invention, FIGS. 2 and 3 are signal waveform diagrams for explaining a response request signal in the information data write mode and the clock frequency adjustment mode, and FIG. This figure is a block diagram showing the detailed configuration of the clock oscillation frequency adjustment circuit of FIG. 1, and FIGS. 5 and 6 are block diagrams showing other embodiments. 1...Information card reading device, 2...Information writing/reading device, 11...Antenna, 13...
...Information memory, 14...Clock signal generation circuit, 14A...Resistance value setting circuit, 14B.
...CR oscillation circuit main body, 16 ... Received signal detection circuit, 21 ... Clock oscillation frequency adjustment circuit, 21A ... Buffer amplifier circuit, 21B.
...Adjustment data generation circuit.

Claims (1)

[Scope of Claims] An information card having a clock signal generation circuit configured as a CR oscillator and configured to read out information data using a read clock signal obtained from the clock signal generation circuit, wherein the clock signal generation circuit comprises: An information card comprising clock oscillation frequency adjustment means for adjusting the CR oscillation frequency.