JP2761249B2 - Pixel density conversion pulse generator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] A pixel density conversion pulse generation apparatus for generating a pixel density conversion pulse, which has versatility and requires a small capacity of a memory used for pixel density conversion. Conversion rate setting means for setting a reciprocal of a conversion rate; addition result storage means for storing an addition result of a stage immediately before an addition operation performed stepwise; Adding means for adding the output of the setting means and the output of the adding result storing means, and decimating a pulse corresponding to the pixel data of the next stage in the step from the addition result of the adding means, or leaving it as normal,
Alternatively, a predetermined period is provided, and one of the pixel data
And determining means for determining whether or not to output a plurality of pulses corresponding to each of them.

The present invention relates to a pixel density conversion pulse generation device that generates a pixel density conversion pulse.

With the recent increase in the speed of computer systems, the field of digitally processing and handling images has been increasing. In this digital processing, it is required to reduce and enlarge the original image data in order to output one original image data to various media. Therefore, it is necessary to generate a pixel density conversion pulse at any reduction / enlargement.

[Prior Art] An original image is converted to a line sensor, for example, a CCD (Charge-Coupled D).
evice) to obtain a pixel signal. As is well known, a light image from an original image is converted into a charge amount corresponding to the light intensity of a light image projected on a plurality of light receiving elements of a CCD, and a plurality of A pixel signal of a plurality of bits (dots) corresponding to the light receiving element is obtained.

The electric charges stored in each light receiving element of the CCD are sequentially transferred by a transfer clock and output from the CCD.

As a conventional pixel density conversion pulse generation device, there is one shown in FIG. 5, for example.

In FIG. 5, reference numeral 31 denotes a counter to which the above-described CCD transfer clock is input, 32 denotes a selector for selecting the counter value of the counter 31 and data from the system, that is, a selector for selecting pattern data of a thinning-out pulse or an enlarging pulse of a conversion rate, and 33 denotes a selector. RAM to which the output value selected by selector 32 is input, 34 is R
This is an OR circuit to which the output of AM33 and the transfer clock are input.
The RAM 33 stores a table in which a pattern of a thinning pulse or an enlarging pulse which is considered to be necessary, for example, a pattern shown in FIG. 6B is set. This pattern is provided by the system as described above.

The output of this device is shown in FIG. In FIG. 6, A
Indicates a transfer clock to be input, and B indicates an output of the RAM 33. In this example, a pulse is output at the third clock. C indicates a transfer clock after thinning, and D indicates a transfer clock at the time of enlargement.
The charge stored in each light receiving element of the CCD (not shown) is transferred at the rising edge of the transfer clock A. Is entered. The RAM 33 outputs a signal of a level corresponding to the count value of the counter 31 (the number circled in FIG. 6B). The output of RAM 33 is OR circuit 34
And supplied to, for example, a printer (not shown). In the printer, FIG. 6C output from the OR circuit 34,
One dot printing is performed at the rise of the D pulse.

Accordingly, when printing is performed using the pulse shown in FIG. 6C, the pixel signal when the count value of the counter 31 is "4" is not printed out of the pixel signals shown in FIG. This means that thinning has been performed.

When printing is performed by the pulse shown in FIG. 6D,
Of the pixel signals shown in FIG. 7A, when the count value of the counter 31 is "3", the pixel signal is printed twice, that is, two dots are printed. Therefore, the pixel corresponding to the pixel signal is printed in two dots and enlarged. It will be.

[Problems to be Solved by the Invention] However, in such a conventional pixel-density conversion pulse generation device, a pattern of a thinning-out pulse or an expansion pulse that is considered to be necessary is set in advance, and the table is referred to. By doing so, a thinning-out pulse or an expanded pulse is generated, so that there is a problem that the degree of freedom of the conversion rate is small and there is no versatility. On the other hand, in order to provide versatility, a large number of pixel density conversion pulse generation patterns must be registered in advance, so that a large memory capacity is required and the cost is increased.

SUMMARY OF THE INVENTION The present invention has been made in view of such conventional problems, and has as its object to provide a pixel density conversion pulse generator having versatility and requiring a small memory capacity.

[Means for Solving the Problems] FIG. 1 is an explanatory view of the principle of the present invention.

In FIG. 1, 1 is a conversion rate setting means for setting a reciprocal of a conversion rate, 2 is an addition result storage means for storing an addition result of a step (previous stage) immediately before a stepwise addition operation,
7 is an addition means for adding the output of the conversion rate setting means 1 and the output of the addition result storage means 2, and 8 is a function for thinning out the pulse corresponding to the pixel data of the next stage in the stage from the addition result of the addition unit 7. , Is a determination means for determining whether to output a plurality of pulses corresponding to pixel data, which are arranged as usual or provided with a predetermined period.

[Action] In the present invention, the reciprocal of the conversion rate is added,
Based on the result of the addition, it is determined whether the pulse of the next stage is thinned out, a plurality of pulses are output (enlarged), or the normal operation is performed.

For example, in the case of reduction to 4/5, the CCD transfer clock, which is a pulse corresponding to pixel data, may be masked once every five times. At that time, the reciprocal of the reduction ratio (1.25 in this case)
And add four times to raise the decimal part.
At this time, if the transfer clock of the next stage is masked, it is masked once every five times. Similarly, enlargement generates a conversion pulse by adding the reciprocal of the conversion rate.

Therefore, by simply changing the conversion rate (the reciprocal of the conversion rate), it is possible to generate a conversion pulse corresponding to a different conversion rate, and it is possible to greatly improve the degree of freedom of reduction and enlargement, and as a result, The versatility of the device can be improved.

Further, even if the versatility is given, the pattern information corresponding to the converted pulse is not required, so that the memory capacity does not need to be increased and the cost can be reduced.

[Example] Hereinafter, an example of the present invention will be described with reference to the drawings.

 2 to 4 are views showing an embodiment of the present invention.

First, the configuration will be described. Reference numeral 1 denotes a register (conversion rate setting means) for setting an integer part of a reciprocal of a conversion rate.
Here, an integer is set. This integer is provided as system data from the microprocessor. Reference numeral 2 denotes a register (addition result storage means) in which an initial value "0" is set and in which the addition result of the stage immediately before the stepwise addition operation is stored, an integer portion is stored here. 3
Are AND gates 3a-3f, OR gates 3g, 3
h, 3k, and a selector having inverters I _{1 to} I ₃ , and by controlling the output of the register 9, the pixel signal corresponding to this stage of the above-described addition operation [(i = 1, 1 in FIG. 6P)
2,... Signal), the output of the register 2 is selected, and other than the thinning, the output of the register 1 is selected. 4 is a register storing “−1”, 5 is a register storing “0”, and the selector 6 controls the output of the register 9 to select the output of the register 4 at the time of thinning like the selector 3 Then, the output of the register 5 is selected except at the time of thinning.
The selector 6 includes AND gates 6a to 6f, OR gates 6g, 6h, 6k,
An inverter I ₄ ~I _6. 1-1-1-3,2-1-2
-3,4-1 to 4-3 and 5-1 to 5-3 are signals of each bit of the 3-bit register. Reference numeral 7 denotes an adder (addition means). The adder 7 adds the output of the selector 3, the output of the selector 6, and the carry signal 10 from the decimal part of the adder 16. Reference numeral 8 denotes a discriminating unit (discriminating means) for thinning out the pulse of the next stage (next stage), keeping the pulse as it is (normal), or generating a pulse for enlargement according to the addition result of the adding operation performed stepwise. It is determined whether to generate (enlarge).

That is, as shown in FIG. 4, the discriminating unit 8 includes an invar 18, an OR circuit 19, and NOR circuits 20 and 21. When the addition result is 2 or more, the thinning signal is output. When the sum is less than 0, a normal signal is output, and when the addition result is 0 to less than 1, an enlarged signal is output. The outputs of these discriminating units 8 are held as "0" or "1" in the respective bits 9a to 9c of the register 9, and the values of the register 9, that is, the thinning pulse, the normal pulse,
Each of the enlarged pulses is output. A transfer clock is input to the register 9 for latching. The initial value of the register 9 is 9a = 0, 9b = 1, 9c = 0. Note that the selection signal from the register 9 is also input to the selectors 3, 6, and 15.

The value of each bit of the registers 9a to 9c is input to one input terminal of each of the AND gates 9d to 9f, and the other input terminal of each of the AND gates 9d to 9f has an H (high) level voltage V, a transfer clock, 6 A clock signal having a frequency twice the frequency of the transfer clock shown in FIG. The outputs of the AND gates 9d to 9f are input to the clock terminal of the flip-flop 9h via the OR (OR) gate 9g. The pixel signal shown in FIG. 6P is input to the data terminal of the flip-flop 9h. 9k is a signal source for generating a clock signal having a frequency twice as high as the transfer clock as shown in FIG. 6E.

Next, a decimal part for generating the carry signal 10 will be described with reference to FIG.

11 is a register in which the reciprocal of the conversion rate is set as system data from the microprocessor, 12 is a register in which a double part of the reciprocal of the conversion rate is set as system data from the microprocessor D, 13 is 0"
Is a register in which is set. The selector 15 normally outputs the output of the register 11 during normal operation,
At the time of thinning, the output of the register 13 is selected. 17
Is a register for storing the fractional part of the addition result of the previous stage obtained by the adder 16, and a transfer clock is input for latching. The adder 16 adds the output of the selector 15 and the output of the register 17 and outputs a carry signal 10 to the adder 7.
Output to

The selector 15 is configured to output the first to tenth bit signals 11-1 to 11-10 of the 10-bit register and the first to
AND gates 15 ₁ to 15 for receiving a 10 signal 9a~9c of each bit of the bit signal 12-1～12-10,3 bit register 9 ₃₀ and OR gate 15 which receives the outputs of the AND gates 15 ₁ to 15 ₃₀
a to 15j.

 Next, the operation will be described.

 First, the case of reduction will be described based on Table 1.

If the reduction rate is to be 4/5, for example, “1” is set in the register 1, “0.25” is set in the register 11, and “0.5” is set in the register 12.
Are set respectively.

The leftmost term in Table 1 shows the number of the transfer clock.

Preceding-stage discrimination: Indicates the discrimination value of the preceding stage of the register 9. The output values of the selectors 3, 6, and 15 are determined by the state of this item.

The output of the selector 15... When the value of the register 9 is thinned out, the register 13 is selected. Otherwise, the register 11 is selected.

Calculation result at the preceding stage: The value at the preceding stage of the adder 16

The addition result is added by the adder 16.

Repetition: The integer part of the adder 16. This is selector 3,6
Is added by the adder 7 together with the output.

Operation result at the previous stage: The result of the addition at the previous stage of the adder 7 stored in the register 2 is shown.

Output of the selector 3... If the value of the register 9 is thinned out, the register 2 is selected. Otherwise, the register 1 is selected and the value of the register 2 or 1 is output.

Output of the selector 4... If the value of the register 9 is thinned out, the register 4 is selected. Otherwise, the register 5 is selected, and the value of the register 4 or 5 is output.

The addition result of the adder 7 is shown.

Discrimination: thinning out when the output of the adder 7 is 2 or more, 1-2
If the value is smaller than 0, the discriminating unit 8 determines that the image is enlarged when the value is smaller than 0 to 1.

Pulse (output pulse of OR gate 9g): Indicates the number of pulses output for one transfer clock, where "1" is a normal pulse (that is, transfer pulse) and "2" is a pulse having twice the frequency of a normal pulse “0” indicates that the transfer pulse (clock) is masked and thinned out.

The fourth and ninth clocks in Table 1 are each a part of the thinning processing, and the next pulse is "0". As a result, when looking at the term of the pulse, once every five times is masked. ing.

 Therefore, the reduction ratio is 4/5.

Next, the case of enlargement will be described based on Table 2. Second
The table shows the operation of each register when the enlargement ratio is 4/3. “0” is set in the register 1, “0.75” is set in the register 11, and “0.50” is set in the register 12. Each register
Each output of 9,17,2, each output of selectors 15,3,6, adders 16,7
, The carry signal 10, the output of the discriminator 8 and the pulses are as shown in Table 2.

The second clock, the fifth clock, and the eighth clock in Table 2 each have a pulse of "2" in the enlargement processing part. A clock having a frequency twice as high as the reference clock is output at a rate, and as a result, 4/3 times as many pulses as the reference clock are output.

 Therefore, the magnification is 4/3.

The values determined by the conversion rates are stored in the registers 1 and 2 and the conversion pulses corresponding to the arbitrary reduction rate and the range of 1 to 2 are obtained by performing the addition and discrimination operations as described above. A conversion pulse corresponding to the enlargement ratio can be generated, and the degree of freedom in reduction and enlargement can be greatly increased. Therefore, versatility is large. In addition, it is not necessary to increase the memory capacity even if the versatility is provided.

[Effects of the Invention] As described above, according to the present invention, the reciprocal of the conversion rate is added, and the next stage pulse is thinned out, expanded, or remains normal depending on the addition result. In order to generate a conversion pulse corresponding to the conversion rate, it is sufficient if the memory has a capacity capable of storing a numerical value for determining the conversion rate and a numerical value necessary for the addition operation. There is no need to increase the conversion rate, and the conversion rate need only be set to the reciprocal of the conversion rate, so that the degree of freedom in reduction and enlargement can be greatly increased. As a result, the versatility of the device can be improved.

[Brief description of the drawings]

FIG. 1 is a view for explaining the principle of the present invention, FIG. 2 is a block diagram of an integer part showing one embodiment of the present invention, FIG. 3 is a block diagram of a decimal part, FIG. FIG. 5 is a diagram showing a conventional example, and FIG. 6 is a diagram showing each signal. In the figure, 1 ... register (means for setting the reciprocal of the conversion ratio), 2 ... register (addition result storage means), 3 ... selector, 4 ... register,
5 register, 6 selector, 7 adder (adding means), 8 discriminator (discriminating means), 9 register, 10 carry signal, 11-14 register, 15 selector, 16 ...
Adders, 17 registers, 18 inverters, 19 OR circuits, 20, 21 NOR circuits.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G06F 15/66 355

Claims (1)

(57) [Claims] A conversion rate setting means for setting a reciprocal of a conversion rate; an addition result storage means for storing an addition result obtained immediately before an addition operation performed stepwise; An adding means (7) for adding the output of the conversion rate setting means (1) and the output of the addition result storing means (2), and corresponding to the pixel data of the next stage in the stage based on the addition result of the adding means (7) Determining means (8) for determining whether to thin out the selected pulses, to keep them as normal, or to provide a predetermined period and output a plurality of pulses corresponding to one of the pixel data. A pixel density conversion pulse generation device, comprising: