JP2758509B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a technology for isolating a hetero-bipolar transistor.

FIG. 9 is a cross-sectional structural view of a so-called double heterostructure transistor using a semiconductor having a narrower energy band gap than that of a collector and an emitter as a material of a base layer, according to a conventional technique. As in the prior art shown in FIG. 9 P ^- -type on the semiconductor substrate 1 N ⁺ -type impurity buried layer 2 and the N ^- -type epitaxial <br/> catcher and Le layer 3 is formed, the P thereon ^- A P-type semiconductor film 4 (hereinafter referred to as a P-type base layer 4 ) having an energy band gap smaller than that of the P- type semiconductor substrate 1 is formed, and an N-type semiconductor having the same energy band gap as the P ⁻ -type semiconductor substrate 1 is further formed thereon. Film 5 (hereinafter referred to as N-type emitter layer 5)
) Is formed.

[0003] Then, the N ^- In areas other than the P-type base layer 4 formed region -type epitaxial layer 3 is thinner film thickness than the P-type base layer 4 formed region, the N ^- type epitaxial layer 3 An N ⁺ -type collector contact layer 7 having a depth reaching the N ⁺ -type impurity buried layer 2 is formed in a part of the thin region, and a depth reaching the P-type base layer 4 in a part of the N-type emitter layer 5. is the P ⁺ -type base contact layer 8 is formed, P on a part of the region other than the P ⁺ -type base <br/> over scan contact layer 8 of the N-type emitter layer 5 is formed
Type base layer 4 depth not reaching the of N ⁺ -type emitter contact layer 9 is formed, the N ⁺ -type collector contact layer
7 , P ⁺ type base contact layer 8 , N ⁺ type emitter capacitor
N ⁻ type epitaxial layer 3 other than the tact layer 9 forming region,
The surface of the P-type base layer 4 and the N-type emitter layer 5 has an oxide film 12
N ⁺ type collector contact layer
7 , P ⁺ type base contact layer 8 , N ⁺ type emitter capacitor
On the tact layer 9 , the collector electrode 13 , the base electrode 1
4, the emitter electrode 15 are formed. In the above description, ^{+ on} the right shoulder of P-type and N-type indicates a high impurity concentration, and ^- indicates a low impurity concentration.

[0004]

Since the conventional semiconductor device is configured as described above, when forming an integrated circuit by forming a plurality of transistors on the same semiconductor substrate, first, a buried collector layer is used. There is a problem that a certain N ⁺ -type impurity buried layer 2 becomes common and electrical isolation between elements cannot be performed. In addition, since there is a step between the base and emitter electrodes and the collector electrode, there is a variation in manufacturing accuracy due to disconnection of wiring at the step, an etching residue, and a focus shift during photoresist exposure above and below the step. There were problems such as occurrence.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and it is possible to electrically isolate elements from each other and to produce a semiconductor surface having no large steps and no variation in manufacturing accuracy. It is an object to provide an apparatus and a method for manufacturing the same.

[0006]

According to a first aspect of the present invention , there is provided a semiconductor device, comprising: a second conductive type semiconductor substrate on a first conductive type semiconductor substrate;
Buried collector layer and epitaxial layer
On which a second conductive layer is formed via a base layer of a first conductivity type.
Of the base layer is stacked.
-The band gap is above the buried collector layer, epitaxy
Semiconductor having a structure smaller than the char layer and the emitter layer
Embedded in a semiconductor device
A collector layer and an epitaxial layer;
A base layer formed on a partial area of the layer surface, and the base layer
An emitter layer formed on the epitaxial layer,
A collector layer formed simultaneously with the emitter layer;
To include at least a portion of the serial base layer, in which a said emitter <br/> capacitor layer groove-type partial delamination from the surface which is formed to a depth reaching the epitaxial layer. Also this
A semiconductor device according to a second aspect of the present invention corresponds to the first aspect.
In addition to the above configuration, between adjacent elements,
With groove-type element isolation provided through each layer
It is.

Further, according to a third aspect of the present invention , there is provided a method of manufacturing a semiconductor device , comprising the steps of:
Buried collector layer and epitaxial layer
Are laminated, and a second conductive layer is formed thereon via a first conductive type base layer.
Of the base layer by stacking
Band gap is buried collector layer, epitaxy
The material used is smaller than that of the
A method of manufacturing a semiconductor device having a first conductivity type.
A second conductivity type high concentration impurity buried core on a semiconductor substrate.
And a second conductive type epitaxial layer.
And a step of:
First conductor with narrower energy band gap than conductor substrate
Forming a base layer of an electric type;
An emitter layer of the second conductivity type on the base layer and the base layer.
Formation step and over the element isolation region near the adjacent element.
Of the depth reaching the semiconductor substrate from the surface of the emitter layer.
Forming a trench-type element isolation, and reducing the number of the base layers.
Also to include a portion, a groove-type partial delamination of depth reaching the epitaxial layer from the surface of the emitter layer and
And a process .

[0008]

According to the semiconductor device of the first aspect of the present invention, since the emitter layer is also formed on the epitaxial layer other than the base layer forming region, the step on the semiconductor surface is reduced. . Further, according to the semiconductor device of claim 2 of the present invention,
If, in addition to the above effects, a trench-type element isolation was further formed.
This makes it possible to achieve electrical isolation between elements.
You.

According to the method of manufacturing a semiconductor device of the third aspect of the present invention, since the emitter layer is also formed on the epitaxial layer other than the base layer forming region, the step on the semiconductor surface is reduced, and the step portion is formed. Disconnection of wiring, etching residue, and focus shift during photoresist exposure above and below a step are reduced.

[0010]

FIG. 1 is a sectional view of a semiconductor device (double heterostructure transistor) according to an embodiment of the present invention, in which an N ⁺ type impurity buried layer 2 is formed on a P ⁻ type semiconductor substrate 1.
And an N ⁻ -type epitaxial layer 3 is formed, and a P-type base layer 4 having an energy band gap narrower than that of the P ⁻ -type semiconductor substrate 1 is formed on a part of the epitaxial layer 3.
P ^- type semiconductor substrate 1 on the N ^- type epitaxial layer 3
N-type emitter layer 5 及 of the same energy band gap and
And an N-type collector layer 5a . Further, a groove-type element isolation layer 10 having a depth reaching the P ⁻ -type semiconductor substrate 1 from the surface of the N-type emitter layer 5 is formed on the outer periphery of the transistor, and P ⁺ is formed at the bottom of the groove-type element isolation layer 10. An N-type emitter layer 5 including at least a part of the P-type base layer 4 and an N-type collector layer.
N-type emitter layer 5 and the N-type collector in the boundary region of the data layer 5a
A trench isolation layer 11 having a depth reaching the N ⁻ type epitaxial layer 3 from the surface of the data layer 5 a is formed.

Hereinafter, the manufacturing method will be described with reference to FIGS. FIG. 2 shows a state in which an N ⁺ type impurity buried layer 2 is formed on a P ⁻ type semiconductor substrate 1 and an N ⁻ type epitaxial layer 3 is formed thereon. Then, as shown in FIG. 3, a P-type base layer 4 having a smaller energy band gap than the P ^-- type semiconductor substrate 1 is formed in a predetermined region on the N ^-- type epitaxial layer 3.

Next, as shown in FIG. 4, an N-type emitter layer 5 having the same energy band gap as the P ⁻ -type semiconductor substrate 1 is formed on the P-type base layer 4 and the N ⁻ -type epitaxial layer 3.

As shown in FIG. 5, an N-type emitter layer 5 is formed in a region to be an element isolation region around the transistor region.
A groove type element isolation layer 10 having a depth reaching the P ⁻ type semiconductor substrate 1 from the surface of the trench is formed, and a P ⁺ type channel cut layer 6 is formed at the bottom of the groove type element isolation layer 10. Note that an insulating material such as an oxide film is used as the material of the groove type element isolation layer 10.

Then, as shown in FIG.
A region including a part of the P-type base layer 4 has a depth from the surface of the N-type emitter layer 5 to the N ⁻ -type epitaxial layer 3.
The groove type separation layer 11 is formed. The insulating material is also used for the material of the groove-type separation layer 11 as in the case of the groove-type element separation layer 10. By forming the groove type separation layer 11, the N-type emitter layer 5 is formed.
Of the N ⁻ type epitaxial layer 3 is electrically separated.
N-type collector layer 5a directly in contact with.

Next, as shown in FIG. 7, the collector contact 16, the base contact 17, the emitter contact 1
On the surface of the surface and trench element isolation layer 10 and the trench isolation layer 11 of the N-type emitter layer 5 excluding the region of 8 to form an oxide film 12.

As shown in FIG. 8, N ⁺ is applied to the collector contact 16 from the surface of the N-type emitter layer 5.
An N ⁺ -type collector contact layer 7 having a depth reaching the impurity-buried layer 2 is formed, and a P ⁺ -type base contact having a depth reaching the P-type base layer 4 from the surface of the N-type emitter layer 5 is formed on the base contact 17. A layer 8 is formed, and an N ⁺ -type emitter contact layer 9 having a depth that does not reach the P-type base layer 4 from the surface of the N-type emitter layer 5 is formed on the emitter contact 18.

Thereafter, the N ⁺ type collector contact layer 7 , P
⁺ Type base contact layer 8 , N ⁺ type emitter contact
A collector electrode 13 , a base electrode 14 ,
An emitter electrode 15 is formed to obtain the structure shown in FIG.

As described above, according to this embodiment, the P-type base
Layers other than 4 forming region N ^- N also on type epitaxial layer 3
-Type emitter layer 5, from the N-type emitter layer 5 surface
The trench type element isolation layer 10 having a depth reaching the P ⁻ type semiconductor substrate 1
And a groove-type separation layer 11 having a depth reaching the N ⁻ -type epitaxial layer 3 from the surface of the N-type emitter layer 5 in a region including at least a part of the P-type base layer 4. , N ⁺ type impurity buried as a collector layer on the substrate
Even if the only layer 2 is formed on the entire surface, it can be separated from the adjacent element by the groove-type element isolation layer 10 and also on the N ⁻ -type epitaxial layer 3 other than the region where the base layer 4 is formed.
Since the N-type emitter layer 5 is formed, the base electrode 1
4, the step between the emitter electrode 15 and the collector electrode 13 is reduced, the disconnection of the wiring at the step, the etching residue, the focus shift at the time of photoresist exposure above and below the step, etc. are reduced, and the manufacturing accuracy is improved. be able to.

[0019]

As is evident from the foregoing description, according to the semiconductor device according to claim 1 of the present invention, the step of the semiconductor surface because it is also the emitter layer is formed on the epitaxial layer except base over scan layer formation region It is possible to obtain a high-density integrated circuit which is reduced. Claims of the present invention
According to the semiconductor device of the second aspect, in addition to the above effects,
Electrical isolation between elements can be achieved by the element isolation layer.

Further, according to the method of manufacturing a semiconductor device according to claim 3 of the present invention, since the formation of the emitter layer to the base layer formation regions other than the d pita <br/> Kisharu layer, the semiconductor surface Steps are reduced, there is no disconnection of wiring and etching residues at the steps, and differences in shape and dimensions at the top and bottom of the steps are also reduced.
There is an effect that a stable and highly reliable semiconductor device can be obtained.

[Brief description of the drawings]

FIG. 1 is a sectional structural view of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a sectional structural view of each main step in a method of manufacturing a semiconductor device according to one embodiment of the present invention.

FIG. 3 is a sectional structural view of each main step in the method for manufacturing a semiconductor device according to one embodiment of the present invention;

FIG. 4 is a sectional structural view of each main step in a method of manufacturing a semiconductor device according to one embodiment of the present invention;

FIG. 5 is a sectional structural view showing main steps in a method of manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 6 is a sectional structural view of each main step in the method for manufacturing a semiconductor device according to one embodiment of the present invention;

FIG. 7 is a sectional structural view of each main step in the method of manufacturing a semiconductor device according to one embodiment of the present invention;

FIG. 8 is a sectional structural view of each main step in the method for manufacturing a semiconductor device according to one embodiment of the present invention;

FIG. 9 is a sectional structural view of a semiconductor device according to the related art.

[Explanation of symbols]

Reference Signs List 1 P ⁻ type semiconductor substrate 2 N ⁺ type impurity buried layer 3 N ⁻ type epitaxial layer 4 P type base layer 5 N type emitter layer 5 a N type collector layer 6 P ⁺ channel cut layer 7 N ⁺ type collector contact layer 8 P ⁺ Type base contact layer 9 N ⁺ type emitter contact layer 10 groove type element separation layer 11 groove type separation layer 12 oxide film 13 collector electrode 14 base electrode 15 emitter electrode 16 collector contact 17 base contact 18 emitter contact

Claims (3)

(57) [Claims] A buried collector layer of a second conductivity type and an epitaxial layer are sequentially laminated on a semiconductor substrate of a first conductivity type, and an emitter layer of a second conductivity type is disposed thereon via a base layer of the first conductivity type. A semiconductor device having a structure in which the energy band gap of the base layer is smaller than that of the buried collector layer, the epitaxial layer, and the emitter layer. A base layer formed in a partial region of the surface, an emitter layer formed on the base layer , a collector layer formed simultaneously with the emitter layer on the epitaxial layer, and at least one of the base layers Part to include
From the surface of the
A semiconductor device comprising: a formed groove-type separation layer . Wherein between adjacent elements, the upper from the substrate surface
Having a groove-type element isolation provided through each layer.
The semiconductor device according to claim 1, wherein: 3. A semiconductor device of a second conductivity type on a semiconductor substrate of a first conductivity type.
Buried collector layer and epitaxial layer
And a second conductive type is formed thereon via a first conductive type base layer.
Of the base layer.
The gap is the buried collector layer, epitaxial
Materials smaller than layers and emitter layers were used
In a method of manufacturing a semiconductor device, a high concentration impurity of a second conductivity type is formed on a semiconductor substrate of a first conductivity type.
Buried collector layer and second conductivity type epitaxial
Stacking layers , and providing the semiconductor substrate in a predetermined region on the epitaxial layer.
Of the first conductivity type having a narrower energy band gap than
Forming a source layer and forming a second conductive layer on the epitaxial layer and the base layer.
Forming a conductive type emitter layer, and forming the emitter layer in an element isolation region near an adjacent element.
A trench-type element isolation layer having a depth reaching the semiconductor substrate from the surface.
Forming, and forming the above-mentioned emitter so as to include at least a part of the above-mentioned base layer.
Of the depth reaching the epitaxial layer from the surface of the
Forming a groove-type separation layer .