JP2757767B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming an interlayer insulating film of a semiconductor device.

[0002]

2. Description of the Related Art High integration of a semiconductor device has been realized by miniaturization of wiring constituting the semiconductor device, multi-layering, reduction of wiring intervals, and the like. The characteristics required for the interlayer insulating film are also evolving along with these. The characteristics required for the interlayer insulating film are mainly related to the workability of the upper wiring formed on the upper surface of the interlayer insulating film. That the upper surface of the interlayer insulating film is excellent at least and is smooth,
This is because the embedding property of the gap between two adjacent lower wiring layers is excellent. When the lower wiring is composed of a gate electrode and a diffusion layer, a reflowed PSG film or BPSG film is used as an interlayer insulating film satisfying the above requirements. For example, since the reflow of the BPSG film requires a heat treatment at a temperature of 800 ° C. or more, when the main material of the lower wiring is an aluminum-based metal, copper, or gold, the BPSG film or the PSG film is not used as an interlayer insulating film. Appropriate.

As described above, in the case of the lower wiring in which aluminum-based metal, copper or gold is a main material, tetraethoxysilane (Si) is used as an interlayer insulating film satisfying a part of the above requirements.
(OC ₂ H ₅ ) ₄ ; TEOS) A silicon oxide film (hereinafter referred to as an ozone TEOS oxide film) formed by a thermal chemical vapor deposition method (thermal CVD) using a gas obtained by bubbling a solution with an inert gas (for example, nitrogen gas) and an ozone gas. There is). These thermal CVDs can be used at temperatures below 500 ° C.
The thermal CVD in this case is performed by an atmospheric pressure chemical vapor deposition (APCV) method.
D) or low pressure chemical vapor deposition (LPCVD). Even when the surface of the underlying substrate has severe irregularities, the ozone TEOS oxide film deposited on the surface of the substrate has excellent step coverage with respect to the underlying surface and its upper surface is smooth. APCVD using ordinary monosilane (SiH ₄ ) gas and oxygen gas
When an organic silane gas is used as a part of the source gas as in this thermal CVD, as compared with the case where an inorganic silane gas is used as a part of the source gas, a reactive gas such as TEOS adsorbed on the base substrate surface is used. This is because electrophoresis (migration) of molecules on the substrate surface (this electrophoresis is performed until silicon oxide is formed) is active.

When the semiconductor substrate is made of a silicon substrate,
The above-mentioned ozone TEOS oxide film has a thickness of 10
It is known to have a tensile stress on the order of ⁸ Pa. Therefore, if the interlayer insulating film is formed only of the ozone TEOS oxide film, cracks are likely to occur. One of the countermeasures against this is disclosed in, for example, JP-A-3-29345. With reference to FIG. 9 which is a schematic cross-sectional view of a semiconductor device, the gist of the configuration described in the above publication is schematically described as follows.

The semiconductor substrate 30 is interposed via a base insulating film 311.
A plurality of lower layer wirings 321 having a desired width and a desired interval are provided on 1. These lower wirings 321 are covered with an interlayer insulating film, and an upper wiring 361 is provided on the surface of the interlayer insulating film. This interlayer insulating film is made of TEO
Plasma excited chemical vapor deposition (PEC) using a gas obtained by bubbling an S solution with an inert gas and an oxygen gas as source gases.
VD), a silicon oxide film having a predetermined thickness (hereinafter referred to as a plasma TEOS oxide film) and an ozone TEOS having a predetermined thickness.
Oxide films are alternately stacked. This PECVD is also 5
Can be used at temperatures below 00 ° C. The structure of the interlayer insulating film will be described more schematically. The silicon oxide film 331 that directly covers the upper surface and the side surface of the lower wiring 321 and the silicon oxide film 333 in which the bottom surface of the upper wiring 361 is in direct contact
Is a plasma TEOS oxide film, and a silicon oxide film 3
The silicon oxide film 332 sandwiched between the silicon oxide film 33 and the silicon oxide film 331 is an ozone TEOS oxide film. The silicon oxide films 331 and 333 have a compressive stress on a silicon substrate, for example. Therefore, the silicon oxide film 33
1, silicon oxide film 332 and silicon oxide film 333
In the interlayer insulating film formed by laminating, the stress is relaxed,
The generation of cracks is suppressed.

[0006]

The ozone TEOS oxide film has characteristics that the amount of water remaining in the film cannot be ignored and that it has a high water vapor adsorption property. According to the measurement by the present inventors, for example, ozone T immediately after forming a film at 400 ° C.
In the case of an EOS oxide film, an —OH group (wave number 3400 cm ⁻¹ )
Has an infrared absorption (FT-IR) spectrum absorption coefficient of 18
0 cm ^-1 (for a silicon oxide film by thermal oxidation, a plasma TEOS oxide film, a silicon oxide film by thermal CVD using an inorganic silane gas as a part of the source gas, or the like, this F
The absorption coefficient of T-IR is smaller than the measurement limit). Due to the presence of moisture, the relative dielectric constant ε _r at 1 MHz (however, indirect measurement) of the ozone TEOS oxide film immediately after the film formation is about 4.3, and the silicon oxide film formed by ordinary thermal oxidation The value is larger than the relative dielectric constant (ε _r = 3.9 to 4.0).

When the lower wiring is made of an aluminum-based metal, copper or gold, the interlayer insulating film described in the above-mentioned publication is certainly preferable from the viewpoint of suppressing cracks. However,
Due to the above characteristics of the ozone TEOS oxide film, even with the interlayer insulating film having this structure, the contact resistance between the upper wiring and the lower wiring via the through hole provided in the interlayer insulating film is low. There is a problem that it does not. Further, since the relative dielectric constant of the ozone TEOS oxide film is high (due to the presence of moisture), the stray capacitance between the upper wiring and the lower wiring increases, which hinders the speeding up of the semiconductor device. Furthermore, in a semiconductor device including a MOS transistor, there is a problem that the threshold voltage of the MOS transistor shifts in a high-temperature bias test due to the influence of moisture in the ozone TEOS oxide film.

In a semiconductor device including a MOS transistor (a lower wiring is composed of a gate electrode and a diffusion layer such as a source / drain region), an interlayer insulating film between the gate electrode and the upper wiring is as described above. Generally, it can be formed by reflowing a BPSG film or the like. When this MOS transistor has a source / drain region having a salicide structure, there is a problem similar to the case where the lower wiring is made of aluminum-based metal, copper or gold. Taking a source / drain region of a salicide structure using titanium silicide as an example, when the temperature is increased to about 650 ° C. or more, the crystal structure of titanium silicide is changed and the specific resistance is increased. The reflow temperature of the BPSG film is at least 750 ° C
It is about. In order to remove the water absorption of the BPSG film, at least the glass transition point of the BPSG film, 700
High-temperature heat treatment at about ° C is required. Therefore, in this semiconductor device, it is not preferable to use a BPSG film or a PSG film as the interlayer insulating film that directly covers the gate electrode and the like.

Accordingly, an object of the present invention is to provide a method of forming an interlayer insulating film between a lower wiring and an upper wiring, including a case where a source / drain region having a salicide structure is used as a lower wiring. It is an object of the present invention to provide a method for forming an interlayer insulating film having excellent water step coverage on wiring and suppressing generation of cracks and having a low water content. It is still another object of the present invention to reduce an increase in contact resistance and an increase in stray capacitance between an upper layer wiring and a lower layer wiring, and in a semiconductor device including a MOS transistor, an interlayer for suppressing a variation in a threshold voltage of the MOS transistor. An object of the present invention is to provide a method for forming an insulating film.

[0010]

According to a first aspect of the method of manufacturing a semiconductor device of the present invention, a step of forming a lower insulating film having a smooth upper surface covering a surface of a silicon substrate provided with a predetermined semiconductor element on the surface is provided. Forming a plurality of lower wirings on the surface of the lower insulating film;
Forming a first silicon oxide film covering the exposed surface directly exposed surfaces and the lower insulating film of the lower layer wiring, m
The surface of the first silicon oxide film is formed by thermal CVD using an ozone gas and a gas obtained by bubbling a hydrogenated silsesquioxane ((HSiO _3/2 ) _2m ) solution containing an integer of 4 or more and 10 or less. The second that covers directly
Forming an organic SOG film on the second silicon oxide film, performing etch-back by reactive ion etching, and planarizing the upper surface of the second silicon oxide film. And a second PEC
Forming a third silicon oxide film directly covering the upper surface of the planarized second silicon oxide film by VD; and forming the third, second and first oxide films using a photoresist film as a mask. A step of forming a plurality of through holes reaching predetermined positions of the lower wiring by sequentially etching the silicon film; and a step of forming a plurality of upper wirings on the surface of the third silicon oxide film. .

[0011] Preferably, the lower insulating film has a flattened top surface, the first and silane gas second PECVD respectively and nitrous oxide gas, bubbling gas and oxygen gas by the TEOS solution inert gas ,
A gas obtained by bubbling a trialkoxysilane solution with an inert gas and an oxygen gas, or m is 4 or more and 10 or more
A gas obtained by bubbling a hydrogenated silsesquioxane solution consisting of the following integer with an inert gas and a mixed gas of oxygen gas as a source gas, and the first or second PECVD The trialkoxysilane used is any of trimethoxysilane, triethoxysilane, trinormalpropoxysilane and trinormalbutoxysilane .

According to a second aspect of the method of manufacturing a semiconductor device of the present invention, a smooth lower surface insulating film comprising a field insulating film and a gate insulating film is formed on a surface of a one-conductivity type silicon substrate. Forming a plurality of gate electrodes on the surface of the film, forming a plurality of diffusion layers having a reverse conductivity type and a salicide structure on the surface of the silicon substrate;
Forming a first silicon oxide film covering the lower insulating film including the gate electrode and the diffusion layer by VD; and hydrogenating silsesquioxane ((HSiO ₃₎ wherein m is an integer of 4 or more and 10 or less. _{/ 2} ) _2m ) Thermal CVD using ozone gas and a gas obtained by bubbling a solution with an inert gas
Forming a second silicon oxide film directly covering the surface of the first silicon oxide film, and forming an organic SOG film on the second silicon oxide film by reactive ion etching. Perform etch back, this second
Flattening the upper surface of the silicon oxide film of
Forming a third silicon oxide film directly over the planarized upper surface of the second silicon oxide film by ECVD; and forming the third, second and first oxide films using a photoresist film as a mask. Forming a plurality of contact holes respectively reaching a predetermined position of the gate electrode and a predetermined position of the diffusion layer by sequentially etching the silicon film; and forming a plurality of upper layers on the surface of the third silicon oxide film. Forming a wiring.

Preferably, the base insulating film has a substantially planarized upper surface, and the first PECVD is a plasma-enhanced chemical vapor deposition method using silane gas and nitrous oxide gas as source gases, or m is 4 or more. Must be an integer of 10 or less
A gas obtained by bubbling a hydrogenated silsesquioxane ((HSiO _3/2 ) _2m ) solution with an inert gas and a plasma-excited chemical vapor deposition method using an oxygen gas as a source gas. PECVD is a plasma-enhanced chemical vapor deposition method using silane gas and nitrous oxide gas as source gases, a plasma-enhanced chemical vapor deposition method using a gas obtained by bubbling a TEOS solution with an inert gas and an oxygen gas as a source gas, trialkoxysilane A plasma-enhanced chemical vapor deposition method using a gas obtained by bubbling a solution with an inert gas and an oxygen gas as a source gas, or m is 4 or more and 1
Hydrogenated silsesquioxane consisting of an integer of 0 or less ((H
SiO _3/2 ) _2m ) The plasma- enhanced chemical vapor deposition method using a gas obtained by bubbling a solution with an inert gas or an oxygen gas as a source gas, and the second PECVD method
The trialkoxysilane used in the, trimethoxysilane, triethoxysilane, either tri-n-propoxy silane and tri-n-butoxy silane Oh
You.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Prior to the description of the embodiments of the present invention, the steps leading to the present invention will be described. 500 silicon oxide films
PECVD can be formed at a temperature lower than or equal to
And thermal CVD. The silicon oxide film formed by PECVD has a compressive stress on the silicon substrate, the silicon oxide film formed by thermal CVD has a tensile stress on the silicon substrate, and the lower wiring and the upper wiring excluding the diffusion layer are generally formed on the silicon substrate. On the other hand, it has tensile stress. As an interlayer insulating film having a structure in which stress applied to a silicon substrate is relieved, the step coverage is excellent, and the upper surface is at least smooth, PE is used.
A silicon oxide film formed by CVD and a silicon oxide film formed by thermal CVD are alternately laminated, and the lowermost layer and the uppermost layer are formed of PEC.
The structure composed of a silicon oxide film by VD is excellent.
Therefore, thermal CVD for forming a silicon oxide film having excellent step coverage and low water content is important, and the pursuit of a raw material gas that enables this is more important.

Focusing on the difference in step coverage between the ozone TEOS oxide film and the silicon oxide film obtained by thermal CVD using monosilane gas and oxygen gas, the ozone TEOS
The superiority of the oxide film relates to the distance of surface migration that can occur from the time when molecules (or clusters) of the material gas to be oxidized adhere to the base and are oxidized. The vapor pressure of TEOS gas is lower than that of silane gas, TEOS can be gasified under normal pressure, and TEOS molecules have a larger molecular weight than silane molecules. With regard to water content, TEOS molecules hydrogen silane is replaced with all ethoxy (-OC ₂ H _5). For this reason, oxidation is difficult to be performed completely. Based on such considerations, the following predictions were made. Alkoxysilane in which all hydrogens are substituted with an alkoxy group such as TEOS (tetraalkoxysilane (Si (OR) ₄ )
And an alkoxysilane in which some of the alkoxy groups are substituted with hydrogen (for example, trialkoxysilane (HSi (O
R) ₃ ))) is closer to silane in chemical structure. These alkoxysilanes are more easily oxidized than TEOS,
Therefore, it is considered that a silicon oxide film having a smaller water content than an ozone TEOS oxide film can be obtained by such thermal CVD using an alkoxysilane gas and an ozone gas as source gases.

Based on the above hypothesis, investigations were made on alkoxysilanes other than tetraalkoxysilane. Monoalkoxysilane (H ₃ Si (OR) 2) and dialkoxysilane (H ₂ Si (OR) ₂ ) are unstable, and the yields by chemical synthesis are small and unsuitable. On the other hand, among the trialkoxysilanes, trimethoxysilane (HSi (OCH ₃ ) ₃ ) and triethoxysilane (HS
_{i (OC 2 H 5) 3} ), tri-n-propoxy silane _{(HSi (n-OC 3 H} 7) 3) and tri-n-butoxy silane _{(HSi (n-OC 4 H} 9) 3) is (room temperature, normal pressure Gasification (evaporation) by bubbling is easy. A trialkoxysilane having a molecular weight higher than this is not easy to gasify (since the vapor pressure at normal temperature and normal pressure is too low). These trimethoxysilane, triethoxysilane, trinormalpropoxysilane and trinormalbutoxysilane form a liquid phase at normal temperature and normal pressure. Each of these solutions is placed in a constant temperature bath at a predetermined temperature, and nitrogen gas is bubbled thereinto. Each silicon oxide film was obtained by thermal CVD in which the ozone gas was reacted at a temperature of about ° C.

For example, a silicon oxide film obtained by using triethoxysilane has the following characteristics. This silicon oxide film immediately after film formation has an —OH group (wave number 3400).
cm ^-1 ), the absorption coefficient of the FT-IR spectrum is 110c.
m ^-1 which is about 60% of the absorption coefficient of the ozone TEOS film.
It is about. This absorption coefficient of the ozone TEOS film does not change much with changes in the substrate temperature. On the other hand, when triethoxysilane is used, the absorption coefficient of the silicon oxide film greatly depends on the substrate temperature.
As the temperature rises to 0 ° C., the absorption coefficient decreases to about 95 cm ⁻¹ . If the silicon oxide film is left in the air after the film formation, this silicon oxide film also adsorbs water vapor in the air similarly to the ozone TEOS oxide film, but the degree is lower than that of the ozone TEOS oxide film. Note that the adsorption here is for water vapor, and the adsorption for water (and an organic solvent or the like) as a liquid phase is extremely small. Although it is an indirect measurement, the relative dielectric constant ε _r at 1 MHz of this silicon oxide film immediately after film formation is 4.0 to 4.1, and the ozone T
The value is smaller than the relative dielectric constant (ε _r ≒ 4.3) of the EOS oxide film. Thermal CV of alkoxysilane gas and ozone gas
Is the -OH group is formed by D, a portion of the reaction with · O radicals and -OC _n H _{2n + 1} from the _{ozone, (-OC n H 2n + 1} ) + 3n (· O) → ( -OH) + nC
It is considered that O ₂ ↑ + nH ₂ O ↑. The difference in the amount of -OH groups in the silicon oxide film using the triethoxysilane gas with respect to the silicon oxide film using the TEOS gas and the substrate temperature dependence of this amount cannot be explained only by the ratio of the ethoxy groups in one molecule. It is presumed that the presence of hydrogen has a large effect.

The above trialkoxysilanes are organic oxysilanes, but it is expected that in the series of inorganic oxysilanes having no bond to an alkoxy group, the number of -OH groups will be further reduced. As a series of inorganic oxysilanes, hydrogenated silsesquioxane ((HSiO _3/2 ) _2m : m is a positive integer)
We examined the possibility of using it as a source gas. It must be possible to gasify under normal pressure and its molecular weight must be sufficiently larger than monosilane molecules. As a material satisfying these conditions, among hydrogenated silsesquioxanes ((HSiO _3/2 ) _2m ), those having m ≦ 10 can be gasified under normal pressure. Nitrogen gas is bubbled through the hydrogenated silsesquioxane solution of m ≦ 10,
Each silicon oxide film was obtained by thermal CVD in which the ozone gas was reacted at a temperature of about ° C. The -OH groups (wave number 3400c) of these silicon oxide films immediately after film formation
The absorption coefficient of the FT-IR spectrum of m ^-1 ) is less than the measurement limit when m ≧ 4. On the other hand,
When m <4, the amount of -OH groups in the obtained silicon oxide film is larger than that in the ozone TEOS film. In a silicon oxide film obtained by using hydrogenated silsesquioxane with m = 4, the relative dielectric constant ε at 1 MHz of this silicon oxide film immediately after film formation is obtained.
_r (however, indirect measurement) is about 4.0.
Further, unlike the ozone TEOS oxide film or the silicon oxide film using triethoxysilane gas described above, this silicon oxide film is considered to have a low water vapor adsorption property. No increase in the absorption coefficient of the -OH group is observed. This is presumably because Si-H bonds are formed in this film.

Next, manufacture of a semiconductor device related to the present invention.
A method reference example and an embodiment of the present invention will be described with reference to the drawings.

Referring to FIGS. 1 and 2 which are schematic cross-sectional views of a semiconductor device manufacturing process and FIG. 3 which is a schematic view of a thermal CVD apparatus, a method of manufacturing a semiconductor device according to the present invention will be described.
A reference example (hereinafter simply referred to as a reference example) is as follows.

First, a 700 ° C. LPCV using silane gas and nitrous oxide (N ₂ O) gas is applied on the surface of a silicon substrate 101 on which a predetermined semiconductor element (not shown) is formed.
D silicon oxide film (HTO
40) using ozone gas, TEOS gas, trimethoxyborate (B (OCH ₃ ) ₃ ; TMB) gas and trimethyl phosphate (PO (CH ₃ ) ₃ ; TMP) gas.
A BPSG film having a thickness of about 0.5 μm is formed by thermal CVD at 0 ° C. A heat treatment is performed at 800 ° C. for 30 minutes in a nitrogen gas atmosphere, and the BPSG film is reflowed to form a lower insulating film 111. The upper surface of the lower insulating film 111 is
It is smooth but uneven and not flat. The step between the highest position and the lowest position on the upper surface of the lower insulating film 111 is about 0.6 μm.

Next, a contact hole (not shown) reaching the semiconductor element is formed at a predetermined portion of the lower insulating film 111, and a titanium film 121a having a thickness of about 0.06 μm and a thickness of 0 is formed by sputtering or reactive sputtering. .
A titanium nitride film 122a of about 1 μm, an aluminum-copper-silicon alloy film 123a of about 0.6 μm and a titanium nitride film 124a of about 0.05 μm are sequentially deposited. By patterning these four-layered metal films, a lower wiring 125A, a lower wiring 125B, a lower wiring 125C, a lower wiring 125D, and the like are formed (FIG. 1A). The film thickness and minimum line width of these lower wirings (for example, lower wiring 125
B) and the minimum line spacing (for example, between the lower wiring 125C and the lower wiring 125D) are 0.8 μm and 0.6 μm, respectively.
μm and about 0.6 μm.

Subsequently, by a first PECVD using a TEOS gas obtained by bubbling the TEOS solution with a nitrogen gas and an oxygen gas, a film thickness of about 0.2 m made of a plasma TEOS film (in a portion where the base is flat). First)
A silicon oxide film 131 is deposited on the entire surface [FIG.
(B)]. The film forming conditions of this PECVD are as follows:
0 ° C., pressure 1200 Pa, nitrogen gas flow rate for bubbling 450 sccm (standard cm ³ per
min. , A frequency of 13.56 MHz and a power of 400 W. This silicon oxide film 131 has a compressive stress of the order of 10 ⁸ Pa with respect to the silicon substrate 111,
The step coverage in a narrow sense (coverability only in the vicinity of the step portion, not including filling property in a narrow void portion) is excellent. Silicon oxide film 131 on side surfaces of lower layer wiring 125A and the like
Has a thickness of about 1.0 to 1.5 μm.

Next, triethoxysilane (HSi (OC
By thermal CVD using ₂ H _{5) 3)} solution was vaporized by bubbling with nitrogen gas gas and ozone gas, to form a second silicon oxide film 132. The silicon oxide film 132 has a tensile stress on the order of 10 ⁸ Pa with respect to the silicon substrate 111. The thickness of the silicon oxide film 132 in a flat portion of the base over a wide range is about 1.7 μm. This silicon oxide film 132 has a thickness of 2.5 μm.
Up to about m, a film can be formed without generating cracks. The (highest) step between the highest position and the lowest position on the upper surface of the silicon oxide film 132 is about 1.4 μm. The step coverage (in a broad sense) of the silicon oxide film 132 is excellent, though not as large as that of the ozone TEOS film. For example, the silicon oxide film 1 on the upper surface of the lower wiring 125A
32 is about 0.2 μm, the lower wiring 125A
The thickness of the silicon oxide film 132 on the side surface is about 0.2 μm. At this time, the lower wiring 125B and the lower wiring 1
The film thickness in the gap between 25C is about 1.0 μm, and the gap is completely filled with the silicon oxide film 132, thereby avoiding generation of voids and the like. However, the shape of the upper surface of the silicon oxide film 132 is different from the upper surface of the reflowed BPSG film, and is as follows.
The curved surface that covers one step of the base is generally smooth,
The vicinity of the intersection of the two curved surfaces respectively covering the two adjacent steps is not very smooth.

An example of a device for using the silicon oxide film 132 and film forming conditions will be described. This equipment is
The semiconductor substrate 189 is an APCVD apparatus.
It is placed on the face 87 in a face-down manner. The semiconductor substrate 189 is heated to about 400 ° C. by the heater 188 incorporated in the susceptor 187. The reaction gas is exhausted after flowing into the reaction chamber 185 from the dispersion head 186. First, the flow controller 181
a, 181c is closed, and only the flow controller 181b is opened, and the reaction chamber 1 is connected via the dispersion head 186.
85 is sufficiently purged with nitrogen gas. The constant temperature bath 183 containing the triethoxysilane solution 184
It is kept in. At this time, the vapor pressure of triethoxysilane is 3300 Pa (400 Pa in the case of TEOS). In order to avoid a reaction with the triethoxysilane solution 184, it is necessary that the water and oxygen gas in the thermostat 183 be sufficiently purged and the nitrogen gas be sufficiently dehydrated and deoxygenated. Flow controller 181b
Is opened, the flow controller 181a and the flow controller 181b are opened. Flow controller 1
Each of 81a, 181b and 181c has a flow rate of 7.5S.
LM (abbreviation of Std. Liter per Min.)
, A nitrogen gas (carrier gas) at a flow rate of 17.0 SLM, and a nitrogen gas (bubbling gas) at a flow rate of 1.0 SLM. About 5 vol% of the oxygen gas flowing through the flow rate controller 181 a is converted into ozone gas by the ozone generator 182. The ethoxysilane solution 184 is bubbled by the nitrogen gas flowing through the flow rate controller 181c to obtain a triethoxysilane gas. The ozone gas and the triethoxysilane gas are supplied to the reaction chamber 185
And mixed for the first time near the semiconductor substrate 189 (p
ost-mix method) (FIG. 3). Note that this CV
The D apparatus is a face down type APCVD apparatus, but may be a face top type. Although a nitrogen gas is used as the carrier gas and the bubbling gas, a helium gas or an argon gas may be used. Also, LPC
A VD device may be used.

As described above, since the upper surface of the silicon oxide film 132 has a portion which cannot be said to be smooth, if an upper layer wiring is formed on the silicon oxide film 132 in this state, the upper layer wiring is disconnected and short-circuited. Is more likely to occur. Therefore, it is preferable that the upper surface of the silicon oxide film 132 be flattened. Silicon oxide film 132
Is formed, the silicon oxide film 13 is formed by a spin coating method or the like.
An organic SOG film 139a is formed to cover the entire upper surface of the substrate 2 (FIG. 1C).

Subsequently, the SOG film 139a is completely removed.
Until reactive ion etching (RIE)
The OG film 139a and the silicon oxide film 132 are
Oxidized silicon oxide film 132a having a flat top surface.
Is formed. The minimum thickness of the silicon oxide film 132a is
It is about 0.2 μm. The conditions for this RIE are as follows:
It has become. Etching gas flow rate is about 100sccm
Degree of carbon tetrafluoride (CF_Four ) Gas and flow rate about 15sccm
At a pressure of 13 Pa and a power density of 0.
3W / cm^TwoIt is. Next, the same as the first PECVD
Silicon oxide by the second PECVD under similar conditions
A film made of a plasma TEOS oxide film on the surface of the film 132a
A third silicon oxide film 133 having a thickness of about 0.2 μm is formed.
I do. As a result, the silicon oxide film 131 and the silicon oxide
Between the insulating film 132a and the silicon oxide film 133
The formation of the insulating film is completed. This interlayer insulating film is
The silicon oxide film 132a having a force has a compressive stress
Since it is sandwiched between the silicon oxide films 131 and 133,
The force is reduced [FIG. 2 (a)].

The organic SOG film 139a and R under the above conditions
There are the following two reasons why the flattening is performed using the IE. To obtain a thick SOG film, an organic SOG film is easier. In this RIE, the SOG film 139a
Is almost equal to the etching rate of the silicon oxide film 132. In contrast, inorganic SO
When etching back by RIE using a G film, there is a difference in the etching rate between the SOG film and the silicon oxide film 132, and it is not easy to flatten the upper surface of the silicon oxide film 132. Even when the SOG film 139a or the inorganic SOG film is used for planarization by a chemical mechanical polishing method, the SOG film and the silicon oxide film 1 are used.
The difference between the etching rate and the etching rate is large.

Next, using the photoresist film (not shown) as a mask, the silicon oxide film 133, the silicon oxide film 1
32a and the silicon oxide film 131 are sequentially etched to form a plurality of through holes 1 reaching the lower wiring 125A and the like.
41a is formed. The size of the through hole 141a is
It is about 0.5 μm □. This etching is, for example, anisotropic plasma etching using a trifluoromethane (CHF ₃ ) gas and an oxygen gas as an etching gas at a pressure of 10 Pa and a power of 1200 W. In this etching, since the etching rate of the titanium nitride film 124a is also high, the aluminum-copper-silicon alloy film 123a is exposed on the bottom surface of the through hole 141a (FIG. 2B).

Next, a titanium film 151a having a thickness of about 0.01 μm and a titanium nitride film 152a having a thickness of about 0.05 μm are formed on the entire surface by sputtering and reactive sputtering. Subsequently, tungsten hexafluoride (WF ₆ ) at a substrate temperature of 400 ° C. and a pressure of 5000 Pa
By blanket CVD using gas and hydrogen gas,
A tungsten film 153a having a thickness of about 0.2 μm is formed. Next, the tungsten film 153a is etched by plasma etching using sulfur hexafluoride (SF ₆ ) gas as an etching gas, argon gas as a carrier gas, a pressure of 30 Pa and a power of 400 W until the upper surface of the silicon oxide film 133 is exposed.
Etch back etc. Thereby, the through hole 14
The tungsten film 153 has a state of filling the inside of the tungsten film 153.
a, the titanium nitride film 152a and the titanium film 151a are left. Subsequently, a titanium film 16 having a thickness of about 0.06 μm is formed by sputtering or reactive sputtering.
1a, a titanium nitride film 162a having a thickness of about 0.1 μm, and an aluminum-copper-silicon alloy film 163 having a thickness of about 0.6 μm
a and a titanium nitride film 164a having a thickness of about 0.05 μm
Are sequentially deposited. These four-layered metal films are patterned to form a plurality of upper-layer wirings such as an upper-layer wiring 165a, thereby completing the manufacture of the semiconductor device according to the present reference example [FIG.
(C)].

The above reference example is excellent in step coverage with respect to the lower wiring as in the case of the interlayer insulating film described in JP-A-3-29345 in which a plasma TEOS oxide film and an ozone TEOS oxide film are alternately laminated. The generation of cracks is suppressed, and the filling of narrow voids is excellent.

Further, according to the present embodiment , the water content in the interlayer insulating film is reduced to about 60% as compared with the method of forming the interlayer insulating film described in the above-mentioned publication. The relative dielectric constant of the second silicon oxide film in the present reference example is ozone TEOS.
Lower than the relative dielectric constant of the oxide film. As a result, an increase in the contact resistance, an increase in the stray capacitance, and a change in the threshold voltage of the MOS transistor in the semiconductor device including the MOS transistor due to the high-temperature bias test are suppressed as compared with the semiconductor device described in the above-mentioned publication.

For example, a semiconductor device in which upper wirings and lower wirings are alternately connected in series using 50,000 through holes of 0.5 μm square is formed by the method described in the present reference example and the above-mentioned publication, and Comparing the contact resistances obtained from the above semiconductor devices, the following results are obtained. Ginseng
If by Reference Example is about 0.75Omu / number, if by the Publication described about 1.25Omu / Pieces. Also,
In the semiconductor device including the N-channel MOS transistor, and the participants as an interlayer insulating film according to the above publication, wherein
Variation in the threshold voltage (V _T) due to high temperature bias test (BT) and by Reference Example comparisons ([Delta] V _T) was performed. The dimensions of these MOS transistors are
The thickness of the gate oxide film is 15 nm, and the gate length (L) is 0.
5 μm, the gate width (W) is 100 μm or the like. In these semiconductor devices, the MOS transistor is covered with a base insulating film made of a BPSG film, the upper wiring is covered with a surface protective film, and is sealed with a resin. The conditions for the BT test are an applied voltage of 5 V and a storage temperature of 150 ° C. BT
Focusing on the fluctuations in the above, the results of the 1000 hour test are as follows. It is due to the publication, wherein the -7% ΔV _T / V _T, but due to the present reference example is -5% ΔV _T / V _T.

Further, as is clear from the fact that the second silicon oxide film of the above reference example has a lower water content and lower relative dielectric constant than the ozone TEOS oxide film, the resistivity (ρ 1 × 10 ¹⁶ Ω · cm) ozone TEOS
The resistivity of the oxide film (ρ 0.9 × 10 ¹⁶ Ω · cm) is higher, and the semiconductor device employing this reference example has a higher gap between the upper layer wiring and the lower layer wiring than the semiconductor device described in the above publication. The insulation properties of the metal are increased.

In the above reference example , the main material of the lower wiring and the like is aluminum, but copper or gold may be the main material. The triethoxysilane gas, which is a part of the source gas for forming the second silicon oxide film, was obtained by bubbling a triethoxysilane solution in a thermostat kept at 40 ° C. The temperature is not limited to the above, and may be any temperature within a range of 0 to 45 ° C. Furthermore, in place of the triethoxysilane gas, trimethoxysilane (HSi (OCH _{3) 3)} gas, tri-n-propoxy silane _{(HSi (n-OC 3 H} 7) 3) gas or tri-n-butoxy silane (HSi (n- O
C ₄ H ₉ ) ₃ ) gas can be used as a part of the source gas. The silicon oxide film obtained with these gases has the same effect as the above reference example . When these are used, the temperature range of the thermostat for gasifying each solution is different from that of triethoxysilane. Preferred thermostatic bath temperatures for the trimethoxysilane solution, the trinormalpropoxysilane solution and the trinormalbutoxysilane solution are in the ranges of 0 to 10 ° C, 35 to 80 ° C, and 80 to 120 ° C, respectively.

Furthermore, in the above reference example , the first and third silicon oxide films were plasma TEOS oxide films, but trimethoxysilane, triethoxysilane, trinormal propoxysilane or trinormal butoxysilane was vaporized. PECV using gas and oxygen gas
D may be a silicon oxide film. These silicon oxide films also have a compressive stress on the silicon substrate. 2
According to secondary ion mass spectrometry (SIMS), plasma T
Although the carbon in the EOS oxide film is of the order of 10 ²¹ / cm ³ ,
For example, the number of carbon atoms in a silicon oxide film formed by PECVD using triethoxysilane gas is on the order of 10 ²⁰ atoms / cm ³ . As a result, as compared with the plasma TEOS oxide film, the silicon oxide film formed by PECVD using the trialkoxysilane gas has an increased resistivity and a reduced trap order density. For this reason, in the present reference example , the first and third samples are formed by PECVD using these trialkoxysilane gases.
When the silicon oxide film is formed, the insulation characteristics between the upper layer wiring and the lower layer wiring are improved, and the effect of the parasitic MOS transistor is reduced.

FIG. 3 is a schematic cross-sectional view of a manufacturing process of a semiconductor device.
Referring to FIG. 4 and FIG.First embodiment
Indicates the shape of the lower insulating film and the first, second and third oxide films.
And a method of forming a recon film.Reference example aboveDifferent from
I have.

First, a lower insulating film 112 is formed on the surface of the silicon substrate 101 in the same manner as in the above-described reference example .
The thickness of the lower insulating film 112 is about 0.8 μm (of the BPSG film) thicker than the thickness of the lower insulating film 111 of the reference example . An organic SOG film 119 that completely covers the surface of the base insulating film 112 is formed by a spin coating method or the like (FIG. 4A).

Next, by the same RIE as in the above reference example ,
Etchback is performed until the SOG film 119 is completely removed, and an interlayer insulating film 112b having a flattened upper surface and a thickness of about 0.6 μm is formed. Subsequently, similarly to the above reference example , a titanium film 121b having a thickness of about 0.06 μm, a titanium nitride film 122b having a thickness of about 0.1 μm, and a thickness of 0.6 μm.
m, an aluminum-copper-silicon alloy film 123b of about m and a titanium nitride film 124b of about 0.05 μm in thickness are sequentially deposited, and the four-layered metal film is patterned to form lower wiring 126A, lower wiring 126B, lower wiring. 126C and the lower wiring 126D are formed (FIG. 4B).

Next, the first PECVD using silane (SH ₄ ) gas and nitrous oxide (N ₂ O) gas is performed to form a film on the upper surface of the lower wiring 126A and the like and on the exposed surface of the lower insulating film 112b. A first silicon oxide film 134 having a thickness of about 0.2 μm is formed. The silicon oxide film 134 has a compressive stress on the order of 10 ⁸ Pa with respect to the silicon substrate 101. The thickness of the silicon oxide film 134 on the side surface of the lower wiring 126A and the like is at most about 1.0 μm. As described above , the step coverage in the narrow sense of the silicon oxide film 134 is somewhat inferior to the silicon oxide film 131 of the above-described reference example , but the silicon oxide film 134 is carbon-free.

Thereafter, using the APCVD apparatus shown in FIG. 3, the thermostat 183 was maintained at a temperature of 30 ° C.
A hydrogenated silsesquioxane solution having a molecular formula of (HSiO _3/2 ) ₈ is put in the 83 in place of the triethoxysilane solution 184, the substrate temperature is set to 400 ° C., and the hydrogenated silsesquioxane gas and the ozone gas Heat CV using
D is used to form a second silicon oxide film 135. The average film thickness of the silicon oxide film 135 is about 1.2 μm. The smoothness of the upper surface of the film and the step coverage of the film in a broad sense (including the filling of narrow gaps) are the same as those of the above reference example . One silicon oxide film 131 is substantially the same. The step between the highest position and the lowest position on the upper surface of the silicon oxide film 135 is about 0.8 μm (equal to the thickness of the lower wiring). The silicon oxide film 135 can be formed up to a thickness of about 2.5 μm without generating cracks. Subsequently, an organic SOG film 139 that completely covers the surface of the silicon oxide film 135 is formed in the same manner as in the above-described reference example.
b is formed (FIG. 4C).

Next, similarly to the above-described reference example , the SOG film 139b is completely removed by etch-back using RIE, and the silicon oxide film 13 having a planarized upper surface is removed.
5b is formed. The minimum thickness of the silicon oxide film 135b is about 0.2 μm. Subsequently, a second PECVD similar to that used for forming the silicon oxide film 134 is performed.
As a result, the third silicon oxide film 1 having a thickness of about 0.2 μm
36 is formed. Thus, the formation of the interlayer insulating film according to the present embodiment is completed. Further, a plurality of through-holes 141b reaching the lower layer wiring 126A and the like are formed by the same method as in the above-described reference example (FIG. 5A).

Next, a titanium film 151b having a thickness of about 0.01 μm, a titanium nitride film 152b having a thickness of about 0.05 μm, and a tungsten film 153b having a thickness of about 0.2 μm are formed on the entire surface in the same manner as in the above-described reference example. And a tungsten film 153b and a titanium nitride film 15 having a form of filling the through holes 141b by etch back.
2b and the titanium film 151b are left. In addition the participants
The titanium film 161b having a thickness of about 0.06 μm and the titanium nitride film 16 having a thickness of about 0.1 μm are formed in the same manner as in the example.
2b, an aluminum-copper-silicon alloy film 163b having a thickness of about 0.6 μm and a titanium nitride film 164b having a thickness of about 0.05 μm are sequentially deposited, and the four-layered metal film is patterned to form an upper wiring 165b and the like. Are formed, and the manufacture of the semiconductor device according to the present embodiment is completed (FIG. 5B).

This embodiment has the effects of the above-mentioned reference example . Further, the water content, water adsorbability, relative dielectric constant, resistivity, and the like of the second silicon oxide film of this embodiment are the same as those described above.
It is more preferable than those of the second silicon oxide film of the example. Therefore, the contact resistance increases, the stray capacitance increases, and the M
The present embodiment is more effective than the above-mentioned reference example in terms of fluctuation of the threshold voltage of the OS transistor due to the high-temperature bias test. Taking the contact resistance as an example, the adoption of this embodiment results in about 0.5 Ω / piece for a 0.5 μm square through hole. 5V, 1000 hours BT
Is ΔV _T / V _T -2%.

Further, the first (and third) silicon oxide film of this embodiment is free of carbon, and the second silicon oxide film of this embodiment has low water content and low water adsorbability. Thus, the improvement of the insulation characteristics between the upper layer wiring and the lower layer wiring and the reduction of the parasitic MOS transistor effect are more effective than the above reference example . Furthermore, in the present embodiment is a flat upper surface of the underlying insulating film, the reference
Processing accuracy of the lower wiring is improved as compared with the example , and miniaturization of the lower wiring is facilitated.

[0046] Note that the main material of the lower layer wiring and the like even on SL first embodiment was aluminum, copper or gold may be the main material. Further, a hydrogenated silsesquioxane gas used as a part of a source gas for forming the second silicon oxide film is formed by bubbling a hydrogenated silsesquioxane solution having a molecular formula of (HSiO _3/2 ) _8. The molecular formulas were (HSiO _3/2 ) ₁₀ , (HSiO _3/2 ) ₁₂ , (H
SiO _3/2 ) ₁₄ , (HSiO _3/2 ) ₁₆ , (HSiO
A hydrogenated silsesquioxane gas obtained by bubbling a hydrogenated silsesquioxane solution comprising _3/2 ) ₁₈ or (HSiO _3/2 ) ₂₀ can also be used.

Further, in the first embodiment , the first
And the third silicon oxide film was formed by PECVD using silane gas and nitrous oxide gas. However, hydrogenated silsesquioxane (here, (HSiO
_3/2 ) _2m ) m is an integer in the range of 4 to 10) A silicon oxide film by PECVD using a gas obtained by bubbling a solution with an inert gas and an oxygen gas as a source gas may be used.
The narrow step coverage of this silicon oxide film is plasma TE
This is about the same as the OS oxide film, and this silicon oxide film has a compressive stress of the order of 10 ⁸ Pa against the silicon substrate.
According to the SIMS measurement, the carbon in the silicon oxide film formed by PECVD has a value less than the SIMS measurement limit (about 10 ¹⁶ / cm ³ ). That is, this silicon oxide film can also be regarded as carbon-free.

FIG. 5 is a schematic cross-sectional view of a semiconductor device manufacturing process.
Referring to FIG. 6 and FIG.Second embodiment
Represents N having a salicide structure source / drain region.
Manufacturing of semiconductor device including channel MOS transistor
It is about the method and it is as follows.

First, a LOCOS type field oxide film 211 having a thickness of about 0.6 μm is formed in an element isolation region on the surface of a P-type silicon substrate 201. P-type silicon substrate 2
A gate oxide film 212 having a thickness of about 15 nm is formed in the element formation region on the surface of the substrate 01. Further, the gate electrode 221
A, the gate electrode 221B, such as the gate electrode 221C and the gate electrode 221D are formed, N ⁺ -type diffusion layer 202
A, N ⁺ type diffusion layer 202B and N ⁺ type diffusion layer 202C
Are formed. The gate electrodes 221A and the like have a thickness of about 0.3 μm, and the side surfaces of the gate electrodes 221A and the like are covered with an insulating film spacer (not shown) having a thickness of about 0.1 μm. These gate electrodes 221A and the like are made of an N ⁺ -type polycrystalline silicon film, a high melting point metal film, a high melting point metal silicide film, or a high melting point metal polycide film. When forming the insulating film spacer, the N ⁺ type diffusion layer 2
The gate oxide film 212 on the surface such as 02B is removed. Deposition of titanium film on the entire surface by sputtering, at most 60
By heat treatment of about 0 ° C and removal of unreacted titanium film,
At least N ⁺ type diffusion layer 202A, N ⁺ type diffusion layer 202
The surface of the B and N ⁺ type diffusion layers 202C and the like have a thickness of 0.1
A titanium silicide film 204 of about μm is formed. Thus, an N-channel MOS transistor having a source / drain region having a salicide structure is completed [FIG.
(A)]. At this stage N ⁺ -type diffusion layer 202A and the like of the P-
The depth of the N junction is about 0.1 μm.

Next, in the same manner as in the first embodiment , a first P using silane gas and nitrous oxide gas is used.
By ECVD, a film thickness of 0.2 (at a flat base portion)
A first silicon oxide film 234 having a thickness of about μm is formed. Subsequently, AP using hydrogenated silsesquioxane gas (having a molecular formula of (HSiO _3/2 ) ₈ ) and ozone gas
The second film having an average film thickness of 1.0 μm is formed by CVD (thermal CVD).
Of silicon oxide film 235 is formed. Further, an organic SOG film 239 that completely covers the surface of the silicon oxide film 235
Is formed (FIG. 6B).

Next, as in the above-described reference example , the SOG film 239 is completely removed by etch-back using RIE, and the silicon oxide film 235 having a flattened upper surface is formed.
a is formed. The minimum thickness of the silicon oxide film 235a is about 0.2 μm. Subsequently, a third silicon oxide film 236 having a thickness of about 0.2 μm is formed by second PECVD similar to that used for forming the silicon oxide film 234.
To form Thus, the formation of the interlayer insulating film according to the present embodiment is completed. Further, the titanium silicide film 2 forming the source / drain region is formed in the same manner as in the above reference example.
A plurality of contact holes 241 reaching the gate electrode 221D and the like are formed [FIG. 6 (c)].

Next, a titanium film 251a having a thickness of about 0.01 μm, a titanium nitride film 252a having a thickness of about 0.05 μm, and a tungsten film 253a having a thickness of about 0.2 μm are formed on the entire surface by the same method as in the above-mentioned reference example. Is formed, and the tungsten film 253a, the titanium nitride film 252a, and the titanium film 251a having a form of filling the contact holes 241 and 242 by etch back are left. Further, by the same method as in the above reference example , a film thickness of 0.06 μm
, A titanium nitride film 262a having a thickness of about 0.1 μm, an aluminum-copper-silicon alloy film 263a having a thickness of about 0.6 μm, and a titanium nitride film 264a having a thickness of about 0.05 μm are sequentially deposited. These four-layered metal films are patterned to form upper layer wirings 265A and 265B.
Are formed, and the manufacture of the semiconductor device according to the present embodiment is completed [FIG. 7].

The effects that directly depend on the film quality of the interlayer insulating film, such as step coverage, filling, surface flatness, and suppression of void generation, suppression of increase in contact resistance and stray capacitance, and upper and lower wiring (Gate electrode and source / drain regions)
The second embodiment has the same effect as the first embodiment .

The second embodiment has a specific effect on the fluctuation of the threshold value of the MOS transistor.
Although the interlayer insulating film in the above reference example and the first embodiment is provided at a position separated from the semiconductor element, the interlayer insulating film of the present embodiment is used for an N-channel MOS transistor having a source / drain region having a salicide structure. The transistor is provided at an adjacent position, and the characteristics of the interlayer insulating film directly affect the transistor characteristics. Since an BPSG film cannot be used as an interlayer insulating film that covers this transistor (directly), an interlayer insulating film including an ozone TEOS oxide film has to be formed in the related art. As a result, the fluctuation of the threshold value due to BT or the like was extremely large. Comparing the transistor dimensions and BT conditions with the same reference example and the first embodiment , the absolute value of ΔV _T / V _T is 2 in the conventional semiconductor device.
There was a large variation in the range of about 10% to 60% centering on about 0%. On the other hand, if this embodiment is adopted, the absolute value of ΔV _T / V _T is about 2% to 4%.

Incidentally, also in the second embodiment described above,
As in the first embodiment , the main material of the upper wiring may be copper or gold. A hydrogen silsesquioxane hydride gas used as a part of a source gas for forming the second silicon oxide film may be a compound having a molecular formula of (HSiO _3/2 ) ₁₀ or (HSiO
_3/2 ) ₁₂ , (HSiO _3/2 ) ₁₄ , (HSiO _3/2 ) ₁₆ ,
A hydrogenated silsesquioxane gas obtained by bubbling a hydrogenated silsesquioxane solution composed of (HSiO _3/2 ) ₁₈ or (HSiO _3/2 ) ₂₀ can also be used. Furthermore, the first and third silicon oxide films are formed by bubbling a solution of hydrogenated silsesquioxane (here, _{m of} (HSiO _3/2 ) _2m is an integer of 4 to 10) with an inert gas. P using hydrogen and oxygen gas as source gas
A silicon oxide film formed by ECVD may be used.

Referring to FIG. 8, which is a schematic cross-sectional view of a manufacturing process of a semiconductor device, the third embodiment of the present invention differs from the second embodiment in the shape of the field oxide film and the method of forming the same. And it looks like this:

First, a first LOCOS type film having a thickness of about 0.3 μm is formed in the element isolation region on the surface of the P-type silicon substrate 201.
After the first field oxide film is removed, an (improved) LOCOS type field oxide film 213 having a thickness of about 0.6 μm is formed again at the same place. I do. Subsequently, a gate oxide film 214 having a thickness of about 15 nm is formed in the element formation region on the surface of the P-type silicon substrate 201. Field oxide film 213
And the upper surface of the gate oxide film 214 substantially coincide with each other to form one substantially flat plane.

Further, the gate electrode 222A, the gate electrode 222B, the gate electrode 222C and the gate electrode 222
D ⁺ and the like, and the N ⁺ type diffusion layer 203A, the N ⁺ type diffusion layer 2
03B and an N ⁺ type diffusion layer 203C are formed. The appearance of the gate electrode 222A and the like such as the film thickness is determined by the second embodiment.
This is the same as the gate electrode of the embodiment. Side surfaces of the gate electrode 222A and the like are covered with an insulating film spacer (not shown) having a thickness of about 0.1 μm. Subsequently, a titanium silicide film 204 is formed on at least the surfaces of the N ⁺ -type diffusion layers 203A, the N ⁺ -type diffusion layers 203B, the N ⁺ -type diffusion layers 203C, and the like. Next, a first silicon oxide film 234 and a second silicon oxide film 235 having a thickness of about 0.7 μm are formed in the same manner as in the first embodiment (FIG. 8).
(A)].

Next, the silicon oxide film 235 is processed into a silicon oxide film 235b having a flat upper surface by the same method as in the above-described reference example . After that, a third silicon oxide film 236 is formed using the second PECVD by the same method as in the first embodiment, and the formation of the interlayer insulating film according to the present embodiment is completed. Subsequently, similarly to the second embodiment , the titanium silicide film 2 forming the source / drain region is formed.
A plurality of contact holes 243 reaching the gate electrode 222D and the like are formed [FIG. 8 (b)].

Next, a titanium film 251b, a titanium nitride film 252b, and a tungsten film 253b are formed on the entire surface by the same method as that of the above-described reference example , and the tungsten having the appearance of filling the contact holes 241 and 242 by etch back is formed. The film 253b, the titanium nitride film 252b, and the titanium film 251b are left. Further, the titanium film 261b and the titanium nitride film 26 are formed in the same manner as in the above reference example.
2b, an aluminum-copper-silicon alloy film 263b and a titanium nitride film 264b are sequentially deposited, and the four-layered metal film is patterned to form a plurality of upper wirings such as upper wirings 266A and 266B. (FIG. 8 (c)).

The third embodiment has the same effects as the second embodiment . Further, in this embodiment, since the top surfaces and the gate oxide film of the field oxide film forms a generally consistent with generally flat one plane, the second embodiment
Compared to the example , the processing accuracy of the gate electrode is improved and the miniaturization of the gate electrode is facilitated, and the difference in aspect ratio between the contact hole reaching the gate electrode and the contact hole reaching the source / drain region is reduced. The processing accuracy of the holes and the filling of the conductive film into these holes are facilitated.

In the third embodiment , an improved LOCOS type field oxide film is employed in order that the upper surface of the field oxide film and the upper surface of the gate oxide film are substantially coincident with each other to form one substantially flat plane. However, a trench isolation type field insulating film may be used instead, or a trench isolation type field insulating film and an improved LOCOS type field oxide film may be used in combination.

[0063]

As described above, according to the semiconductor device manufacturing method of the present invention, the first silicon oxide film formed by the first PECVD, the second silicon oxide film formed by the thermal CVD, and the third silicon oxide film formed by the second PECVD. in forming an interlayer insulating film of a silicon oxide film, hydrogenated Shirusesukioki
A second silicon oxide film is formed by thermal CVD using a gas obtained by bubbling a sun solution with an inert gas and an ozone gas. This second silicon oxide film is made of ozone T
Since the water content is lower than that of the EOS oxide film, cracks are suppressed due to excellent step coverage of the lower wiring, including the case where the source / drain regions of the salicide structure are used as the lower wiring. The rise in stray capacitance between the wiring and the lower wiring is reduced,
In a semiconductor device including an S transistor, it becomes easy to suppress a change in threshold voltage of a MOS transistor.

[Brief description of the drawings]

FIG. 1 is a reference of a method of manufacturing a semiconductor device according to the present invention.
It is a cross-sectional schematic diagram of the manufacturing process of an example .

FIG. 2 is a schematic cross-sectional view of a manufacturing process of the reference example .

FIG. 3 is a schematic diagram of a chemical vapor deposition apparatus used in the reference example .

FIG. 4 is a schematic sectional view of a manufacturing process according to the first embodiment of the present invention.

FIG. 5 is a schematic sectional view of a manufacturing process of the first embodiment .

FIG. 6 is a schematic sectional view of a manufacturing process according to a second embodiment of the present invention.

FIG. 7 is a schematic sectional view of a manufacturing process of the second embodiment .

FIG. 8 is a schematic sectional view of a manufacturing process according to a third embodiment of the present invention.

FIG. 9 is a schematic cross-sectional view for explaining a conventional method for manufacturing a semiconductor device.

[Explanation of symbols]

101 silicon substrate 111, 112, 112b, 311 base insulating film 119, 139a, 139b, 239 SOG film 121a, 121b, 151a, 151b, 161a,
161b, 251a, 251b, 261a, 261b
The titanium films 122a, 122b, 124a, 124b, 152a,
152b, 162a, 162b, 164a, 164b,
252a, 252b, 262a, 262b, 264a,
264b titanium nitride films 123a, 123b, 163a, 163b, 263a,
263b Aluminum-copper-silicon alloy film 125A-125D, 126A-126D, 321
Lower layer wiring 131, 132, 132a, 133, 134, 135,
135b, 136, 234, 235, 235a, 235
b, 236, 331, 332, 333 Silicon oxide films 141a, 141b Through holes 153a, 153b, 253a, 253b Tungsten films 165a, 165b, 265A, 265B, 266A,
266B, 361 Upper wiring 181a-181c Flow controller 182 Ozone generator 183 Constant temperature bath 184 Triethoxysilane solution 185 Reaction chamber 186 Dispersion head 187 Susceptor 188 Heater 189 Semiconductor base 201 P-type silicon substrate 202A-202C, 203A-203C N ⁺ Diffusion layer 204 Titanium silicide film 211, 213 Field oxide film 212, 214 Gate oxide film 221A-221D, 222A-222D Gate electrode 241, 242, 243, 244 Contact hole 301 Semiconductor substrate

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H01L 21/31 H01L 21/312-21/3205 H01L 21/3213 H01L 21/768

Claims (10)

(57) [Claims] A step of forming a lower insulating film having a smooth upper surface covering a surface of a silicon substrate on which a predetermined semiconductor element is provided; and a step of forming a plurality of lower wirings on the surface of the lower insulating film. , the first plasma enhanced chemical vapor deposition, and forming a first silicon oxide film covering the exposed surface of the exposed surface and the lower insulating film of the lower layer wiring directly, m is 4 to 10 The surface of the first silicon oxide film is directly formed by a thermochemical vapor deposition method using an ozone gas and a gas obtained by bubbling a hydrogenated silsesquioxane ((HSiO _3/2 ) _2m ) solution of an integer with an inert gas. Forming an organic SOG film on the second silicon oxide film and performing etch-back by reactive ion etching to form a second silicon oxide film on the second silicon oxide film; A step of planarizing the upper surface of the silicon film, and a step of forming a third silicon oxide film directly covering the planarized upper surface of the second silicon oxide film by a second plasma-enhanced chemical vapor deposition method Forming a plurality of through holes reaching predetermined positions of the lower wiring by sequentially etching the third, second, and first silicon oxide films using a photoresist film as a mask; Forming a plurality of upper wirings on the surface of the silicon oxide film. 2. The method according to claim 1, wherein the lower insulating film has a flattened upper surface. 3. The method of claim 1, wherein the first plasma-enhanced chemical vapor deposition method comprises a step of bubbling a silane gas, a nitrous oxide gas, and a solution of tetraethoxysilane (Si (OC ₂ H ₅ ) ₄ ) with an inert gas and an oxygen gas. A gas obtained by bubbling a trialkoxysilane solution with an inert gas and an oxygen gas, or m is an integer of 4 or more and 10 or less.
That hydrogenated silsesquioxane that is ((HSiO _{3/2) 2m)} solution of either a mixed gas of the bubbled gas and oxygen gas with an inert gas and raw material gas plasma enhanced chemical vapor deposition 3. The method for manufacturing a semiconductor device according to claim 1, wherein 4. The second plasma-excited chemical vapor deposition method comprises the steps of: bubbling a silane gas, a nitrous oxide gas, a tetraethoxysilane solution with an inert gas, an oxygen gas, and a trialkoxysilane solution with an inert gas. Bubbling gas and oxygen gas or m
Plasma-excited chemical gas using a mixed gas of a gas obtained by bubbling a hydrogenated silsesquioxane ((HSiO _3/2 ) _2m ) solution consisting of an integer of 4 or more and 10 or less with an inert gas or an oxygen gas as a source gas. 4. The method for manufacturing a semiconductor device according to claim 1, wherein the method is a phase growth method. 5. The first or second plasma excitation
The trialkoxysilane (HS) used for chemical vapor deposition
i (OR) ₃ ) is trimethoxysilane (HSi (OC
H ₃ ) ₃ ), triethoxysilane (HSi (OC ₂ H
₅ ) ₃ ), trinormal propoxysilane (HSi (n
5. The method for manufacturing a semiconductor device according to claim 3 , wherein the semiconductor device is any one of —OC ₃ H ₇ ) ₃ ) and trinormal butoxysilane (HSi (n-OC ₄ H ₉ ) ₃ ). 6. 6. A lower insulating film having a smooth surface composed of a field insulating film and a gate insulating film is formed on a surface of a silicon substrate of one conductivity type, and a plurality of gate electrodes are formed on the surface of the lower insulating film. Forming a plurality of diffusion layers having a salicide structure of a reverse conductivity type on a surface of the silicon substrate; and covering the lower insulating film including the gate electrode and the diffusion layer by a first plasma-enhanced chemical vapor deposition method Forming a first silicon oxide film, and using an ozone gas and a gas obtained by bubbling a hydrogenated silsesquioxane ((HSiO _3/2 ) _2m ) solution in which m is an integer from 4 to 10 with an inert gas. Forming a second silicon oxide film directly covering the surface of the first silicon oxide film by a thermal chemical vapor deposition method, and forming an organic SOG film on the second silicon oxide film Performing a step of etching back by reactive ion etching to planarize the upper surface of the second silicon oxide film; and a step of planarizing the second silicon oxide film by a second plasma-excited chemical vapor deposition method. Forming a third silicon oxide film directly covering the upper surface of the film; and sequentially etching the third, second and first silicon oxide films using a photoresist film as a mask, thereby forming the gate electrode. Forming a plurality of contact holes respectively reaching a predetermined position and a predetermined position of the diffusion layer; and forming a plurality of upper wirings on a surface of the third silicon oxide film. A method for manufacturing a semiconductor device. 7. The method according to claim 6 , wherein the lower insulating film has a substantially planarized upper surface. 8. The first plasma-enhanced chemical vapor deposition method using a silane gas and a nitrous oxide gas as a source gas, or m is 4 or more and 10 or more.
Hydrogenated silsesquioxane of integers below ((HSi
O _{3/2) 2m)} solution according to claim 6 or claim 7 wherein is any one of a plasma enhanced chemical vapor deposition method for the bubbling gas and oxygen gas as raw material gases with an inert gas A method for manufacturing a semiconductor device. 9. The plasma-enhanced chemical vapor deposition method using a silane gas and a nitrous oxide gas as source gases, a gas obtained by bubbling a tetraethoxysilane solution with an inert gas, A plasma-excited chemical vapor deposition method using oxygen gas as a source gas, a plasma-excited chemical vapor deposition method using a gas obtained by bubbling a trialkoxysilane solution with an inert gas and an oxygen gas as a source gas, or m of 4 to 10 From an integer
Characterized in that that hydrogen silsesquioxane ((HSiO _{3/2) 2m)} solution is either a bubbling gas and oxygen gas with an inert gas plasma enhanced chemical vapor deposition method as a raw material gas 9. The method for manufacturing a semiconductor device according to claim 6 , 7 or 8 . 10. The second plasma-excited chemical vapor deposition.
The trialkoxysilane used in law (HSi (OR)
₃ ) is trimethoxysilane (HSi (OCH ₃ )
₃ ), triethoxysilane (HSi (OC ₂ H ₅ )
₃ ), trinormal propoxysilane (HSi (n-O
C ₃ H ₇ ) ₃ ) and trinormal butoxysilane (H
The method according to claim 9, wherein a is either _{Si (n-OC 4 H 9} ) 3).