JP2755600B2 - Image processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to processing of a CT (computer tomography) image used for medical or industrial use, an ultrasonic flaw detector or a microwave underground. The present invention relates to an image processing device used for processing a search radar image.

(Prior Art) Generally, in digital grayscale image processing, it is necessary to perform various geometric transformations (enlargement, reduction, rotation, translation, etc.) on an input image. FIG. 4 shows a block diagram of a typical processing device used at this time.

In FIG. 4, 11 is a system controller, 12 is an input interface, 13 ₁ and 13 ₂ are memories, 14 is a processor dedicated to signal processing, 15 is an output interface, 16 is a control bus, and 17 is a data bus. Input image Sin is captured via the input interface 12 to the memory 13 _1. Here, the geometric transformation is performed by the dedicated processor 14, and the memory
Image data in the 13 ₁ is transferred to the memory 13 ₂ is taken out as an output image Sout via the output interface 15.

Here, the dedicated processor 14 performs a calculation for determining each time an address of the input image Sin to be assigned to each image constituting the output image Sout.
An alternative is an affine transformation, which is a first-order geometric transformation. In general, a geometric transformation processor often requires only a primary geometric transformation function at most because of complicated calculations. On the other hand, for example, in synthetic aperture processing in an ultrasonic flaw detector or a microwave underground exploration radar, and in geometric transformation processing in an industrial X-ray CT apparatus, data is written to a memory as a radius of a circle as processing contents, Various processes such as adding while rotating are used.

For this reason, in the conventional image processing apparatus as described above, even if simple processing is considered in terms of circular coordinates, since ordinary memory only allows rectangular coordinates, this is considered as a combination of affine transformations or special geometric transformation. And the processing becomes complicated, and even if it can be realized, the processing speed is reduced.

(Problems to be Solved by the Invention) As described above, in a conventional image processing apparatus, even if a mathematically simple geometric transformation is realized by a combination of an existing memory and a dedicated processor, the processing becomes complicated. This causes a reduction in processing speed.

Therefore, the present invention has been made to eliminate the above-mentioned disadvantages, and relates to image data represented by a representative coordinate system.
An object of the present invention is to provide an image processing apparatus capable of simplifying and speeding up processing by eliminating the processing time of a dedicated processor such as affine transformation.

[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above object, an image processing apparatus according to the present invention comprises: a first memory and a second memory that hold image data in a rectangular coordinate system; After reading the image data from the first memory and performing a predetermined geometric transformation, the converted image data is written into the second memory, and a processor dedicated to signal processing is used. A memory control circuit that converts the image data into an arbitrary coordinate system by performing data conversion, wherein the memory control circuit corresponds to the first or second coordinate conversion mode set in advance. An address conversion unit having a function of converting an access address of the second memory; and the address conversion unit according to a coordinate conversion mode designated by the signal processing dedicated processor. Constructed and a mode selecting means for selecting control coordinate conversion mode.

(Operation) Since the image processing apparatus having the above configuration has a memory control circuit having a coordinate conversion function therein, the processor dedicated to signal processing is involved in address calculation and the like for image data that can be expressed by these conversions. This eliminates the need and reduces processing time.

Embodiment An embodiment of the present invention will be described below with reference to FIGS. 1 to 3.

FIG. 1 shows a configuration in which the present invention is applied to the image processing apparatus shown in FIG. In FIG. 1, the same parts as those in FIG. 4 are denoted by the same reference numerals, and description thereof will be omitted.

First, the memory 13 _1, each of memory control circuit against 13 ₂ 21 _1, 21 ₂ are provided, in accessing the memory 13 _1, 13 _2, via the必Razu memory control circuit 21 _1, 21 ₂ I do. Here, conversion of address data used at the time of access is performed. This transformation is bidirectional, rectangular coordinates (x, y)
And other arbitrary coordinates, for example, circular coordinates (r, o), oblique coordinates (l, m), parabolic coordinates (a, b), and so on.

FIG. 2 shows a block diagram of the memory control circuit 21 _1, image data is input from for example a data bus 17, address conversion circuit 36 ₁ via the data distribution circuit 35
~ 36 _n is input to any one of them. The data distribution circuit 35 receives the control of the mode setting circuit 34 and passes the data to the address conversion circuit having the conversion function of each coordinate system according to the conversion coordinate item given from the signal processing dedicated processor 14 via the control bus 16. (Of course, it is also possible to put together the common parts of the address conversion circuit).

The address conversion circuit is geometric transformation data by the conversion function independently with writes the converted data in the memory 13 _1. Data written in the memory 13 ₁ is read out by a command from the mode setting circuit 34, the address conversion circuit,
The data is sent to the data bus 17 via the data distribution circuit 35.

The configuration of the memory control circuit 21 ₁ is the same as 21 _1.

FIG. 3 shows a block diagram of the address conversion circuit. The normal rectangular coordinate address (x, y) sent from the data distribution circuit 35 is converted to an (x, y) address separating section 43.
Table lookup processor 45
Alternatively, it is passed to a higher-order polynomial processor 46. A table memory 44 is connected to the table look-up processor 45 or the higher-order polynomial processor 46, in which table data including addresses after conversion and coefficients of higher-order polynomials are set in advance.

The table lookup processor 45 reads the corresponding address information from the table memory 44 based on the address information from the (x, y) address separation unit 43. The high-order polynomial processor 46 reads the coefficients of the table memory 44 from the address information by the separating unit 43, creates a polynomial, and obtains a converted address. Each processor 4
The translated addresses obtained in steps 5 and 46 are combined by an address combining unit 47.

That is, in the above-mentioned address conversion circuit, generally, mathematical transformation formulas of a rectangular coordinate system and other coordinate systems can often be approximated by a higher-order polynomial, in which case only the higher-order polynomial processor 46 is used, but a special coordinate system is used. Uses a table look-up processor 45 for referring to a table to determine an address. However, even if both are made to function and the address is converted, it is no problem.

In FIG. 3, one address conversion circuit (36 _{1 to} 36 _n ) is used for each coordinate system conversion. However, the number of address conversion circuits may be reduced to one. Although no image data is involved in the address conversion in FIG. 3, a calculation function of image data can be added in consideration of a bilinear method or a cubic convolution method as a resampling method. Further, although the image processing apparatus can convert the coordinate system, this function can be used to collect data distributed on a memory and perform compression processing.

That is, in the image processing apparatus having the above configuration, a memory control circuit having a coordinate conversion function for accessing data on the memory in an arbitrary coordinate system is provided inside the image processing apparatus. For possible image data, the signal processing dedicated processor does not need to be involved in address calculation and the like. Therefore, according to this apparatus, the processing time can be reduced, and the user handles the digital image obtained in an arbitrary coordinate system without considering the geometric transformation when holding or performing various processes. be able to. Since this apparatus can perform high-speed processing, it is of course suitable for use in image processing for industrial, medical, and remote sensing.

[Effects of the Invention] As described above, according to the present invention, when a digital image obtained in an arbitrary coordinate system is held or various processes are performed, a user handles the digital image without considering each geometric transformation. Thus, it is possible to provide an image processing apparatus capable of high-speed processing suitable for use in industrial, medical, and remote sensing image processing.

[Brief description of the drawings]

FIG. 1 is a block circuit diagram showing an embodiment of an image processing apparatus according to the present invention, FIG. 2 is a block circuit diagram showing a configuration of a memory control device of the embodiment, and FIG. FIG. 4 is a block circuit diagram showing the configuration of the apparatus, and FIG. 4 is a block diagram showing an embodiment of a conventional ordinary image processing apparatus. 11 ... System controller, 12 ... Input interface, 1
3 ₁ , 13 ₂ … Memory, 14… Processor dedicated to signal processing, 15…
Output interface, 16 control bus, 17 data bus,
21 ₁ , 21 ₂ … Memory control circuit, 34… Mode control circuit, 35…
Data distribution circuit, 36 _{1 to} 36 _n ... address conversion circuit, 37 ... memory, 43 ... (x, y) address separation unit, 44 ... table memory, 45 ... table lookup processor, 46 ... high-order polynomial processor, 47 ... Address combining unit.

Claims (1)

(57) [Claims] A first memory for storing image data in a rectangular coordinate system; and an image data read from the first memory and subjected to a predetermined geometric transformation. A dedicated signal processing processor for writing to the second memory; and a memory control circuit for converting the image data into an arbitrary coordinate system by converting address data when accessing the first and second memories. An address conversion unit having a function of converting an access address of the first or second memory in accordance with a plurality of coordinate conversion modes set in advance;
An image processing apparatus comprising: a mode selection unit that selectively controls a coordinate conversion mode of the address conversion unit according to a coordinate conversion mode specified by the signal processing dedicated processor.