JP2744841B2 - Electronics - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic device, and more particularly to an electronic device having display means for performing dot matrix display.

[Prior art] Conventionally, electronic devices such as an electronic organizer, a word processor, and a personal computer using a liquid crystal or a plasma display for display have been known.
When there is no input of an operation instruction or the like for a certain period of time, there is known an automatic power-off control for turning off the power of the display unit or the entire electronic device to save power.

[Problems to be Solved by the Invention] However, in the electronic device as described above, when the user wants to think while looking at the screen without inputting for a certain period of time, or wants to occasionally see the information displayed on the screen, etc. The screen disappears after a certain time, which is very difficult to use.

Also, in the case of a type in which the power of the entire apparatus is automatically turned off, it is necessary to restart from turning on the power to operate the apparatus.

On the other hand, in the method in which only the screen display is stopped, such a problem does not occur, and the original display can be restored by performing a keyboard operation or the like.
There is a drawback in that a person other than the user cannot easily understand the usage status of the device and the on / off state of the power supply.

An object of the present invention is to solve the above problems and provide a configuration of an electronic device that can achieve both power saving, display visibility, and device operability by performing appropriate display control.

[Means for Solving the Problems] In order to solve the above problems, according to the present invention, in an electronic apparatus having a display means for performing dot matrix display, the electronic apparatus is used for actually driving the dot matrix of the display means. Means for variably controlling the number of rows or columns, and means for compressing image data, reducing the display area actually used for display driving of the display means in accordance with predetermined control conditions, and A configuration is adopted in which image data compressed by the compression means is displayed in a display area.

[Operation] According to the above configuration, the display area used for display driving can be reduced according to the desired control condition, and the compressed image data can be displayed in the reduced display area.

EXAMPLES Hereinafter, the present invention will be described in detail based on examples shown in the drawings.

FIG. 7 shows an outline view of a personal information device employing the present invention.

As shown, the personal information device of this embodiment is a numeric keypad,
There is no input unit such as a keyboard, and the input pen 30 is used to input character commands by hand on the input / output surface 31 that combines a transparent digitizer and a liquid crystal panel, and to display pen trajectories, character recognition results, and application results. is there.

FIG. 8 shows a block diagram of the entire control system of the apparatus shown in FIG.

The control system in Fig. 8 is a CP consisting of a microprocessor, etc.
U19 controls the operation of the entire apparatus. CPU
Each member as shown is connected to the 19 system bus. Hereinafter, each member will be described.

The ROM 20 stores control programs for the CPU 19 (application programs, OS, dictionary data, etc.)
1 is used as a work area of the CPU 19, a RAM disk area, and the like.

Reference numerals 22 to 24 denote interface circuits of an IC (memory) card as external storage means, a serial port such as RS232C, and a Centronics port (mainly a parallel port for a printer).

The input / output surface 31 in FIG. 7 is a combination of a transparent digitizer and a liquid crystal panel. The transparent digitizer and the liquid crystal panel are indicated by reference numerals 25 and 17, respectively.

The LCD panel 17 displays the LCD controller / driver
Controlled via 18. The display data is stored in the VRAM 10. The transparent digitizer 25 faces two sheets of glass (or one sheet of PET and one sheet of glass) on which resistive films are deposited, and plots the coordinates according to the voltage when the two resistive films contact each other by pressing a pen or the like. It is composed of a resistive digitizer to be converted.

Input and output to and from the transparent digitizer 25 are controlled via a digitizer driver for obtaining input coordinates by an input pen and an A / D converter 27 for converting a digitizer voltage into a digital value.

The power of the apparatus is supplied from a power supply unit 28 including a battery, a switching power supply, and the like.

Such information device applications (stored in ROM 20 or supplied using a medium such as an IC card) include world clocks, schedules,
Address book characters, calculations, drawing notes, etc. are possible.

FIG. 1 shows a configuration of a main part of the liquid crystal controller / driver 18 of FIG.

1 reads the display data from the VRAM 10,
The circuit transfers the control signal to the driver (FIG. 3) and generates a control signal. In this embodiment, in particular, in addition to the normal mode, the display range of the display unit is reduced in the reduction mode, and the control signal and data transfer are performed. A configuration for lowering the frequency is provided.

Here, the liquid crystal panel 17 is, for example, a 320 × 128 dot matrix liquid crystal, and its display data is stored in the VRAM 10.

In the figure, reference numeral 1 denotes a frequency divider / frequency selector constituted by a counter and a selector, which receives an input clock (for example, 667 KHZ) and a 1/4 frequency-divided clock (for example, 167 KHZ).
KHZ) is selected by the frequency select signal set in the register 2 and output as the column counter 3, the total counter 6, and the liquid crystal clock CP.

In the input clock reduction mode, a clock having a frequency 1/4 that of the normal mode is selected. The column counter 3 and the register 4 set the timing of the load signal LOAD. The load signal is generated once every 80 clocks (320 dots) in the normal mode and once every 40 clocks (160 dots) in the reduced mode. You.

The setting value of the register 4 is written by the CPU. The load timing control unit 5 adjusts the signal width from the count-up signal of the column counter 3 and outputs it as a load signal LOAD. The load signal LOAD is a signal for latching one line of data sent to the liquid crystal drainer (FIG. 3).

The frame signal FRAME and the address B for VRAM data access are generated by the total counter 6 and the register 7. The LCD screen is 32 in the normal mode of this embodiment.
Since it is 0x128 dots, once every 128 lines
Become a frame. The count of the register 7 is set by the CPU 19.

The frame signal controller 8 outputs a frame signal FRAME at the timing of counting up of the total counter 6 and generates a signal DF for inverting the bias polarity of the liquid crystal for each frame.

The count number of the total counter 6 becomes an address (address B) for accessing the VRAM 10 as it is.

The image data in the VRAM 10 is read and written through the liquid crystal data control unit 7. When the CPU 19 reads and writes the contents of the VRAM 10, the address A is selected, and when the display contents are read by the liquid crystal driver, the address B is selected, and control is performed so that the timings of the two do not overlap.

Also, since the data read from the VRAM 10 is 8 bits and the LCD driver is 4-bit data, the read data is divided into upper 4 bits and lower 4 bits, and the clock (C
P) and sent out in synchronization.

The signals DISP OFF1 and DISP set in register 2
OFF2 is a control signal for turning the LCD driver display to the OFF state (constant output voltage). In normal mode, all drivers DISP OFF1 and DISP OFF2 are set to “H” for all drivers, and used in reduced mode. Only the DISP OFF1 wired to the driver that does not have an “L” level.

FIG. 2 shows a timing waveform of the operation described above. FIG. 2A shows the normal mode, and FIG. 2B shows the reduction mode. In the waveform, the upper signals LOAD, DF, and FRAME represent signals for one frame, and the lower signals from DF to address B represent signals for one line. 2 (a) and 2 (b) are both 1
The time width corresponding to the frame is the same.

FIG. 3 shows a driver circuit of the liquid crystal panel 17. 11, 12
Are common drivers (eg, MSM5298: Oki Electric), 13, 14, 1
5 and 16 are segment drivers (for example, MSM5299: Oki Electric)
It is. In the normal mode, all the drivers are used, and in the reduced mode, only the drivers 11, 13, and 14 are used.

Therefore, the signal DISP OFF2 is output from the drivers 11, 13, 14
Further, the signal DISP OFF1 is connected to the drivers 12, 15, and 16.

Next, the fourth step is to reduce and smooth the display screen.
This will be described with reference to the drawings. 4 each indicate one display dot on the liquid crystal panel 17.

In the present embodiment, when reducing the display image, the screen is reduced by half.
In order to reduce the apparent frequency of data transfer, four dots are converted to one dot, and the spatial frequency of the image is reduced by performing smoothing.

Therefore, first, as shown in FIG. 4 (a), 12 pixels (a5 to a16) around the target pixel 4 dots (a1 to a4) are taken in, and each pixel is weighted as in (b).

The pixel of interest is large and small in the oblique direction. The value A obtained from the following equation is A ≧ 19.
, The target pixel dot is “H”, and when A <19, “L”
(A = 36 for all pixels black).

Next, a control procedure when the reduction and smoothing of FIG. 4 are performed by software is shown in a flowchart of FIG.
The illustrated procedure is executed by the CPU 19. In the procedure shown in FIG. 5, the display data area
Part of the area such as AM10 or RAM21 is VRAM1 and VR
Used as AM2.

At step S1 in FIG. 5, the pixel of interest and surrounding data are read from the VRAM 10 in which the image information currently displayed is stored. The data is composed of a total of 16 bytes of 4 bytes as a pixel of interest and 12 bytes as a periphery in order to create 8-bit reduced image data by one reading. The data at the end without an image is set to 0.

In step S2, the data captured in step S1 is
The target pixel is decomposed into bit data a1 to a16 for each pixel, and A is calculated in step S3 by weighting each pixel element (a1 to a16) according to equation (1).

In step S4, whether the calculated A is 19 or more,
It is determined whether the reduction smoothing result of the target pixel is 1 or 0 depending on whether it is small. If A is 19 or more in step S4, step
The process proceeds to S5, where the target pixel = 1, that is, black, and when the pixel is smaller than 19, the target pixel = 0, that is, white in step S6.

Then, in step S7, one bit of the pixel of interest is sequentially converted into byte data according to the image position.

In step S8, it is determined whether the target pixel data has been calculated in 8 bits. If not, the process returns to step S2 again.
The same calculation is performed for the next target pixel. When 8 bits are calculated, it is a buffer for reduced data in step S9
Write data to VRAM1.

If data conversion for one screen is not completed, step
In step S10, the process returns to step S1 to read the next 16-byte pixel group of interest and continue the calculation.

When one screen is completed, the data in VRAM10 is saved to VRAM2 in step S11, and the data in VRAM1 is stored in VRAM2 in step S12.
Transfer to RAM10. Thereby, the image displayed on the screen of the liquid crystal panel 17 is reduced and smoothed.

Although not shown in the flow chart hereinafter, when entering this mode, the mode is automatically entered when the user has not made an input for a certain period of time (for example, 5 minutes), or entered according to the mode setting of the user.

Then, if there is any input from the user, immediately transfer the original image saved in VRAM2 to VRMA,
Return to normal screen mode. In the case of an application that needs to change the value even when the display screen is a reduced screen, such as a clock, only the time display portion is reduced and smoothed according to the above algorithm, and written to the VRAM 10.

The above-described display screen reduction and smoothing processing is used as an alternative to the conventional auto power-off control when it is confirmed that there is no input for a fixed time by a known method such as measuring a time interval with the input pen 30. In addition to the execution, a reduction and smoothing process may be performed according to a user's instruction by operating the input pen 30 or a switch (not shown).

By reducing and smoothing the display screen and reducing the display data and control signal transfer frequency and turning off the display driver section that does not contribute to the display, the display-related power is always displayed while the information required by the user is constantly displayed. Great savings can be made.

Moreover, at the time of reduction, smoothing processing is performed instead of simple reduction by thinning out dots.
High-quality display can be performed, and display visibility and operability are not impaired.

Further, in the conventional method in which the entire display is erased, there is a problem that the determination cannot be made only by looking at the state of the device. However, this embodiment does not have such a problem.

In input control other than display, time measurement, and the like, a normal operation is performed even during a reduced screen.

Here, FIG. 6 shows an example of a screen display in a typical application of the electronic apparatus in the present embodiment.

The display in FIG. 6 (a) is for a world clock, and the central year, month and day are in Japan Standard Time. It is an application that displays the standard time of each location when pointing each point on the world map with a pen (the digitizer and the display screen are integrated), mouse, etc.

When the above-described reduction and smoothing processing is applied to the display of this application, a display reduced in area ratio to 1/4 as shown in FIG. 6B is obtained.

Although a part of the map of the reduced image has disappeared due to the smoothing, the date and time can be read according to the smoothing process described above.

On the other hand, the calendar shown in FIG. 6 (c) is an application that allows registration and confirmation of the schedule of the day by pointing each date. According to the smoothing process described above, the reduced screen is a ruled line of the calendar,
Although the day of the week disappears, the characters representing the day, year, and month become readable (FIG. 6 (d)).

In the above embodiment, a liquid crystal was assumed as the display element, and the simple matrix method was described as the driving method. Hereinafter, amorphous Si or polycrystal is used as the driving method of the liquid crystal.
The case of using an active matrix method using Si and a thin film transistor (TFT) will be described.

The active matrix method is one in which one transistor is arranged for one pixel on a substrate, and is also effective in expressing halftones.

As shown in FIG. 9, the scanning circuit and the data driver circuit form a matrix structure. In the reduced mode, the scanning circuit 91 scans the active matrix terminals 1 to 80 in the same manner as described above. Switch to scan ~ 40, and at the same time, halve the clock frequency,
Further, by switching the display data supply via the data driver 92 from using only the terminals 1 to 320 to using only the terminals 1 to 160, it is possible to achieve screen reduction and power saving. it can.

It goes without saying that the same control can be performed by using a simple matrix or an active matrix EL (electroluminescence) or a plasma display other than the liquid crystal display.

In the above embodiment, the compression / smoothing is performed by software based on the equation (1), but may be performed by hardware. FIG. 10 shows an example of such a hardware configuration. The circuit of FIG. 10 mainly performs the above-mentioned weighting processing in hardware.

In FIG. 10, symbols D1 to D16 are shift registers,
The pixel data input in 4-bit parallel to the terminals A to E are respectively weighted, summed by an adder circuit 94, and compared by a comparator 95 to determine whether the addition result is 19 or more.
1-byte output data F is obtained. By shifting the data of A to E by 2 bits every time one bit is obtained, 8-bit compressed data F can be obtained.

The weighting is not limited to the one shown in FIG. 4, and it goes without saying that other coefficients may be adopted according to desired display control conditions.

[Effects of the Invention] As is apparent from the above, according to the present invention, in an electronic device having a display means for performing dot matrix display, the number of rows or columns actually used for display drive of the dot matrix of the display means And a means for variably controlling image data, and a means for compressing image data, reducing a display area actually used for display driving of the display means according to a predetermined control condition, and including the reduced display area in the reduced display area. Since the configuration for displaying the image data compressed by the compression means is adopted, the display area used for the display drive can be reduced according to the desired control conditions, and the compressed image data can be displayed in both the reduced display areas. In addition, there is an excellent effect that power required for display can be saved, and required display information can be transmitted to a user without omission by reduced display.

[Brief description of the drawings]

FIG. 1 is a block diagram of a liquid crystal control unit for switching between a normal mode and a reduction mode, and FIGS. 2A and 2B are timing charts of the normal mode and the reduction mode, respectively.
FIG. 3 is a block diagram of a liquid crystal display driver, FIGS. 4 (a) and 4 (b) are explanatory diagrams showing weighting processing in reduction and smoothing control, FIG. 5 is a flowchart of reduction and smoothing control, and FIG. 7 (a) to 7 (d) are explanatory views illustrating screen displays, FIG. 7 is a perspective view showing the outer shape of the electronic device, FIG. 8 is a block diagram of the entire control system of the electronic device, and FIG. 9 is active. FIG. 10 is a block diagram showing a configuration using a matrix liquid crystal, and FIG. 10 is a block diagram of hardware for performing reduction and smoothing. 1 Divided frequency selector 2, 4, 7 Register 3 Column counter 5 Load timing controller 6 Total counter 8 Frame signal controller 9 Liquid crystal data controller 10 VRAM 11,12 Common driver 13-16 Segment driver 17 Liquid crystal element 31, Input / output surface

Claims (3)

(57) [Claims] 1. An electronic apparatus having display means for performing dot matrix display, comprising: means for variably controlling the number of rows or columns actually used for display driving of the dot matrix of the display means; and means for compressing image data. Having a display area actually used for display driving of the display means reduced in accordance with a predetermined control condition, and displaying the image data compressed by the compression means in the reduced display area. Electronic equipment characterized. 2. An electronic apparatus according to claim 1, further comprising means for variably controlling a control clock frequency of said display means. 3. The electronic apparatus according to claim 1, further comprising means for performing image data smoothing processing together with image data compression when said display area is reduced.