JP2742314B2 - Clock matching method and device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial applications]

The present invention relates to a clock matching method and apparatus, and more particularly, a clock signal matching method and apparatus when a clock signal of a received digital signal and a clock signal of a processing device for processing the received digital signal have a frequency difference. In particular, such as an exchange, a fixed-length digital data is transmitted as a transfer unit (cell), an information signal is transmitted, and a transmission frame is received as a set of a cell array as a group of cells and management operation information, This is effective when applied to a processing device that performs processing in units of cells.

[Prior art]

When transmitting digital signals, if there is wander in the transmission line even in an asynchronous network or a synchronous network, a reception clock signal synchronized with the received digital signal and a clock of a device for processing the received digital signal. Clock matching with the signal is required. 2. Description of the Related Art Conventionally, in the case of an asynchronous network, particularly, when transmitting a digital signal as a packet, clock matching is performed through a buffer memory. In particular, the prior art shown in FIG. 2 is known for transmitting a fixed-length packet (cell) called an asynchronous transfer mode. In this prior art, a reception digital signal is written into a buffer memory 22, 22 'with a reception clock 25 synchronized with a reception signal in a reception cell 21, 21', and is read out with a device clock 26 of a signal processing device. At that time, if the reception clock 25 is faster than the clock 26 of the signal processing device,
Insert 23. On the other hand, in the opposite case, the empty cell 24 is removed from the reception cell row 21 '. The above prior art is described in Reference 1, IEE, Journal on Selected Area in Communication, Vol. 6, 1528.
Page 1537 (IEEE Journal on Selected Are)
a in Communications, Vo16.pp1528-1537). On the other hand, as a clock matching method of a synchronous network, particularly a digital signal transmission method of a synchronous network called frame transmission, reference 2, Bell Communication Research, Technical Advisory TA-TSY-00253, page 25 (Bell Commu
nications Research, Technical Advisory, TA-TSY-002
53, p25)), a method using staff synchronization is known. The method based on stuff synchronization is a method in which control information indicating the start position of an information signal in a frame is provided in management information called a header, and the start position of the information signal is controlled by the number of bytes corresponding to the stuff information. Clock matching is performed by inserting a proper stuff (when the received clock is slower than the device clock) or a negative stuff (when the received clock is faster than the device clock) as appropriate.

[Problems to be solved by the invention]

Using a transmission network based on frame transmission as the synchronous network, digital signals in an asynchronous transfer mode,
That is, it is desirable to transmit cells from the viewpoint of using existing equipment. However, the technique described in the above-mentioned document 1 does not consider the point of transmitting a digital signal in the asynchronous transfer mode via the transmission network which is the synchronous network, in particular, does not consider clock matching. There was a problem that facilities could not be used. SUMMARY OF THE INVENTION It is a first object of the present invention to provide a method and means for solving the above-mentioned problems and for solving the problem of clock matching when transferring a cell string through a transmission network using a synchronous network. Further, in the transmission network which is the above-mentioned synchronous network, the stuff processing is executed at each relay node when digital data is transferred while being relay-multiplexed. The relay node does not process the digital data itself, which is the content of the transmission frame, but processes only the transmission frame unit, and the clock mismatch is transmitted as stuff information. on the other hand,
In a node that exchanges / multiplexes digital data, which is the content of a transmission frame, it is necessary to terminate stuff information with a large-capacity memory or the like to absorb clock mismatch.
Even when the digital data is a cell row related to the asynchronous transfer mode, it is possible to absorb the clock mismatch by using a large-capacity memory for the switching / multiplexing process. A memory amount for this requires several kilobytes corresponding to the information amount of one frame. Accordingly, another object of the present invention is to reduce the capacity of a buffer memory for clock matching in frame transmission.

[Means for Solving the Problems]

In order to achieve the above object, in the present invention, a transmission frame is configured by combining a cell sequence as a group of cells and management operation information, and a stuff synchronization method is used as clock matching means in transferring the transmission frame. In the communication network to be used, a stuff signal inserted as a result of the stuff synchronization processing is removed by removing or inserting an empty cell in the cell train, and a reception clock and the cell train received together with the transmission frame are processed. A method for matching the device clock to be implemented has been realized. Further, as an apparatus for performing the above method, a circuit for obtaining a write timing signal from stuff information of a received digital signal and a received clock signal, and a buffer memory capable of removing a received cell using the received clock signal corrected with the stuff information It comprises a write control circuit, a buffer memory write control circuit into which empty cells can be inserted using the device clock, and a buffer memory having a relatively small capacity.

[Action]

If the digital data is a cell row, insert an empty cell /
Clock elimination can be performed by removal, and the required memory amount in that case may be at most several cells (several hundred octets). For this reason, if the stuff information processing is converted to the empty cell insertion / removal processing, the required memory amount can be greatly reduced.
In addition, this conversion processing enables the same exchange / multiplexing processing as that of a cell string received from a network other than a cell string received from a network in which clock mismatch is transmitted as stuff information.

【Example】

Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a configuration of an embodiment of a clock matching device for implementing a clock matching method according to the present invention.
FIG. 3 is a diagram showing a transmission frame configuration of a received digital signal input to the clock matching device. As shown in FIG. 3, the received digital signal 101 has a frame configuration in which each row includes a section overhead (SOH) area of 9 bytes and a virtual container (VC) area. The SOH area includes management information such as maintenance and control information. In the SOH area, there is an AU pointer indicating the head position of the container, which also serves as stuff control information. In other words, a stuff area is provided by setting a 3-byte area before and after the ninth and tenth byte boundaries of the line where the AU pointer is located.
The region includes a plurality of cells as shown in FIG. The cell is composed of, for example, a fixed number of bits of 53 bytes, a 1-byte access area ACF, a 4-byte header area HED, and 48 bytes.
It consists of a byte information area INF. Whether or not the cell is an empty cell is provided with a specific bit in the access area ACF. The synchronization separation circuit 11 separates and extracts a reception clock 102 and an overhead timing signal designating an overhead area portion from the reception digital signal 101. The received digital signal 101 is converted by the serial / parallel conversion circuit 10 into 8
The signal is converted into a parallel signal of bits and applied to the stuff detection circuit 12. The stuff detection circuit 12 receives the digital signal 101
Is detected, and the presence / absence of positive / negative stuff is detected. For this stuff detection method, a conventionally known technique, for example, described in the above-mentioned document 2 is applied. The overhead removing unit 19 includes the receiving clock 102, the overhead timing signal, and the stuff detecting unit.
The stuff information 110 detected at 12 is input, and a timing signal 102 'excluding an overhead part is generated. At this time, depending on the contents of the stuff information 110, a reception clock may or may not be generated in the stuff information portion of FIG. That is, the stuff information is reflected on the clock signal 102 '. Digital signal passed through stuff detection circuit 12
Reference numeral 103 denotes a RAM through a cell synchronization circuit 18 and an empty cell detection circuit 13 and according to a write address 118 from the address control unit 15.
It is written into a buffer memory 14 composed of a memory. The empty cell detection circuit 13 examines the access area ACF of the cell by using the cell synchronization signal and determines whether or not the cell is empty. The position specifying signal 111 is applied to the empty cell removing circuit 16. Although the structure of the empty cell removing circuit 16 will be described in detail with reference to FIG. 7, the function is to stop the write clock 102 'modified with respect to the overhead portion and the empty cell portion of the received digital signal, and to the buffer memory 14. Is prevented from being written. The address control unit 15 controls the write and read addresses to and from the buffer memory 14 and also controls the write address.
The phase difference between 118 and the read address 119 is monitored. FIG. 5 is a diagram showing a main configuration of the address control unit 15. The address control unit 15 converts the clock 113 from the empty cell removing circuit 16 into a write address 118 by the address counter 27, Clock 116 from address counter 28
To read address 119. The phase difference detection circuit 29 converts the addresses 118 and 119 into a pointer in units of cells and detects the difference. The determination circuit 30 generates an empty cell removal instruction signal 112 and an empty cell insertion instruction signal 115 based on the difference between the pointers. FIGS. 6A and 6B are conceptual diagrams for explaining the operation of the phase difference detection circuit 29. FIG. Inside buffer memory 14
33 is divided in units of cells, and its boundaries are indicated by 34a to 34h. It is assumed that both the pointer 31 indicating the write address and the pointer 32 indicating the read address access the buffer 33 clockwise. As shown in FIG. 6 (a), when the phase difference between the read pointer 32b and the read pointer 32b as viewed from the write pointer 31b becomes smaller than one cell, an empty cell insertion instruction signal 115 is sent from the address control unit 15 to the empty cell insertion unit 17. Will be notified. Also, as shown in FIG. 6 (b), the write pointer 3 as viewed from the read pointer 32b.
When the phase difference of 1b becomes equal to or less than one cell, the empty cell removal instruction signal 112 is similarly notified from the address control unit 15 to the empty cell removal unit 16. FIG. 7 is a circuit diagram showing a configuration of one embodiment of the empty cell removing unit 16. Since the removal of empty cells needs to be performed on a cell-by-cell basis, the signal indicating the beginning of empty cells from the empty cell detector 13
As the reference 111, the writing clock 113 is stopped by stopping the cell period. The gate circuit 41 outputs an empty cell removal instruction 112.
Only when there is, the cell head pulse 111 is accepted and the counter 42 is reset. Counter 42 receives clock 10
The gate circuit 43 counts 2 'for the number of clocks corresponding to the length of the cell, and stops outputting the reception clock 102' as the write address drive clock 113 during the counting period. As a result, no writing is performed in the buffer memory 14 during the empty cell period, so that the write pointer 31b in FIG. 6B stops, and the phase difference viewed from the read pointer 32b increases. In the case of the empty cell insertion circuit 17, it is constituted by a circuit having almost the same configuration as that of FIG. In the case of the empty cell insertion circuit 17, an empty cell insertion instruction signal 115 is input instead of the empty cell removal instruction signal 112, and a device clock 105 is input instead of the reception clock 102 '. The cell head pulse signal 111 is detected by writing phase information indicating the cell head or cell end in the buffer memory 14 in parallel with the cell. The cell signal and cell head position designation signal 114 read from the buffer memory 14 are applied to a signal processing device 20 such as an exchange, and a process synchronized with the device clock is performed. In the method of this embodiment, the stuff information is used for correcting the reception clock, and the control of cell insertion / removal utilizes the phase difference of the address pointer with respect to the buffer. Therefore, there is an advantage that the portion for performing the cell insertion / removal processing can be applied without change even when the stuff information is not included. FIG. 8 is a block diagram showing a configuration of another embodiment of the clock matching circuit according to the present invention. In this embodiment, when the number of bytes of the staff reaches the same amount as the number of bytes of the cell, the operation of inserting and removing an empty cell is performed. In the present embodiment, the stuff detecting unit 12, the overhead removing unit 19, the empty cell detecting unit 13, the empty cell removing unit 16, and the empty cell inserting unit 17 have the same functions and configurations as the parts with the same numbers in FIG. is there. The stuff detection signals 110a and 110b from the stuff detection unit 12 are input to the up / down counter 51. For example, the positive stuff detection signal 110a is input to the up-count side, and the negative stuff detection signal 110b is input to the down-count side. When the count value reaches a predetermined value, the up / down counter 51 outputs an empty cell removal instruction 112 'or an empty cell insertion instruction 115'. These are notified to the empty cell removing unit 16 or the inserting unit 17, and control the write clock 501 or the read clock 502 to the buffer memory 14 '. In this case, the buffer memory 14 '
Applies a FIFO memory that is read out in the order of writing, and does not require address control. Output of up / down counter 51
112 'and 115' are other second up-down counters 53
And the counting result is input to a circuit 52 for presetting a first up / down counter 51. The number of bytes J of the stuff information described with reference to FIG. 3 is not always an integer multiple of the number of bytes L of the cell. For this reason, when empty cells are inserted and removed after an integer number of stuff operations, the data pointer phase of the buffer may not return to the original state. To prevent this, the second up-down counter 53 and the counter preset circuit 52
Use Now, it is assumed that L = JN + K. Normally, empty cell removal is performed once after N regular stuff operations. However, in this case, the data pointer phase of the buffer is shifted by K due to the removal of empty cells. For this reason, (N +
1) Empty cells must be removed by one stuff operation. Now, m N stuff operations and empty cell removal, p (N
+1) If the data pointer phase shift is corrected by the stuff operation and the empty cell removal, it is necessary to set m (JN−L) + p {J (N + 1) −L} = 0. According to this, it is necessary to select p and m so that p / (p + m) = K / J. For example,
When J = 3 bytes and L = 53 bytes, N = 17, K =
2, it is necessary to set p / (p + m) = ｍ. That is, the process of removing cells after the N stuff operation is repeated m = 1 time, and the process of removing cells after the (N + 1) stuff operation is repeated p = 2 times, whereby the phase shift due to K = 0 is corrected. . FIG. 9 shows the operation of the up / down counter 51 and the state of the buffer memory 14 '. First, the up / down counter 51 sets the positive stuff operation to N
After counting (= 17) times, an empty cell removal instruction 112 'is output. The up-down counter 53 performs up-counting +1 by one cell removal instruction. Counter preset
Numeral 52 presets the preset value of the up / down counter 51 to -1 when the output of the up / down counter 53 is +1. As a result, the next correct stuff operation count is executed N + 1 (= 18) times. In the counter preset 52, the output of the second up / down counter 53 is +2.
If, the preset value is preset to -1. As a result, the next positive stuff operation count is also N + 1 (= 18).
Will be executed twice. The counter preset 52 presets the preset value to 0 when the output of the second up / down counter 53 is +3,
Reset 53 to zero. Therefore, when the correct stuff is continuously detected, the above operation is repeated. In the case of the negative stuff operation, the above processing is similarly executed. Further, even in the case where the negative stuff and the positive stuff are mixed, the counter preset circuit 52 operates according to the state of the up / down counter 53, and the phase difference is corrected normally. In this case, even if the positive stuff and the negative stuff are mixed, the counter preset 52 operates according to the output of the second up / down counter 53, and the correction is completely performed. This is shown in FIG. 9 (b). According to the present embodiment, since the buffer memory of the FIFO format can be used, there is an advantage that address control is unnecessary.

【The invention's effect】

As described above with reference to the embodiment, according to the method and apparatus of the present invention, the signal of the cell row that has passed through the network that performs the clock matching by the stuff operation is equivalent to the other cell rows. The process of removing / inserting empty cells makes it possible to match the reception clock with the device clock. Therefore, the capacity of the buffer memory required for clock matching may be several cells, that is, several hundred bytes.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of a clock matching device according to the present invention, FIG. 2 is a diagram for explaining the prior art, FIG. 3 is a diagram showing a configuration of a transmission frame, and FIG. FIG. 5 is a diagram showing a configuration, FIG. 5 is a configuration diagram of one embodiment of a main part of the address control circuit of FIG. 1, FIG. 6 is a conceptual diagram for explaining the operation of the phase difference detection circuit in FIG. 7 is a circuit diagram of one embodiment of the empty cell removing circuit of FIG. 1, FIG. 8 is a block diagram of another embodiment of the clock matching device according to the present invention, and FIG. 9 is blocks 51 and 52 of FIG. And FIG. 53 are diagrams for explaining the operation of the unit 53. 11: Sync separation circuit, 12: Stuff detection circuit, 13: Empty cell detection circuit, 14, 14 ': Buffer, 15: Address control circuit, 16: Empty cell removal circuit, 17: Empty cell insertion circuit, 19: Overhead removal Circuits 27, 28: Address counter, 29: Phase difference detection circuit, 30: Judgment circuit, 51: First up / down counter, 41, 43: Gate circuit, 42: Counter, 52: Counter preset circuit, 53: Second Up-down counter.

Claims (8)

(57) [Claims] An information signal is transmitted with fixed-length digital data as a cell as a transfer unit, and a transmission frame is formed by combining a cell string as a group of cells and management operation information, and a transmission frame is transmitted. In a communication network using stuff synchronization as the clock matching method, a stuff signal inserted as a result of the stuff synchronization processing is removed by removing or inserting empty cells in the cell train, and is removed together with the transmission frame. A clock matching method comprising: matching a received clock to be received with a processing clock of a processing device that processes the cell string. 2. The clock matching method according to claim 1, wherein said reception clock synchronized with said transmission frame is converted by said stuff information, and said reception clock is faster than said device clock. Writing the bits used for the positive stuff into the buffer memory, and controlling to stop writing the bits used for the negative stuff to the buffer memory when the received clock is slower than the device clock. Clock matching method to use. 3. The clock matching method according to claim 2, wherein, when controlling the write and read addresses to and from said buffer memory, a phase difference from a write address to a read address is equal to or less than the length of said cell. If it does, a discardable cell is detected at the input side of the buffer memory, the writing of the cell to the buffer is stopped, and the phase difference from the read address to the write address becomes less than the length of the cell. And reading from said buffer memory is stopped for a period corresponding to the length of one cell at the output side of said buffer memory. 4. The clock matching method according to claim 1, wherein the length of one cell is L (L is an integer representing the number of bytes) and the length inserted and removed by one stuff operation is J.
(J is an integer representing the number of bytes), and when L = nJ + K (n is an integer, 0 ≦ K <J), a discardable cell is detected on the input side of the buffer memory after n stuffing operations. Stopping the writing of the cell to the buffer memory is performed m (m is an integer) times, and after n + 1 times of the stuffing operation, a discardable cell is detected at the input side of the buffer. A clock matching method characterized by repeating the steps of stopping writing to the memory p times (where p / (p + m) = K / J). 5. An apparatus for clock-matching a transmission frame signal composed of management operation information including a stuff signal for stuff synchronization and an information signal including a plurality of cells as transfer units of fixed-length digital data by a buffer memory. An overhead removal circuit that removes an overhead part from a reception clock and creates a corrected reception clock corrected by the stuff signal, and a write control unit for writing a reception transmission frame signal to the buffer memory, An empty cell detection circuit for detecting an empty cell; and a first circuit for generating a write control signal to the buffer memory based on the corrected reception clock and the output of the empty cell detection circuit. Is the device in which the read transmission frame signal is processed. Clock alignment apparatus characterized by being composed of a second circuit to create a read control signal to control the insertion of the location clock signal and read empty cell as an input a position signal of a cell of the transmission frame signal. 6. The buffer memory according to claim 5, further comprising an address control unit for generating a write address and a read address of the buffer memory RAM, wherein the address control unit generates write and read signals from the write address and the read address. A clock matching device comprising: a circuit that detects a phase difference and adds an empty cell removal or empty cell insertion signal to the first and second circuits based on the phase difference. 7. The clock matching circuit according to claim 5, further comprising: counting a positive stuff and a negative stuff of the stuff signal, and vacating the first circuit in accordance with the counted values of the positive stuff and the negative stuff. A first up / down counter for generating a first instruction signal for instructing cell removal and a second instruction signal for instructing the second circuit to insert an empty cell; counting the first and second instruction signals; And a second up / down counter for presetting a preset circuit of the up / down counter.
A clock matching device comprising a memory. 8. The method according to claim 5, 6 or 7,
A clock matching apparatus, wherein information on the phase of the cell in the buffer memory is written simultaneously with the cell in the buffer memory.