JP2738726B2 - Gate turn-off thyristor protection device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a thyristor (hereinafter, GT) having a gate arc extinguishing function.
More specifically, the present invention relates to a GTO protection method that detects that the voltage of a power supply unit that controls the gate has risen normally and outputs a gate pulse.

[Conventional technology]

Related to this type of protection are, for example,
Japanese Patent Application Laid-Open No. 52-88751 discloses a "protection device for a switching regulator". In the present invention, a rise of a power supply for driving a base of a transistor which is a switching element for control is detected. Limited to
No mention is made of a power supply for phase logic which controls the on period and the off period of the transistor.

[Problems to be solved by the invention]

The above prior art is limited to detecting the rise of a power supply for driving a base of a transistor, and does not consider a power supply for phase logic for controlling an on period and an off period of a transistor.

An object of the present invention is to provide a power supply unit for a gate circuit for outputting a GTO gate pulse in a device using a GTO,
The power supply for the phase logic circuit that controls the GTO on-period and off-period outputs the GTO gate pulse only when both rise to the normal voltage, thereby providing reliability and stability. The object is to provide a highly reliable device.

[Means for solving the problem]

The purpose of the above is to turn on / off the gate turn-off thyristor.
A logic circuit for generating an off signal, a power supply for the logic circuit, a gate circuit for outputting a gate pulse to the gate turn-off thyristor based on an output signal of the logic circuit, and a power supply for driving the gate circuit First detection means for detecting that the output voltage of the power supply of the logic circuit has risen to a predetermined value and outputting a detection signal; and output voltage of the power supply for driving the gate circuit rising to a predetermined value. Second detection means for detecting that the signal has been detected and outputting a detection signal, and transmission of an output signal from the logic circuit to the gate circuit when the output of the first detection means or the second detection means has ceased. And means for blocking

[Action]

Means for preventing transmission of an output signal from the logic circuit to the gate circuit is a power supply unit for a gate circuit, or
When the power supply for the logic circuit is not activated, the operation is performed so that the output signal is not transmitted from the logic circuit to the gate circuit. As a result, the gate circuit does not apply a gate pulse to the GTO, so that it is possible to prevent the GTO from being destroyed by an incomplete gate pulse.

〔Example〕

 Hereinafter, an embodiment of the present invention will be described with reference to FIG.

The apparatus shown in FIG. 1 includes a phase logic circuit 1 for controlling an ON period and an OFF period of a GTO, an optical part 2 for transmitting an output of the phase logic circuit 1 as an optical signal, and an optical part as a GTO on / off signal. 2, a gate circuit 5 for supplying gate pulses 21 to 23 as an output 35 to the gate of the GTO 4 as shown in FIG. 2, a power supply 7 for the phase logic circuit 1, and a power supply for the gate circuit 8, a voltage detection circuit 9 of the power supply unit 7 for the phase logic circuit, and a power supply unit 10 for the gate circuit.

The voltage detection circuits 9 and 10 detect that the voltage of each power supply has risen to a normal value, and output “1”. Only when the power supply voltage rise signal 41 becomes “1”.

In addition, when an on / off pulse is generated, a “1” is output for the time until the GTO completely transitions from on to off or from off to on. 41 and the or gate
By taking OR logic at 12, a pulse transmission signal 42 is sent to the interlock mechanism 13.

Only when the pulse transmission signal 42 is "0", for example, the interlock mechanism 13 disconnects the power supply unit 7 and the optical part 2 by a contact of a relay as shown in FIG. The pulse is not transmitted to the gate circuit 5.

FIG. 2 shows a gate pulse supplied from the gate circuit 5 to the gate of GTO4. It consists of three parts: an overdrive current 21 when the GTO is turned on, a wide on-current 22 for maintaining the GTO on state, and a reverse current 23 for turning the GTO off.

FIG. 3 shows the operation of each unit when the power supply voltage rises. The numbers assigned to the respective waveforms correspond to the numbers shown first.

A power supply voltage rising signal 39 of the power supply unit 7 for the phase logic circuit and a power supply voltage rising signal 40 of the power supply unit for the gate circuit 5
The power supply voltage rising signal 41 rises only when both are rising. Thereafter, the pulse transmission signal 42 is sent to the interlock mechanism 13 by the OR logic of the power supply voltage rising signal 41 and the transmission signal 31 when the on / off pulse is generated. Pulse transmission signal 42
Upon receiving the signal, the interlock mechanism 13 short-circuits the power supply unit 7 for the phase logic circuit and the optical part 2, and the optical part 2 transmits the output of the circuit logic circuit 1 to the gate circuit 5. The gate circuit 5 receiving the output 32 from the optical part outputs a gate pulse 35.

FIG. 4 shows the operation of each unit when an abnormality occurs in the power supply unit 7 or 8 during operation.

When the phase logic circuit power supply unit 7 becomes abnormal, the power supply rising signal 41 changes from “1” to “0” to notify the phase logic circuit 1 that the power supply has become abnormal. At this time, the phase logic circuit 1 outputs a signal so as to turn off the GTO. At this time, if the output of the phase logic circuit happens to be immediately after sending the ON signal or immediately after sending the OFF signal, If the on-pulse or the off-pulse is removed on the way, the GTO is destroyed, so that the pulse transmission signal 42 cannot be changed from “1” to “0” immediately.

In this embodiment, the above-described gate pulse removal inhibition signal 31 is provided so that the gate pulse does not disappear during these periods.

Immediately after outputting the on-pulse, after the pulse is generated,
When the gate pulse removal prohibition signal 31 is about to change to "0", an off pulse is generated to turn off the GTO. Then, after the pulse is generated, the gate pulse removal inhibition signal
31 changes to “0”, the pulse transmission signal 42 changes from “1” to “0”, and the output 32 from the optical pearl 2 is cut off.
The pulses generated thereafter are removed.

Immediately after the output of the off-pulse, the pulse transmission signal 42 is changed from “1” to “0” after the gate pulse removal prohibition signal 31 changes to “0” after the pulse is generated, and the pulses generated thereafter are removed. I do.

After the pulse is generated, the gate pulse removal prohibition signal 31 is configured with a one-shot timer pulse in consideration of the transition time of the GTO from on to off and from off to on after generating the on-pulse or off-pulse. May be.

In the present embodiment, the interlock mechanism 13 is a relay contact, but may be replaced with a switching semiconductor element.

〔The invention's effect〕

According to the present invention, it is possible to safely control the GTO even when the power supply rises at the start of operation and when the power supply fails during operation.

[Brief description of the drawings]

FIG. 1 is a system diagram of one embodiment of the present invention, FIG. 2 is a GTO gate pulse diagram, FIG. 3 is an explanatory diagram of the operation of the embodiment when the power supply rises, and FIG. FIG. 4 is an explanatory diagram of the embodiment. 1 ... Phase logic circuit, 2 ... Optical parts, 4 ... GTO, 5
… Gate circuit, 7,8… Power supply, 9,10… Voltage detection circuit, 11… And gate, 12… OR gate, 13… Interlock mechanism, 21,22… Gate pulse.

 ──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Tetsuya Mizobuchi 1070 Ma, Katsuta-shi, Ibaraki Pref. Mito Plant, Hitachi, Ltd. (56) References JP-A-62-144562 (JP, A)

Claims (2)

(57) [Claims] 1. A logic circuit for generating an on / off signal of a gate turn-off thyristor, a power supply unit of the logic circuit,
A gate circuit for outputting a gate pulse to the gate turn-off thyristor based on an output signal of the logic circuit, a power supply for driving the gate circuit, and an output voltage of the power supply for the logic circuit rising to a predetermined value. First detecting means for detecting that the output voltage has risen and outputting a detection signal; and second detecting means for detecting that the output voltage of the power supply unit driving the gate circuit has risen to a predetermined value and outputting a detection signal. Means for preventing transmission of an output signal from the logic circuit to the gate circuit when the output of the first detection means or the output of the second detection means has ceased. 2. A device according to claim 1, wherein said means for outputting a signal indicating that said gate turn-off thyristor is in a transition state from on to off or in a transition state from off to on is provided. A protection circuit for a gate turn-off thyristor, provided in a logic circuit, for prohibiting the output signal from being blocked by the means for blocking transmission of the output signal during a period when the signal is being output.