JP2738289C - - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a liquid crystal display device, for example, a method for manufacturing an active matrix type liquid crystal display device. 2. Description of the Related Art An active matrix type liquid crystal display device has a thin film transistor (TFT) as a switching element for each pixel. Since the thin film transistor can be formed of amorphous silicon (a-Si), it is inexpensive. In addition, a display device having a large area can be realized. A conventional active matrix type liquid crystal display device will be described with reference to FIGS. 6A is a plan view, and FIG. 6B is a plan view of FIG.
7) is a cross-sectional view taken along the line VI-VI, and FIG. 7A is a cross-sectional view of the thin film transistor portion of FIG. As shown in FIG. 6A, the thin film transistor is a transparent pixel electrode 1
09 is formed between the source pattern 107 and the drain pattern 108 connected to the gate pattern 09 and is switched by the potential of the gate pattern (gate layer) 102.
The details will be described with reference to FIGS. 6B and 7A.
A gate layer 102 is formed thereon, and a first gate insulating layer 1031 made of TaO, SiO, or the like and a second gate insulating layer 1032 made of SiN or the like are stacked thereover to form a gate insulating layer. Further, an I-layer amorphous silicon layer 104 for forming a channel of the thin film transistor and an N-type amorphous silicon layer 105 for forming a low-resistance contact are formed thereon. And Cr, Mo-Ta,
A source pattern 107 and a drain pattern 108 having a single-layer or multilayer structure of Al or Al / Ta are formed, and then a transparent pixel electrode 109 made of ITO is formed.
And an insulating protective layer 110 is formed. FIG. 7B shows a modification of FIG. 7A (refer to Japanese Unexamined Patent Publication No.
324938). In FIG. 7B, the gate layer 102 is embedded in the concave portion 101a of the glass substrate 101. That is, an etching mask having an opening of a gate pattern is formed over the glass substrate 101 using a photoresist. Next, the substrate 101 is etched by an ion beam milling device using Ar. The etching depth is substantially equal to the gate layer 102. In this way, the gate layer 102 is filled in the concave portion 101a of the glass substrate 101,
As a result, the glass substrate surface and the gate layer are flush with each other. Therefore, the height (thickness) of the thin film transistor from the substrate surface is reduced, preventing poor alignment, reducing defects due to the gap control material of the liquid crystal layer, and increasing the thickness of the gate layer by sufficiently increasing the depth of the concave portion. And the resistance can be reduced. FIG. 8 and FIG. 9 show a method of manufacturing another active matrix type liquid crystal display device, in which a gate insulating layer and an insulating protective layer are formed simultaneously (see:
JP-A-2-234126). That is, as shown in FIG. 8A, a conductive film g1 made of Cr is sputtered on a glass substrate G0 to form a gate line GL, a gate electrode GT, a first layer of a gate terminal GTM, and a storage capacitor (not shown). Is formed. Next, a conductive film made of A1 or the like is sputtered to form a second layer also on the second layer of the gate line GL and the gate terminal GTM. In this case, the end of the conductive film g2 on the gate terminal GTM is positioned outside the periphery of the protective film (PSV1 in FIG. 9). Next, as shown in FIG. 8B, a silicon nitride film G1, an I-type amorphous silicon film AS, and an N + type silicon film d0 are provided by a plasma CVD method to form an I-type semiconductor layer. Next, a conductive film d1 made of Cr is sputtered to form a drain line DL.
The first layer of the source electrode SD1, the drain electrode SD2, and the drain terminal DTM is formed. Next, before removing the resist, the N + -type semiconductor layer d0 is patterned by dry etching. Next, a second conductive film is formed by A1 or the like, a second layer of the video signal line DL, the drain electrode SD1, and the source electrode SD2 is formed, and a conductive film d2 is also formed on the drain terminal DTM. In this case, the drain terminal D
The end of the conductive film d2 on the TM is positioned outside the periphery of the protective film (PSV1 in FIG. 9). Next, a conductive film d3 made of an ITO film is sputtered, and a video signal line D is formed.
L, third layer of drain electrode SD1 and source electrode SD2, transparent pixel electrode (not shown)
To form Next, a silicon nitride film PSV having a thickness of 1 μm is formed by a plasma CVD method.
1 is provided. Next, as shown in FIG. 9A, pattern formation of the protective film PSV1 and the insulating film G1 is performed by dry etching. Next, as shown in FIG. 9B, before removing the resist, the conductive film g2 on the conductive film g1 of the gate terminal GTM and the conductive film d2 on the conductive film d1 of the drain terminal DTM are removed. Next, an ITO film is sputtered to form an uppermost layer TMT of the gate terminal GTM and the drain terminal DTM. As described above, since the patterning of the insulating film and the patterning of the protective film are performed at the same time, the pinholes of the resist are not transferred to the insulating film used as the gate insulating film. Since the line, the source electrode, and the drain electrode are not short-circuited, the yield can be improved. However, in the above-mentioned conventional method for manufacturing an active matrix type liquid crystal display device, a signal wiring pattern (
Since the (drain pattern) and the pixel electrode layer in the pixel electrode formation region are formed on the gate insulating layer in the same plane, there is a problem that both are easily short-circuited in a high-density display configuration. In particular, if amorphous silicon remains due to poor etching during patterning of amorphous silicon of a thin film transistor, a short circuit occurs between the drain pattern and the pixel electrode layer or between adjacent pixel electrode layers, thereby causing a point defect defect. I do. Therefore, an object of the present invention is to prevent a short circuit between a signal wiring pattern in a signal wiring region and a pixel electrode layer in a pixel electrode formation region. [0007] In order to solve the above-mentioned problems, the present invention forms a gate layer on an insulating substrate, forms a gate insulating layer on the gate layer, and forms a gate insulating layer on the gate insulating layer. In an active matrix type liquid crystal display device, a semiconductor layer made of amorphous silicon is formed facing a gate layer, and a drain pattern, a source pattern, and a pixel electrode layer connected to the source pattern are formed on the semiconductor layer and the gate insulating layer. And a step of etching and removing the gate insulating layer between the drain pattern and the pixel electrode layer after the step of etching the semiconductor layer. According to the above-mentioned means, the etching residue of the amorphous silicon layer (semiconductor layer) remains on the gate insulating layer between the signal wiring layer (drain pattern) and the pixel electrode layer or between the pixel electrode layers adjacent to each other. Even if present, this etching residue is also etched away at the same time. 1 and 2 show a first embodiment of an active matrix type liquid crystal display device according to the present invention. FIG. 1 (A) is a plan view and FIG. 1 (B) is a diagram. 1 (A) I-
FIG. 2 is a cross-sectional view of the thin film transistor portion of FIG. Hereinafter, the manufacturing method will be described in detail. First, C is formed on the glass substrate 1 by sputtering.
Then, a gate layer (pattern) 2 is formed by photolithography. Next, SiN, amorphous silicon, and N + -type amorphous silicon are sequentially deposited by a plasma enhanced chemical vapor deposition (PCVD) method to form a gate insulating layer 3, an I-type amorphous silicon layer 4, and an N + -type amorphous silicon layer 5. Laminate. Next, the predetermined pattern of the N + type amorphous silicon layer 5 is removed by dry etching, and the I-type amorphous silicon layer 4 having the same pattern is removed except for a necessary portion. Further, thereafter, the gate insulating layer 3 is etched by a predetermined pattern (not shown) for conduction with a later-described source pattern 7 and a drain pattern 8 at peripheral terminal portions and the like by dry etching. At this time, the gate insulating layer 3 between the electrode formation region and the drain pattern formation region is also removed by etching at the same time to form the recess 6. Next, a single-layer or multilayer structure of Cr, Mo-Ta, Al or Al / Ta is formed and patterned to form a source pattern 7 and a drain pattern 8.
Next, ITO is deposited by sputtering and patterned to form a transparent pixel electrode layer 9. Further, channel etching of the N + type amorphous silicon layer 5 and the I type amorphous silicon layer 4 is performed by dry etching, and an insulating protective layer 10 is formed thereon. Thus, an active matrix liquid crystal display device is completed. As described above, in the first embodiment, when a contact is formed on the gate insulating layer 3 by dry etching, the gate insulating layer 3 in a predetermined pattern portion between the drain pattern 8 and the pixel electrode layer 9 is simultaneously etched. By removing, even if amorphous silicon residue due to poor patterning of the amorphous silicon layer in the previous process exists between the drain pattern 8 and the pixel electrode layer 9 or between adjacent pixel electrode layers 9, the number of steps can be increased without increasing the number of steps. Can be removed by etching. FIG. 3 shows a second embodiment of the active matrix type liquid crystal display device according to the present invention. FIG. 3 (A) is a plan view, and FIG. 3 (B) is III in FIG. 3 (A). −III
It is a line sectional view. In the second embodiment, a part of the pixel electrode layer 9 is buried in the recess 6 of the gate insulating layer 3 removed by the dry etching in the contact forming step. Thereby, even when the distance between the drain pattern 8 and the pixel electrode layer 9 is very short, the removal of the amorphous silicon residue can be surely performed. FIG. 4 shows a third embodiment of the active matrix type liquid crystal display device according to the present invention. FIG. 4 (A) is a plan view, and FIG. 4 (B) is an IV in FIG. 4 (A). FIG. 4 is a sectional view taken along line IV. In the third embodiment, the portion of the gate insulating layer 3 to be removed by the dry etching in the contact forming step is enlarged to the region where the drain pattern 8 is formed, and therefore, a concave portion 6 'is formed as shown in the figure. As a result, the drain pattern 8
Is buried in this recess 6 '. According to the third embodiment, as in the second embodiment,
Even when the distance between the drain pattern 8 and the pixel electrode layer 9 is very close, the removal of the amorphous silicon residue can be surely performed. FIG. 5 shows a fourth embodiment of the active matrix type liquid crystal display device according to the present invention. FIG. 5 (A) is a plan view, and FIG. 5 (B) is V in FIG. 5 (A). FIG. 5 is a sectional view taken along line V. In the fourth embodiment, the I-type amorphous silicon layer 4 and N
The process up to the patterning of the + type amorphous silicon layer 5 is the same as in the first embodiment. Thereafter, when patterning the gate insulating layer 3 in the contact step, the gate insulating layer in the pixel electrode formation region is not etched away. After that, the source pattern 7 and the drain pattern 8 are further formed, and the transparent pixel electrode layer 9 is further formed. Thereafter, channel engraving is performed, and an insulating protective layer 10 is formed thereon. Then, at the time of the insulating protection layer processing step (passivation step), a predetermined pattern of the insulating protection layer 10 and the gate insulating layer 3 around the pixel electrode layer 9 are simultaneously removed by etching to form a concave portion 6 ″. Is approximately equal to the thickness of the gate insulating film, whereby the amorphous silicon residue due to the poor patterning of the amorphous silicon layer can be removed by etching, as in the first embodiment. As described above, according to the present invention, even if there is an etching residue due to an amorphous silicon layer patterning defect between a drain pattern (signal wiring pattern) and a pixel electrode layer or between successive pixel electrode layers, this can be removed at the same time. Between the pixel electrode layer and the continuous pixel electrode layer It is possible to reduce defects poor. Incidentally, the results of the prototype stage, the adoption of the present invention, the point defect failure became about 40% compared with conventional models.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 shows a first embodiment of an active matrix type liquid crystal display device according to the present invention, wherein (A) is a plan view and (B) is a cross section taken along line II of (A). FIG. FIG. 2 is a sectional view showing a first embodiment of the active matrix type liquid crystal display device according to the present invention. 3A and 3B show a second embodiment of the active matrix type liquid crystal display device according to the present invention, wherein FIG. 3A is a plan view and FIG. 3B is a sectional view taken along line III-III of FIG. 4A and 4B show a third embodiment of the active matrix type liquid crystal display device according to the present invention, wherein FIG. 4A is a plan view and FIG. 4B is a sectional view taken along line IV-IV of FIG. 5A and 5B show a fourth embodiment of the active matrix type liquid crystal display device according to the present invention, wherein FIG. 5A is a plan view, and FIG. 5B is a cross-sectional view taken along line V-V of FIG. 6A and 6B show a conventional active matrix liquid crystal display device, in which FIG.
(B) is a sectional view taken along line VI-VI of (A). FIG. 7 is a cross-sectional view of the TFT part of FIG. FIG. 8 is a sectional view showing another conventional active matrix type liquid crystal display device. FIG. 9 is a cross-sectional view showing another conventional active matrix liquid crystal display device. DESCRIPTION OF SYMBOLS 1 ... Glass substrate 2 ... Gate layer (pattern) 3 ... Gate insulating layer 4 ... I-type amorphous silicon layer 5 ... N + type amorphous silicon layer 6, 6 ', 6 "... Recess 7 ... Source pattern 8 ... Drain pattern 9 Transparent pixel electrode layer 10 Insulating protective layer 101 Glass substrate 102 Gate layer (pattern) 1031, 1032 Gate insulating layer 104 I-type amorphous silicon layer 105 N + type amorphous silicon layer 107 Source Pattern 108 Drain pattern 109 Transparent pixel electrode layer 110 Insulating protective layer

Claims (1)

Claims 1. A gate layer (2) is formed on an insulating substrate (1), a gate insulating layer (3) is formed on the gate layer, and the gate is formed on the gate insulating layer. A semiconductor layer (4, 5) made of amorphous silicon was formed facing the layer, and was connected to the drain pattern (8), the source pattern ( 7 ), and the source pattern on the semiconductor layer and the gate insulating layer. In the active matrix liquid crystal display device having the pixel electrode layer (9) formed, after the step of etching the semiconductor layer, the step of etching and removing the gate insulating layer between the drain pattern and the pixel electrode layer is performed. A method for manufacturing a liquid crystal display device, comprising: 2. The method according to claim 1, wherein the step of etching and removing the gate insulating layer also etches and removes the gate insulating layer around the pixel electrode layer. 3. The method according to claim 1, wherein the pixel electrode layer is formed also on the insulating substrate from which the gate insulating layer has been removed by etching. 4. The method according to claim 1, wherein the step of etching and removing the gate insulating layer also removes a portion of the gate insulating layer where the drain pattern is formed. 5. A gate layer (2) is formed on an insulating substrate (1), a gate insulating layer (3) is formed on the gate layer, and an amorphous layer is formed on the gate insulating layer so as to face the gate layer. A semiconductor layer (4, 5) made of silicon is formed, and a drain pattern (8), a source pattern ( 7 ), and a pixel electrode layer (9) connected to the source pattern are formed on the semiconductor layer and the gate insulating layer. And forming a protective insulating layer (10) covering the drain pattern and the pixel electrode layer. In the active matrix type liquid crystal display device, after etching the semiconductor layer, etching the protective insulating layer And etching the gate insulating layer between the drain pattern and the pixel electrode layer. 6. The method according to claim 5, wherein the step of etching and removing the gate insulating layer also etches and removes the gate insulating layer around the pixel electrode layer.