JP2734192B2 - Music processing unit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a musical tone processing device suitable for use in an electronic musical instrument that synthesizes musical tones based on data stored in a storage means.

2. Description of the Related Art Conventionally, in addition to a method of synthesizing a musical tone by an electric or electronic circuit (so-called hardware), a musical tone is generally synthesized by software. For this purpose, a general CPU (central processing unit), a DSP (Digital Signal Processor) for tone processing, and the like are used.

[Problem to be Solved by the Invention] By the way, since the above-mentioned CPU is originally a general-purpose control device and the other DSP is a general signal processing device,
There is an aspect that it is unsuitable for use as an apparatus for controlling a tone signal used in an electronic musical instrument. That is, in a case where a normal CPU or DSP performs tone control of a plurality of sequences by time-division processing (synthesizing a plurality of musical tones with one sound source; polyphonic), a predetermined value is set every time data of each sequence is switched. Will be saved in the memory area. For this reason, CP
U has to read out the stored data into a predetermined area once for each series of processing, or perform independent processing for each series. Therefore, one CP
In U, there is a very large overhead for each sequence change. On the other hand, the other DSP requires a program for each sequence, which causes a problem that the storage area for storing the program becomes large, and the contents of the register must be transferred for each program. Therefore, there has been a problem that the overall processing capacity is reduced.

The present invention has been made in view of the above problems,
It is an object of the present invention to provide a tone processing apparatus which can reduce the load of the tone control processing, enable high-speed processing, and can share data and programs for each stream.

[Means for Solving the Problems] In order to solve the above problem, in the invention according to claim 1, in the musical sound processing device having musical sound generating means for generating a plurality of musical sound signals in a time-division manner based on parameters, A first storage unit in which the parameters are stored for each tone signal; and a parameter for each tone signal stored in the first storage unit for each of the tone signals sequentially read out. A first control means for performing the above processing and supplying the same to the musical sound generating means, wherein the first control means generates a common first address for the plurality of musical sound signals; and In synchronization with the reading of the parameters of each tone signal,
A second correction address different for each tone signal is generated and a first address common to the plurality of tone signals generated by the first control means is corrected by the first correction address. Control means, wherein the first
The control means reads the parameter stored at the address corrected by the second control means.

According to a second aspect of the present invention, in the tone processing apparatus according to the first aspect, the apparatus further comprises a second storage unit in which a plurality of procedures for performing a predetermined process on the parameter are stored. Is a control unit that reads one of a plurality of procedures stored in the second storage unit and performs the predetermined processing according to the read procedure. The second control means generates a second correction address different for each tone signal in synchronization with the reading of each procedure by the first control means. The second address for the plurality of tone signals generated from the first control means is corrected by the corrected address, and the first control means stores the corrected address in the address corrected by the second control means. Is Wherein the reading out step.

According to the invention, the first control means generates a common first address for a plurality of tone signals, and the second control means generates the first address different for each tone signal. And generates a correction address. When reading the parameters from the first storage means, the first control means reads the parameters stored at the corrected address, performs predetermined processing on the read parameters, and supplies the read parameters to the musical tone generating means. I do.

According to the second aspect of the present invention, the first control means generates a second address for a plurality of tone signals, and the second control means generates a different second correction address for each tone signal. And correct. Then, when reading out any of the plurality of procedures stored in the second storage means, the first control means reads out the procedure stored at the corrected address, and performs a predetermined operation in accordance with the read-out procedure. Perform processing.

"Example" Next, an example of the present invention will be described with reference to the drawings.

First Embodiment FIG. 1 is a block diagram showing a configuration of an electronic musical instrument using a musical tone control device according to a first embodiment of the present invention. In this figure, the musical sound processing CPU 1 synthesizes a plurality of musical tones (polyphonic) using a time division multiplexing and a musical sound formation method using a waveform memory. This tone processing CPU1 is working RAM (random access memory) via adder AD1.
2 is accessed to exchange data D1. Working RAM2
Is composed of dual port RAM,
A parameter (data D1) relating to the musical sound of each stream synthesized by PU1 is stored. The data structure of the working RAM 2 has, for example, as shown in FIG. The reason for having one extra segment is an area for switching sound generation used in the KON processing routine described later. These segments are
It is indicated by the offset value, and inside each segment, the key code K
C, waveform number, EG waveform number, touch information, waveform phase, and EG phase are stored. Also, this working RAM2
Is used as a temporary storage area required for the operation. Next, the address management CPU 3
Is accessed by the address A3 to transfer the data D3. The data D3 is address offset information OF1, which is stored in the offset memory 4 for each channel and supplied to the adder AD1 as shown in FIG.
That is, the address offset information OF1 contains the tone processing C
The address A1 used when the PU1 accesses the working RAM 2 is modified for each system to obtain an address A1 '. Therefore,
The tone processing CPU 1 is characterized in that it is not necessary to save the register every time the series is switched, and the processing can be continuously performed as it is. Switching for each series is a tone processing CP
Switching is performed in synchronization with the interrupt signal INT output by U1.
The address management CPU 3 directly accesses the working RAM 2 by the address A2, and rewrites the tone processing parameters by supplying the data D2. Next, a ROM (read only memory) 5 is used as a waveform memory for tone synthesis, and stores programs of the tone processing CPU 1 and the address management CPU 3, tables of various other information, and the like. The operator 6 is an operator attached to a general electronic musical instrument such as a keyboard. Next, the sound system 7 includes a D / A converter, a tone color adjustment circuit, a volume adjustment circuit, and the like, converts the tone data output from the tone processing CPU 1 into an analog signal, and converts the tone data at a predetermined volume as a tone by the speaker SP. Pronounce. CPU 1 for tone processing, CPU 3 for address management, ROM 5, operation unit 6, and sound system 7
Are connected by a common data bus DB.

Next, the operation according to the above configuration will be described with reference to FIGS.
This will be described with reference to the flowchart shown in FIG.

First, when the power of the electronic musical instrument is turned on or when an instruction is given by a player, one of the tone processing CPUs 1 executes the main routine shown in FIG. In this figure, first, in step SA1, initialization such as clearing of the working RAM 2 is performed. Next, step SA
In 2, the sound processing routine shown in FIG. 5 is executed.

In the sound processing routine, first, in steps SB1 to SB6, various parameters are obtained from the working RAM 2. In step SB1, the address A1 is set to "0" to obtain a key code KC. Next, in step SB2, the address A1
Is set to "1" to obtain the waveform number of the musical tone. In step SB3, the address A1 is set to "2" to obtain an EG (envelope) waveform number. Next, the process proceeds to Step SB4, where the address A1 is set to “3” to obtain touch information. And step SB5
, The address A1 is set to "4" to obtain a waveform phase.
Further, in step SB6, the address A1 is set to "6" to obtain the EG phase.

Next, the process proceeds to Step SB7, where a waveform read address is calculated based on the waveform phase and the key code KC. Then, in step SB8, the waveform value of the musical tone is read using the above-mentioned waveform read address, and the flow advances to step SB9. In step SB9, an EG read address is calculated based on the EG phase and the key code KC. Then, step
Proceeding to SB10, it is determined whether the EG read address has exceeded the final address. Here, if the EG read address exceeds the final address, step SB
The result of the determination at 10 is "YES" and the flow proceeds to step SB11. In step SB11, the EG read address is set to the final address.

On the other hand, if the EG read address is not over, the determination result in step SB10 is “NO”,
Proceed to step SB12. In step SB12, it is not necessary to change the EG read address. However, in the processing by the DSP or the like, the processing time varies depending on the processing content, so that time adjustment is performed to match timing.

When the processing in step SB11 or SB12 ends, the flow advances to step SB13. In step SB12, the EG value is read based on the EG read address, the EG value is scaled by the touch information, and then multiplied by the waveform value read in step SB8 to obtain a final output value. next,
Proceeding to step SB14, the final output value is output to the sound system 7. The sound system 7 converts the final output value into an analog signal and outputs it as a musical tone from the speaker SP. Then, in step SB15, the current waveform phase and EG phase are written back, and the process proceeds to step SB16. In step SB16, an interrupt signal INT is output to the address management CPU3. When step SB16 ends, the sound generation processing routine ends, and the process returns to the main routine shown in FIG. The CPU 1 for the sound processing is provided with a step SA of the main routine.
The above-mentioned sound generation processing routine in 2 is repeatedly executed.

The other address management CPU 3 executes a main routine shown in FIG. First, in step SC1, initialization for clearing various registers and the like is performed. Next, in step SC2, the operator 6 is scanned. Then, in step SC3, it is determined whether or not a key event, that is, a key press or a key release has occurred based on the scan result.

Here, if any key event occurs, step
The result of the determination in SC3 is “YES”, and the flow proceeds to step SC4. In step SC4, in order to determine whether or not the key event is an event due to key depression, the key-on signal KO
It is determined whether N has been output. And in this case,
If a key event is triggered by a key press, the step
The determination result of SC4 is "YES", and the process proceeds to Step SC5.
At step SC5, the KON processing routine shown in FIG. 7 is executed.

In the KON processing routine, first, in step SD1,
Perform initialization. Next, in step SD2,
Various data for sound generation are temporarily stored in a FIFO (First In First Out) according to the information from the manipulator 6. Next, the process proceeds to step SD3, where the EG phase column of the working RAM 2 is checked to search for a channel whose sound is stopped. Then, in step SD4, it is determined whether or not there is a channel whose sound is stopped. Since the current EG output value is known from the EG phase and the EG waveform number, if it is "0", it is determined that the sound generation is stopped. Here, if there is no channel whose sound is stopped, the determination result in step SD4 is “N
O "and goes to step SD5. In step SD5, EG
Search for the channel with the lowest output value and set a dump flag for that channel. Next, proceed to Step SD6,
The EG waveform number, key code KC and EG phase are forcibly written so that the current output value of the above channel can be dumped smoothly. As a result, the tone of the channel is forcibly dumped and an empty channel is secured. As described above, when there is no channel whose sound is stopped, the channel with the most attenuation is forcibly dumped. However, since the dumping takes some time, it is performed by another processing routine. (A dump processing routine to be described later). Therefore, in this routine, as described above, a dump flag indicating that the channel is being dumped is set, and the data related to the EG, out of the data related to the sound generation of the channel, is forcibly rewritten, so that the format is not changed. Perform a single dump.
The actual dump process and the KON process waiting until the end of the dump are processed in a dump process routine described later.

On the other hand, if there is a channel whose sound is stopped, the result of determination in step SD4 is “YES”, and
Proceed to SD7. In step SD7, various data for sound generation stored in the FIFO is transferred to a free area of the working RAM2. Next, the process proceeds to step SD8, in which the offset information of the address corresponding to the channel whose sound is stopped in the offset memory 4 is rewritten. From this point, synthesis of a new musical tone is started.

When steps SD6 and SD8 described above are completed, the KO
The N processing routine ends, and the process returns to the main routine shown in FIG.

In the main routine, the process proceeds to step SC9, and executes a dump processing routine shown in FIG.

In the dump processing routine, first, in step SE1, it is determined whether any dump flag is set. Here, if the dump flag is not set,
The result of the determination in step SE1 is "NO", the process ends as it is, and the process returns to the main routine.

On the other hand, if the dump flag is set,
The result of the determination in SE1 is "YES", and the flow proceeds to step SE2. In step SE2, it is determined whether or not the dump of the channel for which the dump flag has been set has been completed. Here, if the dump of the corresponding channel has not been completed, the determination result in step SE2 is “NO”,
Proceed to step SE5. In step SE5, nothing is performed on the channel, and it is determined whether or not there is another channel on which the dump flag is set. Here, if there is another channel with the dump flag set, step SE
The determination result in 5 is “YES”, and the
Return to SE2. Then, again in step SE2, it is determined whether or not the dump of the corresponding channel has been completed. Here, again, the determination result in step SE2 is “N
In the case of "O", the process proceeds to Step SE5, and the above-described process is repeated. That is, in steps SE2 and SE5, all channels for which the dump flag is set are searched, and channels whose dump has already been completed are searched. If there is a channel for which dumping has been completed, step
The result of the determination in SE2 is "YES", and the flow proceeds to step SE3. In step SE3, F
Transfer various data for pronunciation stored in the IFO. Next, the process proceeds to step SE4, in which the offset information of the address corresponding to the channel for which the sound generation is stopped in the offset memory 4 is rewritten, and the sound generation of the musical sound is started.

On the other hand, even if all the other channels for which the dump flag is set are searched, if there is no channel for which the dump has been completed, the result of the determination in step SE5 is “NO”, and the process is terminated as it is. Return to the main routine shown in FIG.

In the main routine, the process returns to step SC2, and repeats the processing again.

On the other hand, in the main routine, when the key event is not due to the key depression, the determination result in step SC4 is “NO”, and the process proceeds to step SC6. In step SC6, it is determined whether or not the key-off signal KOFF has been output in order to determine whether or not the event is due to a key release. In this case, for example, if the key event is due to a key release, the determination result of step SC6 is “YES”
And proceed to step SC7. In step SC7, a KOFF processing routine shown in FIG. 9 is executed.

In the KOFF processing routine, first, in step SF1, the working RAM 2 is searched for a channel corresponding to the key code KC having a key-off event, and the process proceeds to step SF2. In step SF2, it is determined whether a corresponding channel exists. Here, when the corresponding channel exists, the determination result in step SF2 described above is “YES”, and the flow proceeds to step SF3. In step SF3, in the same manner as in the dump processing described above,
The EG waveform number, the key code KC and the EG phase are forcibly written so that the current output value of the above channel smoothly dumps. As a result, the tone of the channel is forcibly dumped.

On the other hand, for example, the musical tone of the corresponding channel is forcibly dumped by the above-described forcing dump or the like and no longer exists, and the determination result in step SF2 is “NO”.
When the above-mentioned condition is satisfied, or when the above-described step SF3 is completed, the KOFF processing routine is terminated and the process returns to the main routine shown in FIG.

In the main routine, the process proceeds to step SC9, and executes the above-described dump processing routine. When the dump processing routine in step SC9 ends, the flow returns to step SC2, and thereafter, steps SC2 to SC9 are repeatedly executed.

On the other hand, in the main routine, if the key event is not a key release, the result of the determination in step SC6 is “NO”, and the flow proceeds to step SC8.
In step SC8, a process corresponding to a key event due to a key other than a key press / release is performed. Next, the process proceeds to step SC9 to perform the above-described dump processing. If no key event has occurred, the result of the determination in step SC3 is “NO”, and the flow directly proceeds to step SC9 to perform the above-described dump processing.

When the dump process ends, the process returns to step SC2, and repeatedly executes steps SC2 to SC9.

In parallel with the execution of the main routine, a synchronous interrupt processing routine shown in FIG. 10 is executed. This synchronous interrupt processing routine is forcibly executed when the tone processing CPU 1 outputs the interrupt signal INT. First,
At step SG1, necessary registers are saved. Next, in step SG2, the offset memory
Increment the counter and proceed to step SG3. At Step SG3, it is determined whether or not an overflow has occurred. If an overflow has occurred, the result of the determination at step SG3 is "YES", and the routine proceeds to step SG4.
At Step SG4, the offset memory counter is reset.

On the other hand, if the determination result in step SG3 described above is “N
If "O", or if the process of step SG4 is completed, the process proceeds to step SG5. In step SG5, after the saved register is restored, the process returns to the normal processing. Switching of channels is performed by this synchronous interrupt processing routine.

11A to 11E show examples of the EG waveform obtained as a result of the above-described processing. 1A is used for a stringed instrument such as a piano, FIG. 8B is used for a plucked instrument such as a guitar, and FIG. 8C is used for a bowed instrument such as a violin. FIGS. 4D and 4E show attenuation waveforms for a forcing dump.

Second Embodiment Next, a second embodiment according to the present invention will be described with reference to the block diagram shown in FIG. In this figure, portions corresponding to the respective portions of the first embodiment described above are denoted by the same reference numerals, and description thereof is omitted. The feature of this embodiment resides in that the address offset is applied not only to the working RAM 2 but also to the program ROM 10. The program ROM 10 stores a control program for tone synthesis for each stream. The address management CPU 3a also supplies the adder AD2 with the address offset information OF.
2, whereby the control program is changed for each stream. The control program is changed according to which area of the keyboard is divided in advance by a depressed key. As shown in FIG. 13, the offset memory 4 stores a data offset address and a program offset address for each channel (in this example, four channels). In working RAM2,
As shown in FIG. 14, for each channel, a data segment for data and a program segment for programming are on the same memory map. However, it is necessary to pay attention to how to provide them separately or to give an offset so that they do not enter each other region due to the offset. Here, tone synthesis by FM is instructed for channels 1 and 4, and tone synthesis by PCM is instructed for channels 2 and 3. Therefore, segment 2 storing the data of channel 3 (the segment corresponding to channel 3 is not necessarily segment 2)
Stores various parameters required for FM synthesis.

Next, the operation according to the above configuration will be described with reference to FIGS.
This will be described with reference to the flowchart shown in FIG. When the power is turned on or an instruction is given by the player, the same processing as the main routine of the first embodiment shown in FIG. 6 is executed. That is, first, it is determined whether or not a key event has occurred. Next, when a key event has occurred, it is determined whether or not the event is due to key depression or key release. Then, when a key event occurs due to key depression, a KON processing routine shown in FIG. 15 is executed. First, in step SH1, a control program (sound generation algorithm) is determined based on an area to which a depressed key belongs. The control program may be determined based on other touch information, or may be determined in advance for each sound using a sequencer or the like. Next, the process proceeds to step SH2, where various data are determined according to the key code KC, touch data, and sound generation algorithm. Next, the process proceeds to step SH3, where various data for sound generation are stored in the FIFO. Then, in step SH4, the working RAM
Check the EG phase column and search for the channel whose sound is stopped. Then, in step SH4, it is determined whether or not there is a channel whose sound is stopped. This is the first
Similarly to the KON processing routine in the embodiment, the EG phase and the EG
Since the current EG output value is known from the waveform number, if it is "0", it is determined that the sound generation is stopped. Here, if there is no channel whose sound is stopped, the result of the determination in step SH5 is “NO”, and the flow proceeds to step SH6. In step SH6, a channel with the lowest EG output value is searched, and a dump flag for that channel is set. Next, the process proceeds to step SH7, in which data such that the current output value of the channel can be dumped smoothly is forcibly written in accordance with the tone generation algorithm. As a result, the tone of the channel is forcibly dumped, and an empty channel is secured. As described above, this embodiment is characterized in that data corresponding to the sounding algorithm (related to the dump) is given at the time of dumping.

On the other hand, if there is a channel whose sound is stopped, the determination result in step SH5 is “YES”, and
Proceed to SH8. In step SH8, various data for sound generation stored in the FIFO is transferred to a free area of the working RAM2. Next, the process proceeds to step SH9, in which the offset information of the address of the offset memory 4 corresponding to the channel whose sound is stopped is rewritten. From this point, synthesis of a new musical tone is started.

When steps SH7 and SH9 described above are completed, the KO
After terminating the N processing routine, the routine returns to the same main routine as in the first embodiment shown in FIG. 6, and the dump processing is performed.

On the other hand, if a key event due to key release occurs,
The KOFF processing routine shown in FIG. 16 is executed. This KOFF processing routine is substantially the same as the routine of the first embodiment described above. First, in step SI1, the working RAM 2 is searched to find a channel corresponding to the key code KC having a key-off event.
Proceed to. In step SI2, it is determined whether a corresponding channel exists. Here, when the corresponding channel exists, the determination result in step SI2 described above is “YES”, and the flow proceeds to step SI3. Step SI
In step 3, data is output in such a manner that the current output value of the channel smoothly dumps in accordance with the tone generation algorithm in the same manner as in the above-described dump processing. As a result, the tone of the channel is forcibly dumped.

On the other hand, for example, the tone of the corresponding channel is forcibly dumped by the above-described forcing dump or the like and no longer exists, and the determination result in step SI2 is “NO”.
When the above-mentioned condition is satisfied, or when the above-described step SI3 is completed, the KOFF processing routine is ended, the processing returns to the main routine, and the dump processing routine is executed.

On the other hand, the musical sound processing CPU 1 executes a sound generation processing routine shown in FIG. First, in step SJ1, the address A1 is set to “1” to obtain the phase data ωc. Next, in step SJ2, the address A1 is set to “2” to obtain the phase data ωm. Then, in step SJ3, the address A1 is set to "5" to obtain t. Next, the process proceeds to step SJ4 to obtain I (t) and A (t). In step SJ5, a musical tone waveform E is obtained using the parameters obtained in the above-described steps. Next, the tone waveform E is output to the sound system 7 in step SJ6. The sound system 7 converts the final output value into an analog signal and outputs it as a musical tone from the speaker SP. Next, the process proceeds to step SJ7, where the time variable t is advanced, and the address A1 = "5"
Return to Then, in step SJ8, an interrupt signal INT is output to the address management CPU3. And step S
When J8 ends, the sound generation processing routine ends, and the process returns to the main routine (not shown).

Also in this embodiment, the same as in the first embodiment,
The synchronous interrupt processing routine shown in FIG. 10 is executed.

As described above, in this embodiment, not only the address of the working RAM 2 but also the offset of the address of the program RAM 10 are realized.

In the first and second embodiments described above, the addresses of the memory are modified. However, the present invention is not limited to this, and an I / O port may be used.

Further, as an embodiment, the present invention is not limited to the sound source, and may be applied to an effect imparting device provided for each stream.

[Effects of the Invention] As described above, according to the first aspect of the present invention, a common first address is corrected for a plurality of tone signals, and a parameter stored at the corrected address is read. Therefore, when generating a plurality of tone signals, the program of the first control means can be shared for the plurality of tone signals. As a result, only one program needs to be prepared, and the effect that the configuration can be simplified is obtained. Further, according to the second aspect of the present invention, any one of the plurality of procedures is read out for each tone signal and the processing is performed, so that a plurality of tone signals are processed according to different programs for each tone signal. A signal can be generated, and a high-quality tone signal can be generated.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of a first embodiment of the present invention,
FIG. 2 is a conceptual diagram showing the data structure of the working RAM 2 of the embodiment, FIG. 3 is a conceptual diagram showing the data structure of the offset memory 4, and FIG.
FIG. 5 is a flowchart showing a main routine for explaining the operation of U3, FIG. 5 is a flowchart showing a tone generation processing routine of the embodiment, and FIG.
7 is a flowchart showing a main routine for explaining the operation of the CPU1, FIG. 7 is a flowchart showing a KON processing routine of the musical sound processing CPU1, and FIG.
9 is a flowchart showing a KOFF processing routine of the musical tone processing CPU 1, FIG. 10 is a flowchart showing a synchronous interrupt processing routine of the embodiment, and FIGS. 11 (a) to 11 (e). ) Of the embodiment
FIG. 7A is an example of an EG waveform, FIG. 7A is an EG waveform diagram for a stringed instrument such as a piano, FIG. 7B is an EG waveform diagram for a plucked instrument such as a guitar, and FIG. EG waveform diagrams for (a) and (d) and (e) in FIG.
Is an attenuation waveform diagram for a forcing dump, FIG. 12 is a block diagram showing the configuration of the second embodiment, FIG. 13 is a conceptual diagram showing the data structure of the offset memory 4 of the embodiment, and FIG. Conceptual diagram showing the data structure of the working RAM 2 in the example, FIG.
FIG. 15 is a flowchart showing a KON processing routine of the tone processing CPU 1 of the second embodiment, FIG. 16 is a flowchart showing a KOFF processing routine of the tone processing CPU 1 of the second embodiment,
FIG. 17 is a flowchart showing a sound generation processing routine of the second embodiment. 2 ... working RAM (first storage means), 4 ... offset memory (second storage means), 10 ... program RO
M (third storage means), 3, 3a... Address management CPU (address modification means), 7... Sound system (musical sound formation means).

Claims (2)

(57) [Claims] 1. A tone processing apparatus comprising a tone generating means for generating a plurality of tone signals in a time-division manner based on parameters, a first storage means in which the parameters are stored for each tone signal, A first control unit for sequentially reading out parameters for each tone signal stored in the first storage unit, applying predetermined processing to the read-out parameters, and supplying the read parameters to the tone generation unit; First control means for generating a common first address for the plurality of tone signals, and different for each tone signal in synchronization with the reading of the parameters of each tone signal by the first control means. First
And a second control means for correcting a common first address for the plurality of tone signals generated by the first control means with the first correction address. A musical sound processing apparatus according to claim 1, wherein the first control means reads out a parameter stored at an address corrected by the second control means. 2. The tone processing apparatus according to claim 1, further comprising: a second storage unit in which a plurality of procedures for performing a predetermined process on the parameter are stored, wherein the first control unit is provided. Is a control unit that reads one of a plurality of procedures stored in the second storage unit and performs the predetermined process according to the read procedure.
A second address is generated for the plurality of tone signals, and the second control means synchronizes with the reading of each procedure by the first control means, and performs a second correction different for each tone signal. Generating an address, correcting a second address for the plurality of tone signals generated by the first control means with the second correction address, wherein the first control means controls the second control A tone processing device for reading a procedure stored at an address corrected by the means.