JP2731641B2 - Video analog-to-digital converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a monitor circuit for a video / analog converter which converts an analog video signal into a digital signal.

[0002]

2. Description of the Related Art In a conventional example, video data converted into a digital signal is reproduced into an analog video signal using a digital-to-analog converter, and a horizontal synchronization pulse or a vertical synchronization pulse included in the reproduced analog video signal is reproduced. The amplitude was measured to determine whether the video analog-to-digital converter was operating normally or was in a failure state.

[0003]

However, in such a conventional example, there is no problem in the case of a composite type NTSC color television signal having horizontal and vertical synchronization pulses, but it is separated into a luminance signal and two color difference signals. In the case of a video signal in component format, if the horizontal and vertical sync pulses are attached only to the luminance signal, or if no sync pulse is added, the video signal is transmitted separately as a sync signal along with the luminance signal and color difference signal. In some cases, even when the analog video signal is reproduced, no synchronization pulse is included, so that the presence or absence of a failure cannot be monitored.

The present invention has been made in order to eliminate such a drawback, and a video analog-to-digital converter having means for monitoring the presence or absence of a failure of its own device even when a video signal does not include horizontal and vertical synchronization pulses. The purpose is to provide.

[0005]

SUMMARY OF THE INVENTION The present invention provides a buffer amplifier for amplifying and outputting an analog video signal, an analog-to-digital converter for quantizing and outputting the result of sampling the output of the buffer amplifier, and an analog-to-digital converter. Comparing means for comparing the level of a quantization level of a pedestal section of an analog video signal output by a digital converter with a predetermined quantization level and outputting the result of the comparison, and according to the result of comparison output from the comparing means A video-analog-to-digital converter comprising a DC offset voltage control means for controlling a DC offset voltage of the output of the buffer amplifier, wherein the comparing means determines the quantization level of a pedestal section of the analog video signal and A high level between two new predetermined quantization levels with the predetermined level increased or decreased by the predetermined quantization level; And detecting means that the quantization level of the pedestal section of the analog video signal does not belong to the range between the two new predetermined quantization levels, and an alarm is generated according to the detection result of the detection means. Output means.

[0006]

The comparator compares the quantization level of the pedestal section in the video data output from the analog-to-digital converter with a predetermined pedestal level, and when the two do not match, the output DC offset of the buffer amplifier according to the sign of the level difference. The voltage is controlled so that the quantization level in the pedestal section matches a predetermined pedestal level. Therefore, if an error occurs in the analog-to-digital converter and quantization is not performed correctly, control for matching the quantization level in the pedestal section with the predetermined pedestal level becomes impossible, and the value becomes far from the predetermined level. , Detecting this and outputting an alarm.

[0007]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of this embodiment. In this embodiment, as shown in FIG. 1, a buffer amplifier 1 that amplifies and outputs an analog video signal, an analog-to-digital converter 2 that quantizes and outputs a result of sampling the output of the buffer amplifier 1, A part of the comparator 3, a latch 5, and a part of comparison means for comparing the quantization level of the pedestal section of the analog video signal output from the analog-to-digital converter 2 with a predetermined quantization level and outputting the comparison result. The present invention includes a timing pulse generator 4 and an integrating circuit 7 which is DC offset voltage control means for controlling the DC offset voltage of the output of the buffer amplifier 1 according to the comparison result output from the comparison means. The comparing means is characterized in that the comparing means includes a quantization level of a pedestal section of the analog video signal and the predetermined quantization level. The level is compared with two new predetermined quantization levels in which the predetermined level has been increased or decreased by the bell, and the quantization level of the pedestal section of the analog video signal falls within the range between these two new predetermined quantization levels. An OR gate 8 including a part of the comparator 3 which is a detecting means for detecting that the signal does not belong, a latch 6 and a timing pulse generator 4 and outputting an alarm according to a detection result of the detecting means is provided.

Next, the operation of this embodiment will be described. The input analog video signal is applied to an analog / digital converter 2 via a buffer amplifier 1. Analog-digital converter 2 is quantized to 8 bits at a sampling frequency f _2, and outputs it as image data. The comparator 3 compares the quantization level of the output video data with the pedestal level. Timing pulse generator 4 based on synchronization signal
Generates a latch pulse for the pedestal section in the video signal, and supplies it to the latch 5 and the latch 6. FIG. 2 shows the timing relationship. The comparator 3 outputs “1” from the A> B terminal when the quantization level of the video data is higher than the pedestal level. When the quantization level of the video data is lower than the pedestal level, "1" is output from the A <B terminal. Similarly, the comparator 3 outputs “1” from the A> (B + α) terminal when the quantization level of the video data is higher than the pedestal level by α level or more. When the quantization level of the video data is lower than the pedestal level by α or more. “1” is output from the terminal A <(B−α). The latch 5 latches the output values of the A> B terminal and the A <B terminal at the time when the latch pulse from the timing pulse generator 4 is applied, and sends the output value to the integration circuit 7. When the input value obtained by latching the output of the terminal A> B is "1", the integrating circuit 7 outputs the negative power V.
The negative switch is turned on, the potential of the capacitor C is decreased in the negative direction through the resistor R, and when the input value obtained by latching the output of the terminal A <B is "1", the switch on the positive power supply V + side is turned on. The potential of the capacitor C is increased in the positive direction. The potential of the capacitor C is supplied to the buffer amplifier 1, and the DC offset voltage of the output of the buffer amplifier 1 is controlled in the same direction according to the level of the potential of the capacitor C.
The output of the A> (B + α) terminal of the comparator 3 and A <
The output of the (B-α) terminal is latched by the latch 6 at the same time as the latch 5, and the logical sum is formed by the OR gate 8 and output as an alarm.

[0009]

As described above, according to the present invention, even if the analog video signal being converted does not include horizontal and vertical synchronization pulses, it is possible to monitor the analog-to-digital converter for failure. There is an effect that can be done.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a waveform chart showing the operation of the embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Buffer amplifier 2 Analog-to-digital converter 3 Comparator 4 Timing pulse generator 5, 6 Latch 7 Integrator 8 OR gate

Continuation of the front page (56) References JP-A-3-35666 (JP, A) JP-A-3-60579 (JP, A) JP-A-2-131082 (JP, A) JP-A-62-29976 (JP) JP-A-62-51876 (JP, A) JP-A-1-231477 (JP, A) JP-A-49-5215 (JP, A) JP-A-2-143697 (JP, A) 3-132288 (JP, A) JP-A-1-199174 (JP, A)

Claims (1)

(57) [Claims] 1. A buffer amplifier for amplifying and outputting an analog video signal, an analog-to-digital converter for quantizing and outputting a result of sampling the output of the buffer amplifier, and an analog video output from the analog-to-digital converter Comparing means for comparing the level of the quantization level of the pedestal section of the signal with a predetermined quantization level and outputting the result of the comparison; and direct current of the output of the buffer amplifier according to the result of the comparison output from the comparing means. A video-analog-to-digital converter having an integration circuit that is a DC offset voltage control unit that controls an offset voltage, wherein the comparison unit includes a predetermined quantization level in a pedestal section of the analog video signal and a predetermined quantization level. Compare the level with two new predetermined quantization levels whose levels have been increased or decreased, and Detecting means for detecting that the quantization level of the pedestal section of the signal does not belong to the range between the two new predetermined quantization levels; and means for outputting an alarm according to the detection result of the detecting means. A video-to-analog converter.