JP2731114B2 - Electronic element and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic device and a method for manufacturing the same, and more particularly, to an electronic device which controls the shapes of openings of a conductive layer and an ohmic contact layer and has high characteristics and reliability, and a method for manufacturing the same.

[0002]

2. Description of the Related Art An inverted staggered thin film transistor (TFT) shown in FIG. 5 will be described as a conventional example of an electronic element.

[0003] A conventional TFT has a C
After an r film or the like is formed by sputtering and patterned to form a gate electrode 501 and a gate wiring 502, a gate insulating film (for example, SiNx) is formed by a plasma CVD method or the like.
503, i-type a-Si 504, and n ⁺ -type a-Si 505 are deposited.

Subsequently, using a mixed solution of HF and HNO ₃ ,
The n ⁺ -type a-Si layer and the i-type a-Si layer are etched for each element, and a conductor layer Al (containing 1 to 2% Si) is formed by sputtering.

Next, source / drain electrodes and wiring 50
6 and a channel portion 507 are formed by etching Al with a phosphoric acid-based etchant, followed by HF / HNO
Etching of n ⁺ -type a-Si is performed using the mixed solution of _three .

Finally, a passivation film is deposited by the plasma CVD method, and windows are opened on the gate wiring and the source / drain wiring to complete the fabrication of the thin film transistor.

[0007]

According to such a method, as shown in FIG. 6A, the gap 601 is formed by etching the ohmic contact layer below the end of the conductor layer by side etching of the ohmic contact layer. become.

In many cases, a TFT has a two-layer structure in which a conductive layer is provided with a barrier layer (for example, W) for preventing diffusion of Al. In this case, FIG.
As a result, a gap 602 is generated between the W layer and the ohmic contact layer.

[0009] Such a gap is formed when the multilayer film is etched, but in the past, little attention was paid to the relationship with the characteristics. However, in order to advance the development of high-density, high-characteristic electronic elements aimed at by the present inventors,
In the conventional manufacturing method, it has been found that there is a limit to further improving the characteristics, and the above-mentioned gap is related to the cause. In other words, there is a clear relationship between the gap and the TFT element characteristics, inter-element variations, and reliability. When a minute gap is formed, an element with low characteristics appears, and the variation in characteristics increases. The reliability of the system is reduced.

The present invention has been completed based on the above findings, and an object of the present invention is to provide an electronic element having high characteristics, small variations, and excellent stability over time. It is another object of the present invention to provide a method for manufacturing an electronic device capable of manufacturing such an electronic device with a high yield.

[0011]

According to the electronic device of the present invention, an opening is formed in a part of the ohmic contact layer and the conductor layer of a multilayer film comprising a semiconductor layer, an ohmic contact layer and a conductor layer, In an electronic device in which a passivation film is formed in a predetermined region including the opening,
The opening of the conductor layer has a width equal to or larger than the width of the opening of the ohmic contact layer.

In a method of manufacturing an electronic device according to the present invention, a multilayer film comprising a semiconductor layer, an ohmic contact layer and a conductor layer is sequentially laminated, and a part of the conductor layer and a part of the ohmic contact layer are etched in the same manner. A method for manufacturing an electronic device, wherein an opening is formed by continuous removal with a liquid, and then a passivation film is formed in a predetermined region including the opening, wherein the etching rate of the conductive layer is set to the etching rate. It is characterized in that an etching solution having an etching rate higher than the etching rate of the ohmic contact layer is used.

[0013]

According to the present invention, as described above, the present inventor has found that the gap formed between the conductor layer and the ohmic contact layer in the etching step has a great effect on the device characteristics, its variation and reliability. It was completed based on knowledge.

The reason that the gap portion lowers the device characteristics and reliability is considered as follows. That is, it is considered that when the gap is formed, the passivation film is hardly formed in the gap, or even when formed, only a coarse film having low density is formed, and thus the element is considered to be deteriorated.

[0015] From the measurement by the energy dispersive X-ray spectrometer, it was found that some of the passivation films formed in the gaps contained a large amount of impurities such as oxygen. It is considered that the reason for this is that the etching liquid is not completely replaced by the cleaning liquid because the gap is extremely fine, and the cleaning liquid or the etching liquid remains without completely coming out of the gap even in the subsequent drying process.

It is considered that these impurities contaminate a channel portion or the like during or after the deposition of the passivation film, thereby deteriorating device characteristics such as carrier mobility or deteriorating characteristics over time. .

On the other hand, in the present invention, the ohmic contact layer and the conductive layer are collectively and continuously etched,
Moreover, by using an etchant having an etching rate of the conductive layer higher than that of the ohmic contact layer, the opening width of the conductive layer can be made larger than the opening of the ohmic contact layer, and a gap is generated between both layers. Can be prevented. As a result, the entire inside of the opening can be covered with the dense passivation film,
A highly reliable electronic device can be obtained. Further, it is possible to prevent an etching solution, a cleaning solution, and the like from remaining in the gap, and to suppress contamination by the remaining solution. Accordingly, the mobility and other characteristics of the obtained electronic element are high and have no variation, and the yield of the electronic element is greatly improved.

In the etching of the present invention, it is preferable to use an etching solution containing at least 0.05 to 0.2 mol / l of hydrofluoric acid and 0.01 mol / l or more of halooxoacid ions. In this case, the etching rate of the conductor layer is higher than that of the ohmic contact layer, and the controllability of the etching is improved, so that the reproducibility is improved. That is, finer etching can be stably performed.

The mechanism of this etching is thought to be that the halooxoacid ions act as a strong oxidizing agent, oxidize solid surfaces such as semiconductors and metals, and then dissolve the resulting oxides in hydrofluoric acid. Therefore, even with a metal such as Al, which reacts with hydrofluoric acid, oxidation by a halooxo acid ion occurs preferentially by selecting an appropriate composition as described above, and the direct reaction between the metal and hydrofluoric acid occurs. Since generation of gas due to the reaction is also suppressed, stable etching can be performed.

The etchant having the above-described composition does not generate heat or generate gas in the reaction with a semiconductor, a metal, and a metal compound, so that a fine pattern of a semiconductor, a metal, or the like can be formed. In addition, since the resist is extremely stable with respect to the etching solution, side etching due to a decrease in the adhesion of the resist and peeling off can be suppressed, and a fine pattern can be formed. Further, since the etching solution is chemically stable, it is possible to perform stable etching for a long time as compared with other etching solutions, and it is also advantageous in terms of cost.

Therefore, it is possible to form a stable fine pattern using the same etchant even for a structure in which a metal layer, a metal compound layer, and a semiconductor layer are stacked in multiple layers. That is, the metal layer and the semiconductor layer may have a multilayer structure of two or more layers.

If the concentration of hydrofluoric acid in the etching solution exceeds 0.33 mol / l, variations in etching due to the direct reaction between metal and hydrofluoric acid are likely to occur. Since this variation affects the underlying semiconductor layer and adversely affects device characteristics, the hydrofluoric acid concentration is preferably set to 0.33 mol / l or less. Also, like an amorphous thin film transistor, i
When etching the ohmic contact layer of about several tens nm and the metal layer of about several hundred nm formed on the silicon type layer, the concentration of hydrofluoric acid is 0.33 mol / l.
If the concentration exceeds, the etching rate becomes too high with respect to the thickness, and it is difficult to stably obtain the end point.

More preferred concentration of hydrofluoric acid is
Although it changes depending on the concentration of oxo acid ions, 0.2mo
1 / l or less is preferable, and in this range, the generation of bubbles due to the direct reaction between hydrofluoric acid and the metal is further suppressed, and more uniform etching becomes possible. On the other hand, 0.05 mol / l
If the concentration is lower than this, the etching rates of the semiconductor layer and the conductive layer are significantly reduced, which is not preferable in practical use. Further, the concentration of the halooxoacid ion needs to be 0.01 mol / l or more, preferably 0.02 mol / l or more.
4 mol / l or more is more preferable. 0.01 mol / l
If the concentration is lower, the reason is unclear, but this is because abnormal etching in which the periphery of the etched portion in the semiconductor layer is extremely etched is likely to occur.
In the region where the concentration of halooxoacid ions is low, the direct reaction between Al and hydrofluoric acid is opposed to the oxidation of halooxoacid ions and the dissolution of oxides by hydrofluoric acid in metals such as Al as described above. The halooxoacid ion is preferably at least 0.02 mol / l, more preferably at least 0.04 mol / l, in order to perform a more uniform etching, since the rate at which the occurrence of the halooxoacid ion occurs increases.

[0024] When Harookiso acid ion is at a high concentration, or decrease the etching rate, and because the halogen such as I ₂ is deposited by the etching reaction, the upper limit of halo oxo ion concentration, the design of the device (the semiconductor layer, The thickness is appropriately determined depending on the thickness of the conductor layer, etc.) or the concentration of the organic solvent that suppresses the precipitation of halogen.

The halooxo acid ion of the present invention is obtained by dissolving a halooxo acid or a halooxo acid salt in water. Specific examples of halooxo acids or halooxo acid salt compounds include, for example, bromic acid (HBrO ₃ ), potassium bromate (K
BrO ₃ ), sodium bromate (NaBrO ₃ ), ammonium bromate (NH ₄ BrO ₃ ), calcium bromate (C
a (BrO ₃ ) ₂ ), magnesium bromate (Mg (BrO 3
₃ ) ₂ ), aluminum bromate (Al (BrO ₃ ) ₃ ), perbromate (HBrO ₄ ), lithium perbromate (LiBr)
O ₄ ), potassium perbromate (KBrO ₄ ), iodic acid (H
IO ₃ ), potassium iodate (KIO ₃ ), sodium iodate (NaIO ₃ ), ammonium iodate (NH ₄ I)
O ₃ ), calcium iodate (Ca (IO ₃ ) ₂ ), magnesium iodate (Mg (IO ₃ ) ₂ ), aluminum iodate (Al (IO ₃ ) ₃ ), periodate (HIO ₄ ),
Examples thereof include lithium periodate (LiIO ₄ ) and potassium periodate (KIO ₄ ). In particular, iodic acid (HI
O _3), potassium iodate (KIO _3), potassium bromate (KBrO ₃₎ is preferable easily be handled reagents. In particular, iodic acid (HIO ₃ ) does not contain a metal element that may become a contamination source of a semiconductor material, and is therefore most suitable as an etchant for a semiconductor device that is a typical electronic device.

Further, a water-soluble organic solvent such as alcohol and carboxylic acid is suitably added to the etching solution of the present invention. Specific examples of the alcohol include methanol, ethanol, isopropyl alcohol, propanol, butanol, ethylene glycol, propanediol, butanediol, and glycerin, and the organic acids include acetic acid and propionic acid. By adding an organic solvent, generated halogen such as iodine can be dissolved, etching can be performed more uniformly and stably, and the distribution of etching amount in the substrate can be suppressed. In the present invention, acetic acid or ethanol is particularly preferred. However, if the concentration exceeds 70% by volume, the resist is eroded by the organic solvent, so that the concentration is preferably 70% by volume or less.

In the etching solution of the present invention, even if it is out of the range of the above composition (hydrofluoric acid 0.05-0.2 mol / l, halooxoacid ion 0.01 mol / l or more), a water-soluble organic solvent may be used. By adding, it is possible to prevent poor etching of the deposition portion due to halogen deposition and improve the uniformity of etching.

Examples of the water-soluble organic solvent include alcohols such as methanol, ethanol, isopropyl alcohol, propanol, butanol, ethylene glycol, propanediol, butanediol, and glycerin;
Carboxylic acids such as propionic acid are preferably used. Of these organic solvents, acetic acid and ethanol are particularly preferred.

Examples of the conductor which can be suitably applied to the present invention include Al, Mo, Ni, Ta, Pt, Ti, P
Metals such as d, W, Co, and Cr, or alloys thereof, or metal compounds of these metals and semiconductors (such as silicide) are exemplified. Furthermore, the present invention is applied to those having a multilayer structure of two or more layers of these metals, alloys or metal compounds.

The semiconductor of the present invention includes Si, G
e, GaAs, GaSb, InAs, InSb, and the like, and any form of amorphous, polycrystalline, or single crystal can be applied.

In the electronic device of the present invention, the expression that the opening of the conductor layer has a width equal to or larger than the width of the opening of the ohmic contact layer means that the opening width that changes in the thickness direction of the conductor layer is the minimum value. Mean that the opening width of the ohmic contact layer, which also changes in the layer thickness direction, is equal to or greater than the maximum value.

[0032]

The present invention will be described in more detail with reference to the following examples, but the present invention is not limited to these examples.

Example 1 A 100 × 100 TFT array was manufactured according to the procedure shown in FIG. 1 by using the method for manufacturing an electronic device of the present invention.

First, a 100 × 100 mm glass substrate (Corning 7059) 100 is precision-cleaned,
A film is formed to a thickness of 100 nm by sputtering, and an etching solution (ceric ammonium nitrate: 71% HNO ₃ : H ₂₎
O = 500 g: 1900 cc: 1870 cc) and the gate electrode (electrode width 7 μm) 101
Then, a gate wiring (wiring width 5 μm) 102 was formed (FIG. 1A).

Next, SiN _{x was formed} by plasma CVD.
103, i-type a-Si 104, and n ⁺ -type a-Si 105 were deposited to 300 nm, 100 nm, and 20 nm, respectively (FIG. 1B). Table 1 shows the respective film forming conditions.

[0036]

[Table 1] Subsequently, an etching solution (HF: 0.54 mol / l, H
IO ₃ : 0.04 mol / l) and n ⁺ -type a-Si
Layer and the i-type a-Si layer were separated for each TFT element (FIG. 1).
(C)).

After forming the contact hole for the gate wiring, Al (containing 1% Si) 106 was formed by sputtering to a thickness of 250 nm (FIG. 1D).

Next, source / drain electrodes, wirings and channel portions (channel length 4 μm, channel width 6 μm)
To form 107, HF 0.1 mol / l and HIO
_The substrate was immersed in an etching solution (25 ° C.) containing 0.04 mol / l for 3 minutes to continuously etch Al and n ⁺ -type a-Si (FIG. 1E).

FIG. 2 schematically shows an enlarged cross-sectional SEM image of the channel portion after the etching. As shown in FIG. 2, no gap is observed between the Al layer and the n ⁺ a-Si layer, and it can be seen that a smooth opening is formed.

Finally, SiN _x for passivation was deposited to a thickness of 400 nm by plasma CVD, and windows were opened on the gate wiring and the source / drain wiring to complete the fabrication of the thin film transistor.

[0041] The 10 ^four TFT manufactured, the carrier mobility, threshold, ON current, and OFF current was measured to evaluate the dispersion. Further, a reliability test was performed, and the characteristics after the test were compared. Table 2 shows the results. In the reliability test, the temperature of the TFT substrate was set to 85 ° C. and the relative humidity was set to 85%.
And left for 1000 hours.

Comparative Example 1 For comparison, a thin film transistor was manufactured in the same manner as in Example 1 except that in the etching step of Al and n ⁺ -type a-Si, etching was performed individually using the following etchants. . In addition, as shown in FIG. 6A, the channel portion includes an Al layer and an n ⁺ -type a−
Gaps were observed between the Si layers.

Al; 85% phosphoric acid: 71% nitric acid: glacial acetic acid: water = 16: 1: 2: 1 (40 ° C.) n ⁺ type a-Si; 49% hydrofluoric acid: 71% nitric acid: glacial acetic acid = 1 : 60: 120 (15.2 ° C) Table 2 shows the results of the same evaluation as in Example 1 performed on the above samples.

[0044]

[Table 2] As shown in Table 2, in the TFT of this example, the mobility and the TFT characteristics were high, the variation was small, and an element having high characteristics was obtained more stably than the conventional method. Further, even under a severe environment, the characteristics hardly deteriorated, and it was found that the device was extremely reliable.

Example 2 A thin film transistor substrate for driving a liquid crystal display having 720 × 480 pixels was manufactured as shown in FIG. 3 by using the method for manufacturing an electronic device of the present invention.

First, a 100 × 100 mm glass substrate (Corning 7059) 300 was precisely washed, and then a pattern of a transparent electrode (ITO) 301 was formed. continue,
Gate electrode (electrode width 7 μm) 3
01 and the gate wiring 302 were formed (FIG. 3A).

Next, SiN _x 303, i-type a-Si 304, n ⁺ type a
-Si 305 is 300 nm, 100 nm, 20
nm (FIG. 3B).

Subsequently, an etching solution (HF: 0.54 m
ol / l, HIO ₃ : 0.04 mol / l)
The n ⁺ -type a-Si layer and the i-type a-Si layer were separated for each pixel (FIG. 3C).

After forming the contact holes for the pixel electrode and the gate wiring, W309 and Al306 are respectively
nm, 250 nm, formed by sputtering (FIG. 3
(D)).

Next, source / drain electrodes, wirings and channel portions (channel length 4 μm, channel width 6 μm)
To form HF 0.1 mol / l and HIO ₃₀ .
Immersed in an etching solution containing 04 mol / l for 7 minutes,
Al, W, and n ⁺ type a-Si were continuously etched (FIG. 3E). FIG. 4 schematically shows an enlarged cross-sectional SEM image of the channel portion after the n ⁺ -type a-Si etching.

In the conventional example, as shown in FIG.
While the layer protruded, and a gap was formed between the conductor layer and the n ⁺ -type a-Si layer, an opening that changed smoothly in the present embodiment was obtained.

Finally, 400 nm of SiN _x for passivation was deposited by the plasma CVD method, and windows were opened on the gate wiring and the source / drain wiring to complete the fabrication of the thin film transistor substrate.

The thin film transistor of Example 2 was evaluated in the same manner as in Example 1. As in Example 1, high characteristics were obtained without variation. Also, the reliability was excellent as in Example 1.

Further, a liquid crystal display was assembled using the separately prepared TFT substrate, a video signal was input, and the image was evaluated. As a result, an image with excellent contrast was displayed stably.

Example 3 In this example, a TFT substrate shown in FIGS. 7 and 8 was manufactured.

In this embodiment, a guard ring 728 electrically connecting a source terminal 719 and a gate terminal 718 as shown in FIG. 11 to prevent the transistor from being damaged by static electricity or the like generated during the process. Is provided. The guard ring is removed in the final step.

First, the structure of the TFT substrate will be described.

FIGS. 7A and 7B are schematic views showing a part of the TFT substrate of the present embodiment. FIG. 7A is a plan view, and FIGS. It is sectional drawing by the -A line, the BB line, and the CC line.

The TFT has an inverted staggered structure, and a 10 μm-wide, 100 nm-thick Cr gate electrode 712 and a gate electrode 71 are formed on a glass substrate (Corning 7059) 711.
2, a Cr gate wiring 721 for supplying a scanning signal is formed, and a gate insulating film 713 made of a silicon nitride thin film having a thickness of 200 nm is formed on the gate electrode 712 and the gate wiring 721. On the gate insulating film 713, a semiconductor active film 714 made of i-type a-Si having a thickness of 50 nm, and an A film having a thickness of 100 nm and a width of 10 μm is formed.
A source electrode 716 and a drain electrode 717 are formed. The thickness between the semiconductor active film 714 and the source electrode 716 and the drain electrode 717 is 20 nm.
Thus, an n ⁺ -type a-Si ohmic contact layer 715 doped with phosphorus is formed.

As shown in FIG. 8, a large number of such TFTs are formed on the substrate at a pitch of 100 μm vertically and horizontally. A video signal from an external video circuit is supplied to the source line 7 on the periphery of the substrate 711 on which the TFT 701 is formed.
A source terminal 719 for supplying a source electrode 716 via the gate 22 and a gate terminal 718 for supplying a scanning signal from an external scanning circuit to the gate electrode 712 via the gate wiring 721 are formed. Source terminal 7
19, Al which is the same conductor as the source electrode 716 and the source wiring 722 was used. Also, the gate terminal 718
Are formed through a contact hole 723 formed in the gate insulating film 713 on the gate wiring 721.
3 is formed of Al which is the same conductor as the source wiring 722.

The TFT 701 and the gate wiring 72
1, a protective film 727 made of a silicon nitride thin film having a thickness of 300 nm is formed on the source line 722, the source terminal 719, and the gate terminal 718.
The surface of the gate terminal 718 is partially exposed so that it can be electrically connected to the video circuit and the scanning circuit. Here, the widths Sl and Gl of the conductors forming the source terminal and the gate terminal 718 are both 50 μm,
The effective connection widths (S0 and G0) from which the protective film 727 on the source terminal and the gate terminal 718 are removed are both 42 μm. That is, the processing accuracy is 4 μm.

Next, a method of manufacturing the TFT substrate of this embodiment will be described.

First, a pixel electrode 720 made of a transparent conductive film
100n thickness on the surface of the glass substrate 711 on which
m Cr thin film was formed by a sputtering method. The surface is subjected to resist formation, mask exposure, development, etching, and resist stripping treatment to form a gate electrode 712 having a desired shape.
And a gate wiring 721 were formed. This state is shown in FIG. FIG. 9A is a schematic plan view, and FIG.
It is an AA sectional view of (a).

Next, on the surface of the substrate 711 on which the gate electrode 712 and the gate wiring 721 are formed, a gate insulating film 713 made of a 200 nm-thick SiN _x thin film and a 50 nm-thick i Type a-Si
714 and n ⁺ doped with phosphorus at a thickness of 20 nm
A type a-Si ohmic contact layer 715 was formed.

By subjecting the semiconductor active film 714 and the ohmic contact layer 715 to a photolithography process,
A semiconductor island having a predetermined shape was formed. Further, a gate insulating film 713 on the pixel electrode 720 and the gate wiring 721
Was formed with a contact hole 723. This state is shown in FIG. FIG. 10A is a schematic plan view, and FIG.
FIG. 10B is a sectional view taken along line AA of FIG.

Subsequently, an Al thin film having a thickness of 100 nm is formed on the substrate 711 including the ohmic contact layer 715 by 1%.
It was formed by a sputtering method using a Si-containing Al target. A resist film 724 was formed on the surface of the Al thin film, exposed and developed using a predetermined mask, and the Al and ohmic contact layers were etched in the same manner as in Example 1. As shown in FIG. 11, a source electrode 716, a source wiring 722, a source terminal 719, a drain electrode 717, a guard ring 728 for electrically connecting the source terminal 719 and the gate terminal 718, and further a gate terminal 71.
8, as well as a channel 726. At this time, the conductor was processed to form the gate terminal 718 so that the gate wiring 721 below the contact hole 723 was completely covered with the Al wiring. FIG. 11A is a schematic plan view, and FIG. 11B is a sectional view taken along line AA of FIG.

In this embodiment, as shown in FIG. 11, the ohmic contact layer 715 is
To source wiring 722, source terminal, guard ring 72
8, the gate terminal 718, the gate wiring 721 and the gate electrode 712.
8, the surfaces of the gate wiring 721 and the gate electrode 712 are made of a gate insulating film 713 or an
2 and the conductors forming the source wiring 722, the source terminal, and the guard ring 728 are all covered with a resist film 724 which is an insulator. That is, the ohmic contact layer 715
All the conductive members electrically connected to are covered with an insulator. Therefore, the ohmic contact layer 715
When an etchant serving as an electrolyte acts on the ohmic contact layer 715, the ohmic contact layer 715 does not form a battery with another conductor, and the ohmic contact layer 715 is not abnormally side-etched due to the battery effect.
As described above, when the ohmic contact layer is etched, the layer electrically connected to the ohmic contact layer is covered with the insulator, whereby side etching due to the battery effect can be prevented.

Next, a protective film 727 made of a silicon nitride thin film
Was formed, and a resist film formation, mask exposure, development, etching, and resist peeling treatment were performed on the surface to expose the source terminal and the gate terminal 718. Here, since the gate terminal 718 is formed above the gate insulating film 713, it can be formed only by removing the protective film 727 similarly to the source terminal. Further, the guard ring 728 connecting the gate wiring 721 and the source wiring 722 was removed to form the TFT substrate shown in FIG.

As described above, when the TFT is placed on the substrate 711,
A large number of substrates are formed in a vertical and horizontal direction at a pitch of 00 μm.
In the peripheral portion of the semiconductor device 11, a source terminal for supplying a video signal from an external video circuit to the source electrode 716 via the source wiring 722, and a scanning signal from the external scanning circuit are gated via the gate wiring 721. A TFT substrate on which a gate terminal 718 for supplying to the electrode 712 is formed is formed.

[0070]

According to the present invention, it is possible to provide an electronic device having high characteristics, small variations, and high reliability. The present invention is suitably applied particularly to an electronic device having a large number of devices such as TFTs required to operate at high speed and requiring uniformity of the characteristics.

Further, the manufacturing method of the electronic device of the present invention simplifies the manufacturing process and increases the yield as compared with the related art, so that the manufacturing costs of various electronic devices can be reduced.

[Brief description of the drawings]

FIG. 1 is a schematic view illustrating a manufacturing process of a TFT substrate of Example 1.

FIG. 2 is a diagram schematically showing an SEM image of a channel portion.

FIG. 3 is a schematic view illustrating a manufacturing process of a TFT substrate for a liquid crystal display of Example 2.

FIG. 4 is a cross-sectional view schematically showing an SEM image of a channel portion.

FIG. 5 is a schematic sectional view showing a conventional TFT.

FIG. 6 is a diagram schematically showing an SEM of a channel portion of a conventional TFT.

FIG. 7 is an enlarged schematic view illustrating a part of a TFT substrate according to a third embodiment.

FIG. 8 is a conceptual diagram illustrating a TFT substrate according to a third embodiment.

FIG. 9 is a schematic view illustrating a process for manufacturing a TFT substrate of Example 3.

FIG. 10 is a schematic view showing a step of manufacturing a TFT substrate of Example 3.

FIG. 11 is a schematic view showing a step of manufacturing a TFT substrate of Example 3.

[Explanation of symbols]

100, 300, 500 glass substrate, 101, 301, 501 gate electrode, 102, 302, 502 gate wiring, 103, 303, 503 SiN _x , 104, 304, 504 i-type a-Si, 105, 305, 505 n ⁺ Type a-Si, 106, 306, 506 Al, 107, 307, 507 Channel, 308 ITO, 309 W, 310 contact hole, 601, 602 gap, 701 TFT, 711 glass substrate, 712 gate electrode, 713 gate insulating film 714, a semiconductor active film made of i-type a-Si, 716 source electrode, 717 drain electrode, 718 gate terminal, 719 source terminal, 721 gate wiring, 722 source wiring, 715 n ⁺ type a-Si ohmic contact layer, 720 pixels Electrodes, 723 contacts Hole, 724 resist film, 726 channel, 727 protective film, 728 guard ring.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Satoshi Miyazawa 1-7 Yukiya Otsukacho, Ota-ku, Tokyo Alps Electric Co., Ltd. (72) Inventor Yasuhiko Kasama 1-7 Yukitani-Otsukacho, Ota-ku, Tokyo (72) Inventor Tadahiro Omi, Miyagi Prefecture, Sendai City, Aoba Ward, Yonegabukuro 2-1-17-1 301 (72) Inventor Matagoro 7, 227 Kaiyamacho, Sakai City, Osaka Prefecture Hashimoto Chemical Co., Ltd. (72) Inventor Hirohisa Kikuyama 7,227 Kaiyama-cho, Sakai-shi, Osaka Prefecture Inside (72) Inventor Jun Takano 7-227, Kaiyama-cho, Sakai-shi, Osaka Prefecture Inside Hashimoto Chemical Co., Ltd. (72) Inventor Miyashita Masayuki 7-227, Kaiyama-cho, Sakai-shi, Osaka, Japan (72) Inventor Tatsuhiro Yabune 7,227, Kaiyama-cho, Sakai-shi, Osaka, Japan (56) References -245226 (JP, A)

Claims (12)

(57) [Claims] An opening is formed by sequentially laminating a multilayer film composed of a semiconductor layer, an ohmic contact layer, and a conductor layer, and continuously removing a part of the conductor layer and the ohmic contact layer with the same etchant. Then, a method for manufacturing an electronic device in which a passivation film is formed in a predetermined region including the opening, wherein the etching solution includes:
A method for manufacturing an electronic device, comprising using an etchant having an etching rate of the conductor layer equal to or higher than an etching rate of the ohmic contact layer. 2. The method according to claim 1, wherein the semiconductor layer is made of amorphous silicon. 3. The method according to claim 1, wherein the opening is a channel of an inverted staggered thin film transistor. Wherein said etching solution is in solution, hydrofluoric acid and the general formula (XO _n) ^p- (where, X is halogen, n represents 3, 4 or 6, p is 1 or Each of the halooxo acid ions represented by 3) is 0.05 to 0.3
The method for manufacturing an electronic device according to claim 1, wherein the amount is 3 mol / l and 0.01 mol / l or more. 5. The method according to claim 4, wherein the halooxo ion is an iodate ion (IO ₃ ¹⁻ ). 6. The method according to claim 4, wherein the etching solution contains a water-soluble organic solvent. 7. The method according to claim 6, wherein the water-soluble organic solvent is acetic acid or ethanol, and its concentration is 70% by volume or less. 8. The method according to claim 1, wherein the ohmic contact layer is obtained by adding an impurity to a semiconductor layer. 9. The method according to claim 8, wherein the impurity is phosphorus or boron. 10. The conductive layer is made of Al, Mo, Ni,
The method for manufacturing an electronic device according to claim 1, comprising a metal of Ta, Pt, Ti, Pd, W, Co, or Cr, or an alloy or a metal compound of the metal. 11. The method according to claim 10, wherein the conductor layer has a multilayer structure of two or more layers made of the metal and / or the alloy and / or the metal compound. . 12. An electronic device manufactured by the method for manufacturing an electronic device according to claim 1. Description: