JP2727952B2 - Semiconductor integrated circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device having a bipolar transistor and a field-effect transistor suitable for a high-speed and low-power-consumption system.

[0002]

2. Description of the Related Art By forming a bipolar transistor and a MOS transistor on the same semiconductor substrate and combining these transistors in a circuit, a high-performance VLSI having the characteristics of the bipolar and the MOS can be realized. This composite technology is a Bi-CMOS (Bipolar-C
This is called OMOS (OMOS) technology and is applied to VLSI such as memories and gate arrays. FIG. 3 shows a typical example of a circuit for realizing these VLSIs. FIG. 3 shows Bi-C
This is an example of a MOS inverter circuit. As shown in the figure, the output section is formed by totem poles of NPN bipolar transistors 120 and 121, and the input section is formed by a MOS transistor. The output section bipolar transistor is driven by the input section MOS transistor. Configuration. The features of this circuit are that the input section is composed of MOS transistors, so that the input impedance is very high, and that the bipolar transistors in the output section operate complementarily by the MOS transistors, so that DC current does not flow and power consumption is very low. It is small, and the load driving force is high because the output section is formed of a bipolar transistor. Therefore, the Bi-CMOS circuit has a circuit configuration suitable for a VLSI having both high speed and low power consumption.

[0003] In the case of this circuit example, the output unit is a well-known TTL (Transistor-Transistor Logi).
The power supply voltage is TTL, as can be seen from the totem pole connection used in c) and that the input section has a CMOS (Complementary MOS) configuration.
It is 5 V like CMOS and CMOS. Of course, the Bi-CMOS VLSI, which is not limited to the example shown in FIG. 3 but is currently applied, such as a memory or a gate array, operates at a power supply voltage of 5V.

There are many documents relating to these Bi-CMOS technologies. For example, JP-A-59-11034, JP-A-59-176624, JP-A-60-27227, and
5 MICRON BICMOS TECHNOLOGY ”(1987 IEDM, pp83
8 to 840).

FIGS. 63 and 64 show another circuit which combines bipolar and CMOS to achieve high speed and low power consumption.
The following circuit is known (JP-A-61-84112). Each is an inverter circuit. The basic operation will be described. The same parts are denoted by the same reference numerals. Input 30
When 8 is at "0" level, a PMOS transistor (PMOS)
300 is turned on, and a base current is supplied to an NPN transistor (hereinafter abbreviated as NPN) 303. So NPN
303 turns on. Also, an NMOS transistor (NMOS) 30
1 turns off, the base current to NPN 304 is not supplied, and NPN 3
04 turns off. Therefore, the output 309 becomes "1" level. On the other hand, when the input 308 becomes “1” level, PM
OS 300 is turned off, no base current is supplied to NPN 303, and NPN 303 is turned off. Also, NMOS 301
Is turned on, and since the NMOS 302 whose output level (in this case, “1”) is input to the gate is still in the on state, the base current is supplied to the NPN 304 and the NPN 304 is turned on. Therefore, the output 309 becomes "0" level. When the output 309 becomes "0" level, the NMOS 302 is turned off, so that the base current to the NPN 304 is cut off, and low power consumption characteristics can be aimed at. However, the circuit of FIG.
When output 309 falls, ie, input 308 rises, NP
When N303 turns off, there is no element to lower the base potential of NPN303. For this reason, the timing of the ON state of the NPN 303 and 304 occurs without the NPN 303 being turned off promptly,
A through current flows from the V _CC power supply 180 to the GND power supply 181, which hinders low power consumption and high speed. FIG. 64 improves this point. By providing the NMOS 305, the NM which is turned on when the input 308 rises
Through OS305, the base current of NPN303 is rapidly reduced,
NPN303 is turned off quickly. Impedance element Z inserted between base and emitter of NPN304
The reference numeral 306 and the resistor 307 reduce the base current to the GND potential when the NPN 304 is turned off.

[0006]

SUMMARY OF THE INVENTION Conventional Bi-CMOS
There are two points to be improved in the system / circuit technology, the first relates to the circuit characteristics (power consumption) and the withstand voltage at a power supply voltage of 5 V, and the other relates to the circuit configuration. Hereinafter, these two technical problems will be described.

Conventionally, the Bi-CMOS circuit shown in FIG. 3 has been used under a power supply voltage of 5V. However, the following problems have arisen with advances in miniaturization technology. That is, the first is a problem of power consumption, and the second is a problem of withstand voltage of the element. As miniaturization advances, the number of transistors formed on one chip naturally increases. Assuming that the power consumption per circuit is constant, the power consumption increases in proportion to the degree of integration. For example, assuming now that the integration degree is 20,000 gates / chip and the power consumption per chip is 5 W, if the miniaturization advances and the integration degree becomes 40,000 gates / chip, the power consumption per chip becomes 10 W Becomes As is clear from such a simple calculation, when the power consumption per circuit is constant, the power consumption per chip increases in proportion to the increase in the degree of integration accompanying miniaturization. When power consumption increases,
Since the temperature in the chip rises and the characteristics and reliability of the transistor deteriorate, it becomes necessary to cool the transistor. In the case of several watts or less, a fan for air cooling is required, and when the power consumption exceeds that, a water cooling facility is required. The equipment required for cooling these chips is ultimately manifested as an increase in cost and an increase in the size of the product, resulting in a reversal in the direction of the VLSI technology, such as a reduction in the cost and size of the product. As miniaturization progresses and the degree of integration increases, the problem of the increase in power consumption is coming to the surface.
Therefore, it is becoming necessary to reduce the power consumption of the Bi-CMOS circuit. On the other hand, another problem with miniaturization is
This is a problem of the withstand voltage of the element. Since the current miniaturization is performed under a constant power supply voltage, the electric field intensity applied to the element is increasing, and accordingly, the deterioration of the element characteristics or the dielectric breakdown is becoming a problem. It is necessary to realize a Bi-CMOS system that solves the problems of power consumption and withstand voltage due to miniaturization. The second problem relates to the circuit configuration. It will be described below that it is difficult to reduce the power consumption by optimizing the circuit constant without deteriorating the high-speed switching characteristics in the conventional circuit shown in FIG.

First, the circuit operation will be described with reference to FIGS. The input voltage 162 shown in FIG.
Is applied, when the input terminal 162 is initially High, the PMOS 100 is off, the NMOSs 110 and 115 are on, and the NMOS 114 is off. Here the input goes from high to Lo
When it changes to w (low), the PMOS 100 is turned on and the NMOS 115 is turned off, so that a base current is supplied from the PMOS 100 to the bipolar 120 and the 120 is turned on. On the other hand, since the NMOS 110 is turned off, the bipolar 121 is turned off.
65 goes high. At this time, the NMOS 114 is turned on, the base and the emitter of the bipolar 121 are short-circuited, and the bipolar 121 is reliably turned off. Next, when the input changes from low to high
PMOS 100 turns off, NMOS 115 turns on, and bipolar 12
Since the base potential of 0 is lowered, the bipolar 120 is turned off. On the other hand, the NMOS 110 is turned on to supply a base current to the bipolar 121, so that the bipolar transistor 121 is turned on and the output 16
5 becomes low. At this time, the NMOS 114 changes from on to off. Immediately after the NMOS 110 is turned on, the NMOS 114 is also turned on. However, since the on-resistance of the NMOS 114 is designed to be larger than the on-resistance of the 110, the current from the NMOS 110 is applied not only to the NMOS 114 but also to the base of the bipolar 121. Is also supplied, and 121 is turned on. This circuit is a low power consumption type circuit because the bipolars 120 and 121 perform complementary operations. However, in a transient state where the switching between the 120s and 121s is performed, a through current flows from the power supply 160 to the ground 161 so that power consumption increases. I do. Therefore, in order to reduce power consumption, it is necessary to switch the bipolars 120 and 121 at high speed to minimize the through current.
For example, when input 162 changes from low to high, bipolar 120 switches from on to off. In order to increase the speed of this operation, the channel width W of the NMOS 115 is increased and the ON resistance of the NMOS 115 is reduced.
It is necessary to reduce the base potential of the bipolar 120 at high speed. On the other hand, when the input changes from high to low, in order for this circuit to operate at high speed, it is necessary to supply a base current from the PMOS 100 to the bipolar 120 at high speed in order to turn on 120 at high speed. For this purpose, it is necessary that the current from the PMOS 100 does not leak to the NMOS 115 and is supplied to the base of the transistor 120 at all. However, in a transition state where the input 162 changes from high to low, the PMOS 100 and the NMOS 115
Are turned on at the same time, a part of the current of the PMOS 100 leaks to the NMOS 115. Therefore, in order to reduce the leakage of the current, it is necessary to increase the on-resistance of the NMOS 115, that is, to design the channel width W of the NMOS 115 to be small. As described above, in the conventional circuit shown in FIG. 3, it is necessary to design the channel width of the NMOS 115 to be large and to turn off the bipolar 120 at a high speed to reduce the through current in order to reduce the power consumption. Therefore, it is necessary to design the channel width of the NMOS 115 small in order to reduce the base leakage current. In other words, contradiction arises when trying to simultaneously achieve low power consumption and high speed. It is necessary to overcome this limitation and provide a circuit configuration that simultaneously achieves low power consumption and high speed of the circuit.

According to the above prior art, the increase in power consumption due to the through current of the circuit accounts for a large proportion of the power consumption of the entire circuit. That is, the power consumption overhead due to the through current cannot be ignored. Therefore, it is necessary to suppress the through current. In the above prior art, the connection between the NMOS transistors (NMOS) 301 and 302 for driving the NPN bipolar transistor 304 is not particularly considered, and the following problem arises. This problem will be described with reference to FIGS. 65 and 66. As shown in FIG. 65, the junction A of the NMOS 301 and 302 has a junction capacitance 310 of the drain or source of the NMOS. Also, NP
Around the base of N304, there is a parasitic capacitance 311 such as a base capacitance or a junction capacitance of the NMOS 302. FIG. 66 shows the operation timing and the on / off states of the NMOS 301 and 302. It is divided into five regions from I to V. Region I is input 308
Is at the “0” level, and the output 309 is set at the “1” level. At this time, the NMOS 301 is off and the NMOS 302
Is on, the potential at point A and the base potential of NPN 304 are both GND potentials. The area II is a state where the input 308 rises and the output 309 starts to fall.
At this time, the NMOS 301 and 302 are turned on, and the potential at the point A becomes N
It rises with a time constant determined by the on-resistance of the MOS 301 and 302. Also, the base potential of NPN 304 increases, and NPN 304 is turned on. Region III is a state where the input 308 is at the “1” level and the output 309 is at the “0” level. At this time, the NMOS 301 is on and the NMOS 302 is off. The potential at the point A becomes V _CC -V _th , where the threshold voltage of the NMOS 301 is V _th . The base potential of the NPN 304 attenuates the time constant of the resistor 307 and the parasitic capacitance 311 to the GND potential. region
IV is the state where input 308 falls and output 309 begins to rise. At this time, both the NMOS 301 and the NMOS 302 are turned off, the state of the potential at the point A in the region III is maintained, and the base potential of the NPN 304 continues to decrease with the same time constant as the region III. In the area V, the input 308 is at the “0” level,
There is a state where the output 309 is at the “1” level. At this time,
NMOS 301 is off, and NMOS 302 is on. The potential at the point A attenuates toward the GND potential, but the base potential of the NPN 304 once increases and then attenuates toward the GND potential. This is because the charge that has been charged in the
When the OS 310 is turned on, the charge is distributed to the parasitic capacitance 311. For this reason, NPN3
03 is turned on, at the time of the timing that NPN304 is turned off, NPN304 does not turn off, GND from the V _CC power supply 180
Through current is generated toward the power supply 181. Due to this through current, power consumption increases, and the charging current of the load by the NPN 303 escapes to the NPN 304, which hinders the high speed operation.

The problem of the prior art shown in FIG.
S100 and 110 are turned on and the bipolar transistor 12
Attempts to supply a base current of 0,121, but the base potential does not reach the base-emitter voltage V _{BE of the} bipolar transistor until the charging is completed because there is a contributing capacitance around the base. It is in.

An object of the present invention is to provide a semiconductor integrated circuit having a bipolar transistor and a field-effect transistor which are high speed and consume low power.

Another object of the present invention is to provide a semiconductor integrated circuit device which satisfies an optimum relationship between power consumption and breakdown voltage.

Another object of the present invention is to provide a semiconductor integrated circuit device which sufficiently satisfies low power consumption and high speed.

Another object of the present invention is to provide a semiconductor integrated circuit device which sufficiently suppresses a through current.

Another object of the present invention is to reduce the time required for the base potential of the bipolar transistor to reach the base-emitter voltage V _BE .

[0016]

In order to reduce the power consumption and avoid the problem of the withstand voltage, the power supply voltage is reduced to 5.0 V of the conventional power supply.
This is achieved by lowering the power supply voltage, for example, to 4 V. This is, of course, not limited to the power supply voltage of 4 V, but an appropriate power supply voltage is selected in view of the performance region required by the system. Therefore, the first object is achieved by using a power supply voltage lower than 5.0 V and satisfying the required performance. This will be described below with reference to FIG. FIG. 5 shows a Bi-CM represented by FIG.
4 is a graph showing characteristics of an OS gate circuit. The horizontal axis indicates power consumption per gate, and the vertical axis indicates gate delay time. The operating frequency and the load capacity are constant, and the characteristics when the power supply voltage is changed are shown. Power supply voltage from 3V to 3.5V, 4
As the voltage increases to V, the power consumption slightly increases, and the gate delay time decreases significantly. When the power supply voltage is further increased from 4 V to 4.5 V and 5 V, the power consumption greatly increases,
The gate delay time will be slightly smaller. Like this, Bi-
The delay time of the CMOS gate circuit strongly depends on the power supply voltage in the region of about 3 V to 4 V. When the power supply voltage is increased beyond that, only the power consumption increases, and the delay time does not decrease so much, but asymptotically. It shows a tendency to approach a certain value. Therefore, for example, even if the power supply voltage is reduced from about 5 V to about 4 V, it is possible to keep the increase in the delay time small and greatly reduce only the power consumption. For example, the shaded area shown in FIG. 5 is a performance area required by a certain system.

The Bi-CMOS circuit is connected to a power supply voltage of 5
When used at V, the delay time performance is satisfied, but the power consumption is large and the required conditions are not satisfied. The required performance range is a range where the power supply voltage is around 4V. In such a case, the Bi-CMOS circuit is connected to, for example, the power supply voltage 4.
The required performance can be satisfied by using V. The idea of using a Bi-CMOS circuit at a power supply voltage lower than 5 V becomes apparent only when the degree of miniaturization and the degree of integration are significantly increased, and the characteristics of the Bi-CMOS circuit shown in FIG. 5 are analyzed. Doing so will reveal that possibility. In addition, at a power supply voltage lower than 5 V, B
In the case of using an i-CMOS circuit, the voltage applied to each transistor constituting the circuit is reduced, so that it is possible to avoid a problem with respect to the withstand voltage of the element, which is a concern due to miniaturization.

Next, the second object, that is, the realization of a Bi-CMOS circuit configuration capable of reducing power consumption while maintaining high speed will be described with reference to FIGS. FIG. 5 shows that the power consumption of the Bi-CMOS circuit can be reduced by lowering the power supply voltage without deteriorating the high-speed performance. However, the characteristics are limited by the curve shown in FIG. To achieve higher speed and lower power consumption at the same time is a conventional Bi-C
As described above, it is impossible with a MOS circuit.
The present invention provides a circuit configuration capable of simultaneously realizing high speed and low power consumption. FIG. 2 is a circuit showing the principle of FIG. 1, and FIG. 2 shows its operation. In FIG. 1, reference numeral 192 denotes a bipolar transistor (bipolar) having a collector and an emitter connected between a power supply 160 and an output 165;
The FET 194, which is an OS type field effect transistor, has a power supply 167.
And the gate of bipolar 192 is connected to input 162. Further, a current bypass element 190 serving as a first potential difference reducing element and an FET 195 are connected in series between the base of the bipolar 192 and the terminal 168.
The gate of 95 is connected to input 162. Bipolar 19
The collector and emitter of 3 are connected between output 165 and power supply 161, FET 196 is connected to the bases of terminals 169 and 193, and the gate is connected to input 162. A current bypass element 191 serving as a second potential difference reducing element is connected between the base of bipolar 193 and power supply 168. FIG. 2 shows an example of the operation in such a circuit configuration. The FETs 194 to 196 turn on and off according to the change in the input voltage, and the current bypass elements 190 and 191 turn on and off with a certain delay from the change in the output voltage. The bipolar transistors 192 and 193 switch according to ON / OFF of the FETs 194 to 196 and the current bypass elements 190 and 191. For example, when the input voltage is high, FE
T194 is off, and FETs 195 and 196 are on. The current bypass element 190 turns off the output row, and 191 turns on. When the input voltage changes from high to low, FE
T194 turns on, and FETs 195 and 196 turn off. Since the current bypass elements 190 and 191 switch with a certain delay from a change in the output voltage, the initial state is maintained and 190 is off and 191 is on. FET 194 is on,
Since the current bypass element 190 is off, a base current is supplied from the power supply 167 to the bipolar transistor 192, and the bipolar transistor 192 is turned on. On the other hand, since the FET 196 is off and the current bypass element 191 is on, the bipolar transistor 193 is turned off.
Is off. Therefore, the output changes from low to high (state II). After the output voltage changes, the current bypass element 190 changes from off to on with a certain delay time.
Reference numeral 91 changes from on to off (state III). Next, when the input voltage changes from low to high, the FET 194 turns off, and FE
T195 and 196 are turned on. At this time, the current bypass element 1
Since 90 is on, the base potential of bipolar 192 drops through 190 and 195 and 192 turns off.
On the other hand, since the FET 196 is on and the current bypass element 191 is off, the base current is supplied to the bipolar transistor 193 from the terminals 169 to 196, the 193 turns on, and the output changes from high to low (state IV). With a certain delay time after the output voltage changes, the current bypass element 190 is turned off, and the current bypass element 191 is turned on (state V). The point that the above-described circuit configuration and operation are characterized in comparison with the conventional circuit is that the element 190 serving as the base current extraction of the bipolar transistor 192 has at least an output voltage V _out and V _out > V _CC −V _BE . It is off until it becomes. Here, V _CC indicates a power supply voltage, and V _BE indicates a base-emitter voltage of the bipolar transistor 192. Further, the element 191 serving as a base current extraction of the bipolar transistor 193 is turned off at least until the output voltage _Vout becomes _Vout > _VGND + _VBE . Here, V _GND is the voltage of the power supply 161. The object of the present invention is achieved by a circuit configuration having such features.

Another object of the present invention to sufficiently suppress the shoot-through current is to use a totem pole connection of an NPN transistor as an output stage, and connect an upper NPN transistor to a PM
The OS is a so-called Darlington connection, and the base current of the lower NPN transistor is connected to the _Vcc power supply and turned off when the output falls, and between the MOS and the base of the lower NPN transistor. This is achieved by supplying via a connected NMOS.

Another object of the present invention is to shorten the time required for the base potential of the bipolar transistor to reach the base-emitter voltage B _BE , as shown in FIG. 74. 314 and 319, and the other terminal of the switch element is biased so that the base potential does not exceed the base-emitter voltage V _BE .

[0021]

A description will now be given, with reference to FIGS. 1 and 2, that the above-described circuit configuration and operation achieve the second object of the present invention. First, B
In order to reduce the power consumption of the i-CMOS circuit, it is necessary to reduce a through current flowing from the power supply 160 to the power supply 161 when the bipolar transistors 192 and 193 are switched. For this purpose, for example, when the output voltage falls, the bipolar 192 must be turned off at a high speed. To quickly turn off the 192, the base current can be quickly bypassed by making the on-resistance of the base current bypass element 190 and the FET 195 of the 192 sufficiently small. When the output falls (state IV), the current bypass element 19
0 is on, and if the on-resistance of 190 is designed to be sufficiently small, the base current can be extracted and 192 can be turned off at high speed. When the output voltage rises, bipolar 193 must be turned off at high speed. 19
In order to turn off the base current at high speed, the on-resistance of the second base current bypass element 191 of 193 should be sufficiently small to quickly bypass the base current. By the way, when the output rises (state II), the current bypass element 191 has already been turned on, and the current bypass element 193 has been turned off in advance. 191 turns off 193 after seeing the output voltage fall sufficiently. Thus, the first and second current bypass elements 19
By designing the on-resistances of 0 and 191 to be sufficiently small, the bipolar transistors 192 and 193 can be turned off at a high speed at the time of switching or turned off in advance of the switching, thereby achieving low power consumption. On the other hand, to increase the speed, the first current bypass element 190 is off, for example, when the output rises (state II). Therefore, the base current supplied from the FET 194 to the bipolar transistor 192 is all supplied to the base of the first current bypass element 190 without leaking to the first current bypass element 190 at all. In other words, no matter how small the on-resistance of the current bypass element is designed to reduce power consumption,
When the bipolar transistor 192 changes from off to on (state II), the current bypass element 190 is off and is in an ideal state where the impedance is extremely high without being affected by the on resistance. At the time of output falling (state IV), the current bypass element 191 is off, and the base current supplied from the FET 196 to the bipolar transistor 193 does not leak to the current bypass element 191 at all and is applied to the base of 193. Supplied. As with the current bypass element 190, no matter how much the on-resistance of the 191 is designed, when the bipolar transistor 193 is turned on, the 191 is off and is in an ideal state with extremely high impedance.

As described above, in the configuration of the circuit of the present invention,
Since the design for low power consumption can be performed independently of the high speed, the low power consumption and high speed can be performed simultaneously, and the second object of the present invention is achieved.

The base current of the lower NPN transistor to which the totem pole is connected is the MOS transistor connected to the _Vcc power supply.
Strongly supplied through. This is because the voltage between the drain and the source of the MOS can be substantially applied by V _CC -V _BE irrespective of the output potential. However, V _BE is the base of NPN
This is the forward voltage between the emitters. Thereby, the lower N
Since the PN transistor is driven strongly, the delay of the fall delay time can be reduced. After the output has fallen, the base current is cut off, so that power consumption can be reduced. Further, by connecting the MOS for blocking the base current to the _Vcc power supply,
As shown in FIG. 6, when the output rises, it is possible to prevent the lower NPN transistor from being turned on due to the distribution of electric charges, so that a through current can be reduced and power consumption can be reduced.

Another configuration for achieving the above object will be described with reference to FIGS. 74 and 75.

FIG. 76 shows an example of the concrete circuit of FIG. Reference numerals 303 and 318 in FIG. 74 correspond to 117, 103 and 118 in FIG. 76, respectively.

These are controlled by 152 and 150 in FIG. 76, respectively. To explain the contents of this control, when the input changes from high to low level, the driver PMOS tries to turn on and the driver NMOS tries to turn off.
03 (D ₁ ) is in the off state, and the switch element 318 is (D ₂ )
D ₁ and D ₂ are controlled to be turned on. As a result, the drain current of the driver PMOS flows to the base terminal without leakage. In addition, since 318 (D ₂ ) is on, the bipolar transistor 121 is cut off. If the input changes from low to high, the driver PMO
S tries to turn off and the driver NMOS tries to turn on. In this period, D ₁ and D ₂ are controlled so that the switch element 303 (D ₁ ) is on and the switch element 318 (D ₂ ) is off. I do. As a result, the bipolar transistor 121 is turned on, and the bipolar transistor 1 is turned on.
20 turns off.

As described above, the switch element connected to the base is operated to be turned on when the bipolar transistor is to be turned on and off when the bipolar transistor is to be turned on.

Next, another switch element D ₅ (314), D
₄ One terminal of (319) is connected to the terminals 168 and 170 having a fixed potential not exceeding the base-emitter voltage V _BE of the bipolar transistor, so that the base potential quickly rises to the base-emitter potential V _BE . Move to raise. In other words, when the input changes from high to low level, the parasitic capacitance around the base of the bipolar transistor 120 is charged by the drain current of the driver PMOS 100. At this time, the base of the NPN 120 already has the D
₅ (314) biased to a fixed potential below V _BE . Therefore, NPN 120 can be turned on at high speed. On the other hand, when the input changes from low to high level, the switch element 319 (D ₄ ) is in the ON state, so that the base of the bipolar transistor 121 is connected to D ₄
Beforehand is biased to a fixed voltage lower than V _BE . Therefore, NPN 121 can be turned on at a high speed.

[0029]

FIG. 6 shows an embodiment of the first invention. FIG. 6 shows a general configuration of a computer, which is connected via a bus 244 to a central processing unit CPU (Central Processing Unit).
), A memory for storing data input to the CPU and / or data output from the CPU, a memory controller, and an i / o processor. In this system, for example, taking a CPU as an example, a gate circuit used in the CPU is required to have high-speed performance in order to perform calculations at high speed. Further, when the CPU is divided into several chips, a signal passes between chips, so that a delay time required for input / output is added. In order to reduce the overhead required for the input / output, it is necessary to reduce the signal crossing between chips and eliminate the delay required for the input / output. For this purpose, FIG.
Is to be integrated on a single semiconductor substrate as much as possible on a chip, thereby increasing the degree of integration. That is, the system shown in FIG. 6 is a typical example in which high speed and low power consumption are simultaneously required. The required performance of this system is
For example, it is a shaded area shown in FIG.
-CMOS circuits consume large power and are not suitable for this system. Therefore, the power supply voltage is reduced to 4 V in order to operate in the performance region indicated by oblique lines. 5V Bi-CMOS
Although the circuit satisfies the delay time requirement, it consumes large power and cannot construct the system shown in FIG. When the power supply voltage is lowered to 4 V, the required performance is satisfied in both the delay time and the power consumption. Therefore, the system shown in FIG.
Can be realized by a Bi-CMOS circuit described in detail below.

FIG. 7 shows a data processing device in which a processor using a Bi-CMOS circuit, a RAM, a ROM, and a timer are connected to a bus 244. As shown, the bus 24
4 is connected to a RAM, a ROM, and a timer, and has a large bus load capacity. Therefore, the processor is Bi-C
It is necessary to use a MOS circuit and drive the bus at high speed. However, in the case of the present system, it is necessary to lower the power supply voltage in order to satisfy the required performance as in the case of FIG. Here, the power supply voltage is not limited to 4 V, but may be, for example, 3.3 V or lower, for example, 5 V such as 2.5 V, 1.5 V, or the like.
A future reference voltage of less than V.

When the system shown in FIG. 7 is constituted by a Bi-CMOS circuit described in detail below, an optimum design may be obtained.

The necessity of using a power supply voltage lower than 5 V will be described below. First, in a TTL (transistor-transistor logic circuit), a future power supply voltage is set to 3.3V.
There is a plan of ± 0.3V (ISSCC'86 Tech. Dig. P2
24). In order to match the TTL with the signal level and provide compatibility, the power supply voltage of the Bi-CMOS must also be adjusted to 3.3V ± 0.3V. By doing so, the TTL can be reduced without level conversion of the signal.
Interface with the server. In another example, EC
When configuring a mixed system of L and Bi-CMOS,
When the power supply voltage of the Bi-CMOS is made equal to the power supply voltage of the ECL, the power supply system is unified into one and the usability is good. E
A mixed system of CL and Bi-CMOS may be formed on an on-chip or a plurality of chips. In any case, the power supply circuit and the power supply wiring are simplified by unifying the power supply system. Can be realized. The power supply voltage of the ECL is -4.5 V ± 10% for the 100K series, for example. Normally, the power supply of the ECL takes a potential in the negative direction from GND.
CMOS also operates with a negative power supply of -4.5V ± 10%. However, as seen in the pseudo-ECL example, the ECL can be operated at a positive power supply potential. In this case, the Bi-CMOS can also operate with the positive power supply. Absolute value of power supply potential difference | 4.
At 5V ± 10% |, it is possible to unify the power supply potentials of ECL and Bi-CMOS, and to simplify the power supply system. Further, for example, Bi-CMOS and NTL (Non-Thr
eshold Logic). E above
The mixed system of CL and Bi-CMOS is for incorporating the high logic capability and high speed of ECL into the Bi-CMOS system, and the mixed system of NTL and Bi-CMOS is
This is mainly to take advantage of the high speed of NTL. These ECL
And NTL are high-speed but have high power consumption.
By using an i-CMOS circuit, a high-speed system with low power consumption can be configured. NTL
Usually uses a power supply of 2V ± 10%. Therefore, Bi
-The power supply for the CMOS is also made common by setting the power supply of the CMOS to 2 V ± 10% common to the NTL.

Further, for example, a dry battery may be used as a power supply. It operates at 1.5V ± 10% for one battery, 3.0V ± 10% for two batteries in series, and 4.5V ± 10% for three batteries in series. Dry batteries have low noise and are small, and are highly advantageous as future power sources.

FIG. 61 shows the characteristics of the Bi-CMOS gate of the present invention. The horizontal axis is the power supply voltage, and the vertical axis is the gate delay time. As can be seen from the characteristics shown here,
The gate delay time increases rapidly below about 4V. Therefore, the voltage region where the Bi-CMOS gate is operated at high speed and the influence of the power supply variation is relatively small is 4 V or more. On the other hand, as miniaturization advances, physical constraints on devices,
For example, the power supply voltage must be reduced due to constraints such as punch through, gate dielectric breakdown, and hot electron effect. Further, since the power consumption changes with the square of the power supply voltage, the lower the power supply voltage is, the better the power consumption is. In particular, complicated logic such as a microprocessor needs to mount many functions on a chip and operate at high speed, and low power consumption is an important factor in system design. Therefore, in the case of the present embodiment, it is conceivable that the power supply voltage variation of the gate delay time is relatively small and as low as possible, for example, the power supply voltage is 4 V ± 10%.

FIG. 62 shows an example of the signal level when any of the above power supply potentials is used. The inside of the chip is supplied to an output circuit using a signal of a power supply full swing. The output circuit converts the full swing signal into an ECL signal and outputs it to the outside of the chip. The input circuit receives the ECL signal, performs level conversion, outputs a full swing signal, and operates the internal circuit. By using a full-swing signal inside the chip, the leakage current of the next-stage gate can be eliminated and low power consumption can be achieved. In particular, in the case of a low-voltage power supply, the MO
In many cases, the threshold voltage of the S transistor is lowered to increase the current drivability. Therefore, it is necessary to make the input signal full swing to reduce the leakage current due to the MOS. Also,
High-speed, low-noise signal propagation is performed between chips by using a small ECL amplitude level. in this way,
Inside the chip, using the signal of the power supply voltage full swing,
By using an ECL signal between chips, a low-voltage power supply system with high speed and low power consumption can be configured.

FIG. 8 shows an inverter circuit according to an embodiment of the present invention. 120 The collector V _CC power source 160, and the abbreviated as NPN transistors or less NPN emitter is connected to the output terminal 165, 121 to the collector output terminal 165, be a NPN transistor whose emitter is connected to the GND terminal 161 , 100 the source V _CC power source 160, to the base of the drain NPN120, PMOS transistor (hereinafter having a gate connected to the input terminal PMOS
110, an NMOS transistor (hereinafter abbreviated as NMOS) having a drain connected to the output terminal 165, a source connected to the base of the NPN 121, and a gate connected to the input terminal 162;
103 is a PMOS having a source connected to the base of the NPN 120 and a drain connected to the output terminal 165;
In the base of 121, the NMOS whose source is connected to the GND terminal 161 and the input terminal 150 is connected to the output terminal 165,
The output terminal is connected to the gates of PMOS103 and NMOS114.
It is a MOS inverter.

Next, the operation will be described with reference to FIG. First, in state I, the input voltage is high, so PMOS 100 is off, NMOS
110 is on. At this time, since the output 165 is low, the output 242 of the inverter 150 becomes high,
3 is off and NMOS 114 is on. Next, when the input voltage changes to low and enters the state II, the NMOS 110 is turned off and the PMOS 10 is turned off.
0 turns on to supply the base current, and NPN 120 turns on. At this time, since the output 242 of the inverter is kept high, the PMOS 103 is off and the NMOS 114 is on. NPN 121 is off. In region II, the output voltage V _out
Rises to V _out = V _CC -V _BE . Here, V _CC is the power supply voltage (hereinafter referred to as V _CC ), and V _BE is the base voltage of the NPN.
It is an emitter-to-emitter voltage (hereinafter referred to as V _BE ). When entering the state III, the output 242 of the inverter 150 is inverted to low,
The NMOS 114 turns off, the PMOS 103 turns on, and the output voltage V _out
To V _out = V _CC . Next, when the input voltage is inverted from low to high and enters the state IV, the PMOS 100 is turned off and the NMO
S110 is turned on to supply a base current to NPN121, and NPN121 is turned on. At this time, since the output 242 of the inverter is kept low, the PMOS remains on and the NMOS 114 remains off. The output voltage V _out drops to V _out = V _GND + V _BE . Here, V _GND is a ground potential, and is hereinafter referred to as V _GND . Finally, in state V, the output 242 of inverter 150
Is inverted to high, the PMOS 103 is turned off, the NMOS 114 is turned on, and the output voltage V _out falls to V _out = V _GND .

According to this embodiment, when the PMOS 100 supplies the base current to the NPN 120, the PMOS 103 is off, so that the PM
The drain current of OS100 is supplied without exception as the base current of NPN 120, and NPN 120 can be turned on at high speed (state II). In this state, the MOS 114 is turned on, and NP
Since the base of N121 is grounded to GND, NPN 121 is turned off in advance at the time of state II, that is, when the output rises, and no through current flows. When the output falls (state I
In (V), since the NMOS 114 is off, the drain current of the NMOS is supplied to the NPN 121 without any leakage, and the NPN 121 can be turned on at high speed. At this time, the PMOS103 is on
The base and emitter of the NPN 120 are short-circuited, and the NPN 120 is off. Therefore, no through current flows. As described above, in this embodiment, when the NPN 120 and the NPN 121 are turned on, the PMs serving as the respective base current extracting elements
Since the OS 103 and the NMOS 114 are off, the NPN can be turned on in an ideal state. In a Bi-CMOS circuit of a type in which an output of an NPN totem pole connection is driven by a MOS, how quickly the base current of the NPN is extracted,
Turning off the PN at high speed to reduce the through current is a key factor in reducing power consumption. For this purpose, it is necessary to design the impedance of the NPN at the time of extracting the base current to be small. On the contrary, when the NPN is turned on, the base current escapes to the extraction element. Therefore, in the conventional Bi-CMOS circuit, power consumption increases when the base current extracting element is designed to have a high impedance to increase the speed, and conversely, when the base current extracting element is designed to have a low impedance and the power consumption is designed to be low, the operation speed decreases. There was a fundamental problem. However, this embodiment solves this problem. That is, even if the on-resistance of the PMOS 103 and the NMOS 114, which are base current extracting elements, is designed to be sufficiently small to reduce power consumption, when the NPN is turned on, the respective extracting elements 103 and 114 are off and have a high impedance. In state. Therefore, low power consumption design can be performed without deteriorating high-speed performance.

FIG. 9 shows an embodiment in which the concept similar to that of the inverter of FIG. 8 is expanded to a three-input NAND circuit. In the inverter of FIG. 8, PMOS 101 and 102 are connected in parallel with 100, and N
MOSs 111 and 112 are connected in series to 110. The operation is easily understood from the example of the inverter, so that the description is omitted here. In addition to this embodiment, a k-input NAND circuit can be generally configured.

FIG. 11 shows an embodiment in which the concept similar to that of the inverter of FIG. 8 is expanded to a three-input NOR circuit. In the inverter of FIG. 8, PMOS 101 and 102 are connected in series to 100, and NMOS 111 and 112 are connected in parallel to 110. The operation can be easily understood from the example of the inverter, so that the description is omitted here. In addition to the present embodiment, a k-input NOR circuit can be generally configured.

FIG. 12 shows an embodiment in which the same concept as the inverter of FIG. 8 is developed to a three-state inverter circuit.
8, the PMOS 101 is connected in series to 100, the NMOS 111 is connected in series to 110, the transfer gate 240 is connected in parallel to the PMOS 103, and the NMOS 115 is connected to the NMOS 114.
, The input of the CMOS inverter 153 is connected to the enable terminal 166, and the output thereof is connected to the PMOS 111 and the NMOS gate of the transfer gate 240.
66 is the PMOS of NMOS111 and transfer gate 240
Connected to gate. The operation is performed by the enable terminal 166.
Is high, the PMOS 101 and NMOS 111 are on, the transfer gate 240 and NMOS 115 are off, and the inverter operates in the same manner as the inverter of FIG. On the other hand, when a low signal is input to the enable terminal 116, the PMOS 10
1, NMOS 111 is off, transfer gate 240, NMOS 11
5 turns on, NPN 120 and 121 turn off, and output terminal 165
Is in a high impedance state.

FIG. 13 shows an example of the configuration of a latch circuit using the inverter of this embodiment. Transfer gate 241 and C
NOS inverter 154 and Bi-CMCOS inverter 159 are connected in series, and transfer gate 240
The input terminal of the CMOS inverter 153 is connected between the output terminal of the CMOS inverter 153 and the input terminal of the transfer gate 241.
The output of 153 is connected to the PMOS gate of 241, and the output of 153 is connected to the transfer gate 241.
Is connected to the input terminal 162, and a Bi-CMOS
The output of the inverter 159 is connected to the output terminal 165, and the NMOS gate of the transfer gate 241 is connected to the latch pulse terminal 167. Latch pulse terminal 167
, A high signal is input, data is written into the circuit from the input terminal 162. When a low level is input to the latch pulse terminal, writing is prohibited, and previously written data is held.

FIG. 14 shows another embodiment of the present invention. FIG.
The following elements are added to the inverter circuit of FIG. That is, the NMOS 113 is connected in parallel with the PMOS 103, the input terminal of the CMOS inverter 151 is connected to the output terminal 242 of the CMOS inverter 150, and the output terminal is connected to the gate of the NMOS 113.

FIG. 16 shows the operation. The difference from the inverter of FIG. 8 is that the NMOS 113 is turned on and off at the same timing as the PMOS 103. The addition of the NMOS 113 enhances the base current extraction of the NPN 120. That is, the source voltage V _S becomes V _S = V _G + V _thp ,
PMOS 103 turns off. Here, the V _G gate voltage of PMOS, V _thp is the PMOS threshold voltage. V _G =
0 So That V _S = V _thp, and the base voltage of NPN120 does not decrease to less than V _thp. Then NMOS113
Is added, the base voltage of the NPN 120 can be reduced to GND equal to the output voltage. If the base pull-out is enhanced by adding the NMOS 113 as in this embodiment, lower power consumption can be achieved. Also, when NPN120 turns on,
NMOS 113 is off, so even if 113 is added, N
The PN is turned on in an ideal state, and the speed is not impaired.

FIG. 15 shows an example in which the concept similar to that of the inverter of FIG. 14 is developed to a three-input NAND circuit. The method of development is the same as when the inverter of FIG. 8 is developed to the 3NAND of FIG. The operation is easily understood from the operation of the inverter shown in FIG.

FIG. 17 shows an example in which the concept similar to that of the inverter of FIG. 14 is expanded to a three-input NOR circuit. The method of deployment is the same as when the inverter of FIG. 8 is deployed in 3NOR of FIG. The operation is easily understood from the operation of the inverter shown in FIG.

FIG. 18 is an example in which the same concept as in FIG. 14 is developed for a three-state inverter circuit. The deployment method is
This is the same as the inverter of FIG. 8 expanded to the three-state inverter of FIG. The operation is easily understood from the twelfth three-state inverter.

FIG. 48 shows NPN120 and NPN1 of the circuit of FIG.
The resistors 140 and 14 are connected between the base and the emitter of 21 respectively.
This is a circuit to which 1 is added. The reason why the resistor is inserted between the base and the emitter of the NPN is as follows. As is clear from the description of the operation of the inverter circuit in FIG. 14, in the 3NAND circuit in FIG.
There is a state where 102 is off and PMOS 103 and NMOS 113 are off. At this time, the base of NPN 120 is in a floating state. If noise enters the input terminal 164 connected to the gate of the PMOS 100 and the PMOS 100 is turned on for a moment, the power supply 100 sends N
Current flows to the base of PN120. Since the base of the NPN 120 is in a floating state, there is no escape path for the base current. Therefore, the NPN 120 is turned on, and a through current flows from the emitter of the NPN 120 to the GND 161 via the NMOSs 110, 111, 112, 114 to increase power consumption. In the worst case, the circuit malfunctions. If the resistor 140 is inserted between the base and the emitter of the NPN 120 as shown in FIG.
Bypassing the current that is going to flow from 100 to the base of NPN 120, NPN 120 will not turn on. Here, of course, the resistor 140 is set to a sufficiently high resistance value so as not to adversely affect the rising characteristics of the circuit. Similarly, FIG.
In, the NMOSs 110 and 111 are on, but the NMOSs 112 and 114 are off, and the base of the NPN 121 may be in a floating state. At this time, when noise enters the input 164 and the NMOS 112 is momentarily turned on, a current flows from the output 165 (high level) to the base of the NPN 121 via the PMOS 110, 111, 112, and the NPN 121 is turned on. Then the current 1
60 through PMOS100, PMOS103 and NMOS113, NPN1
As a result, a through current flows through the ground 161 to increase the power consumption, or in the worst case, the circuit malfunctions. As shown in FIG. 48, if the resistor 141 is connected between the base and the emitter of the NPN 121, the current due to noise is bypassed and the NPN 121 is not turned on. Here, the resistor 141 is the resistor 14
Similar to 0, the resistance is set to a sufficiently high value so as not to deteriorate the circuit characteristics. As described above, by connecting the resistor between the base and the emitter of the NPN 120, 121, the reliability of the circuit can be improved. This method can be applied to the same type of circuit including the inverter circuit of FIG. 14 and the 3NOR circuit of FIG.

FIG. 19 shows another embodiment of the present invention. FIG.
The following elements are added to the inverter circuit of FIG. That is, the drain of the NMOS 115 is connected to the base of the NPN 120, the drain of the NMOS 116 is connected to the source of the NMOS 115,
The source of the NMOS 116 is connected to the GND power source, the output of the CMOS inverter 150 is connected to the CMOS inverter 151,
The output is connected to the gate of the NMOS 115. The operation is shown in FIG.
As shown in FIG.

The feature of this embodiment is that the base is grounded to GND via the base current extracting NMOSs 115 and 116 in the inverter of FIG. It is possible to turn off the NPN 120 faster by simply pulling it to GND instead of simply shorting between the base and emitter of the NPN 120.

FIG. 20 shows an example of application to the 3NAND, FIG. 22 shows an example of application to the 3NOR, and FIG. 23 shows an example of application to the 3-state inverter. The deployment method and operation can be easily understood from the above embodiment.

FIG. 24 shows another embodiment of the present invention. FIG.
The following elements are added to the fourth embodiment of the inverter. That is, the drain of the NMOS 110 and the output terminal 165 of FIG.
The drain of 119 is connected to the output terminal 165, the source is connected to the drain of the NMOS 110, and the gate is connected to the output of the CMOS inverter 243. The operation of this embodiment is shown in FIG. The feature of this embodiment is that the NMOS 119 is turned off when the output rises (state II in FIG. 26), thereby preventing the emitter current of the NPN 120 from leaking from the NMOS 110 to the base of the NPN 121. This makes it possible to speed up the rise of the output.

FIG. 25 is an example of application to 3NAND, FIG. 27 is an example of application to 3NOR, and FIG. 28 is an example of application to a state inverter. The deployment method and operation can be easily understood from the above embodiment.

FIG. 29 shows another embodiment of the present invention. FIG.
In this embodiment, the NMOS 116 is added to the circuit. The drain of the NMOS 116 is connected to the base of the NPN 120, the source is connected to GND, and the gate is connected to the input terminal 162. As the operation is easily understood from FIG. 31, this embodiment is different from the above-described embodiment in that the base current of NPN 120 is set to NMOS 1 when the output rises.
It leaks through 16. This idea is contrary to the gist of the present invention. However, since the NMOS 116 is added as an auxiliary to the base extraction PMOS 103, it is designed to be extremely small and the leakage of the base current is also extremely small. Further, the output fall is the same as in the embodiment of FIG. Therefore, the gist of the present invention of eliminating leakage of the base current is utilized. Rather, the base current extraction of the NPN 120 is assisted by the NMOS 116 and the NPN 120 is turned off at a high speed, so that the effect of reducing power consumption is great.

FIG. 30 is an example of application to the 3NAND, FIG. 32 is an example of application to the 3NOR, and FIG. 33 is an example of application to the 3-state inverter. The deployment method and operation can be easily understood from the above embodiment.

FIG. 34 shows a circuit in which a resistor 140 is additionally connected between the base and the emitter of the NPN 120 in the circuit shown in FIG. The reason for connecting this resistor is to prevent the base of the NPN 120 from being in a floating state, to improve the reliability of the circuit, and to assist the base current extracting PMOS 103 of the NPN 120. For example, input 102 is high, output 105
Is low, PMOSs 100 and 103 are off. Therefore, the base of NPN 120 is in a floating state. At this time, noise enters the input 102 and the PMOS 100
Is momentarily turned on, the NPN 120 is turned on and a through current flows to the output section. By connecting the resistor 140 between the base and the emitter of the NPN 120, the current of the PMOS 100 due to noise can be bypassed, and the NPN 120 does not turn on. It is important that the value of the resistor is set to a sufficiently high value so as not to deteriorate the rising characteristic of the circuit.

FIG. 35 shows an example of application to the 3NAND of this embodiment, FIG. 36 shows an example of application to the 3NOR, and FIG. 37 shows an example of application to the 3-state inverter.

FIG. 38 shows another embodiment of the present invention. This embodiment is different from the above-described embodiment in that there is no PMOS between the base and the emitter of the NPN 120. Therefore, the high level of the output is V _out = V _CC -V _BE . The operation is understood from FIG. FIG. 39 shows the development of this embodiment to 3NAND, and FIG.
1 is a development to 3NOR, and FIG. 42 is a development to a 3-state inverter. FIG. 43 is similar to FIG.
The gate input position 118 is changed. Due to the change of the input position, the speed can be increased depending on the use condition.

FIG. 44 is obtained by adding a resistor 141 to FIG. The reason for connecting the resistor is to prevent the base of the NPN 120 from being in a floating state as described with reference to FIG. 34, and to prevent a circuit malfunction due to noise.

FIG. 45 shows a cross-sectional structure when the circuit shown in FIG. 44 is formed on a Si substrate. P on P board
Well and N-well layers are formed, and NMO
Form S, PMOS, NPN and resistor. Each element is connected to each other by a fine metal wiring layer, but here, for simplicity, a tangential relationship is indicated by a solid line. The metal wiring layers are not limited to a single layer, but are connected by a multilayer wiring layer such as a second layer and a third layer which are electrically separated from each other by an insulating layer as necessary. A large number of such structures are formed on the same silicon substrate, and they are connected to each other by, for example, the second and third metal wiring layers to constitute one system or a part thereof.

FIG. 46 is an example of a planar layout pattern of the circuit shown in FIG. In this embodiment, the base current extracting MOS and the feedback inverter are placed at the center of the cell,
PMOS and NMOS for NPN drive are arranged above and below, and NPN is arranged above and below. Since such a layout is a vertically long cell, a large number of channels of different wiring layers running on the cell in the horizontal direction can be obtained, so that the layout is suitable for, for example, a gate array. On the other hand, FIG. 47 shows an example of a planar layout pattern of the circuit of FIG. 44, in which an NPN, a pull-out MOS, a feedback inverter and the like are arranged like an NPN drive PNOS and an NMOS. Since the cell of this type can have the same height as the CMOS cell, for example, one Bi-CMOS cell can be placed in several CMOS cells, and the ratio of the number of CMOS cells to the number of Bi-CMOS cells Can be freely selected. In this way, a Bi-CMOS cell is arranged only in a necessary portion, and a design with higher integration can be realized. Therefore, the cell of this embodiment is suitable for, for example, a standard cell type LSI.

FIG. 49 shows an inverter circuit according to an embodiment of the present invention. The circuit operation is shown in FIG. The feature of this circuit resides in that the output falls with a PNP transistor. Since the PNP transistor is turned on when the base potential becomes lower than the output potential by V _BE (base-emitter voltage of the bipolar transistor), the output falls at a high speed. 50 shows an example in which this embodiment is applied to a 3NAND circuit, FIG. 52 shows an example applied to a 3NOR circuit, and FIG. 53 shows an example applied to a tristate circuit.

FIG. 54 is characterized in that the fall of the output is performed by a PNP transistor, as in the previous embodiment. However, this embodiment does not use a feedback inverter, and performs a full swing of the output amplitude by a resistor. That is, the resistance 1
40 raises the output signal to the power supply potential through the PMOS 100, and the resistor 130 lowers the output signal to the ground potential through the NMOS 110. As described above, the reason why the present embodiment is fast when the output amplitude is fully swinged by the resistor is as follows.
The point is that the bases of NPN 120 and PNP 130 are driven by different beta ratios. PMOS driving NPN120
The threshold voltage of the CMOS section constituted by 100 and the NMOS 115 is set high, and conversely, the PMOS 104 and the N
The threshold voltage of the CMOS section constituted by the MOS 110 is set low. As a result, the bipolar transistors 120 and 130 start to turn off at the beginning of each change of the input voltage, so that the NPN 120 and the PNP 130 can be turned on at a high speed, respectively. FIG. 55 is an example in which the inverter of this embodiment is applied to a 3NAND circuit, and FIG.
FIG. 58 shows an example of development to a NOR circuit, and FIG. 58 shows an example of development to a tristate circuit. FIG. 56 shows the operation timing of the inverter shown in FIG.

FIG. 59 shows the Bi-CMO of the present invention shown in FIG.
By connecting the S inverter and the CMOS inverter in series,
Preferably, it is an example of being integrated on a single semiconductor substrate. Since the output of the circuit of the present invention swings full, the next stage CMOS
No leakage current flows through inverter 153.

FIG. 60 shows an example in which the Bi-CMOS inverters of the present invention are connected in series and preferably integrated on a single semiconductor substrate. Also in this case, since the output of the circuit of the present invention has a full swing, no leakage current flows to the next-stage Bi-CMOS gate.

As shown in the above two embodiments, the full swing of the output signal from the power supply is an important characteristic for reducing the power consumption because the leakage current of the next stage gate is eliminated. In particular, as the voltage of the power supply decreases in the future, there is a high possibility that the threshold value of the MOS will be lowered. The reason is to improve the current driving capability of the MOS. When the threshold value of the MOS is lowered and the output signal amplitude of the gate is smaller than the power supply voltage, M
When the OS is turned on, a leakage current flows and power consumption increases, and a noise margin of input / output signals is reduced. Therefore, when the power supply voltage is reduced, it is an important characteristic that the output signal fully swings to the power supply level as in the circuit of the present invention.

Hereinafter, another embodiment of the present invention will be described with reference to the drawings.

FIG. 67 shows an inverter circuit according to another embodiment of the present invention. 315 collector V _CC power supply terminal 18
0, an NPN whose emitter is connected to the output terminal 326,
316: collector is output terminal 326, emitter is GND
The NPN, 319 has a source V _CC power source terminal 180 connected to the power supply terminal 181, the base of the drain NPN315,
A PMOS whose gate is connected to the input terminal 325, 320
NM has a drain connected to the base of NPN 315, a source connected to GND power supply terminal 181, and a gate connected to input terminal 325.
OS, 317 to drain V _CC power source terminal 180, the drain of source NMOS318, NMOS, 318 whose gates are connected to the output of the CMOS inverter 321 to the source of drain NMOS 317, the base of the source NPN316,
NMOS 322 whose gate is connected to the input terminal 325
And 321 are CMOS inverters inserted between the output terminal 326 and the gate of the NMOS 317, and 323 and 324 are resistors inserted between the base and emitter of the NPN 315 and 316, respectively.

Next, the operation will be described. FIG. 68 shows the operation timing and the ON / OFF states of the PMOS 319 and the NMOSs 320, 317, 318. The description will be made by dividing into five regions from I to V.

In the area I, when the input 325 is at the "0" level,
The output 326 is set to the “1” level.
At this time, since PMOS 319 is on and NMOS 320 is off, NPN3
The base of 15 is the V _CC potential. After rapidly rises to V _CC -V _BE potential motion of the output 326 NPN315, resistor 323
To the _Vcc potential. On the other hand, since the NMOS 317 is on but the NMOS 318 is off, the base current of the NPN 316 is cut off, the base potential of the NPN 316 becomes the GND potential via the resistor 324, and the NPN 316 is off.

Region II is a state where the input 325 rises, the output of the inverter 321 is at the "1" level, and the output 326 is falling. At this time, PMOS 319 is off and NMO
Since S320 is on, no base current is supplied to NPN 315 and the base potential drops to GND potential, so NPN 315 is off. On the other hand, NMOS317, 318 is because it is on, strong base current is supplied from the V _CC power source 180 to NPN316. Therefore, NPN 316 is turned on and output 32
6 is at the “0” level. In this embodiment, from the region I
When moving to II, charge distribution occurs as described with reference to FIG. In other words, the electric charge charged in the parasitic capacitance at the connection between the NMOSs 317 and 318 turns on the NMOS 318.
It is distributed to increase the base potential of NPN316. However, since this timing is when the NPN 316 is turned on, this phenomenon works well for turning the NPN 316 on rapidly.

In the area III, the input 325 is at the “1” level, the output 326 is at the “0” level,
1 is at the “0” level. At this time, since PMOS 319 is off and NMOS 320 is on, NPN3
The 15 base potential is the GND potential, and the NPN 315 is off. On the other hand, since the NMOS 317 is turned off, the supply of the base current to the NPN 316 stops, and the NPN 316 is turned off. But NP
Since N315 is also off, the output 326 holds the "0" level.

Region IV is a state where the input 325 falls, the output of the inverter 321 is at the "0" level, and the output 326 is rising. At this time, PMOS 319 is on,
Since the NMOS 320 is turned off, a base current is supplied to the NPN 315, and the NPN 315 is turned on. On the other hand, NMOS 317, 318
Are off, so NPN 316 remains off. Therefore, the output 326 becomes "1" level.

The area V is the same as the area I.

According to this embodiment, the bipolar base current is strongly supplied by the MOS current, and after the bipolar is activated, the supply of the base current is stopped. Therefore, a bipolar / CMOS composite inverter having high-speed and low power consumption characteristics is provided. You can also get a circuit. In addition, since the configuration has been configured to eliminate the adverse effect due to the distribution of electric charges, which has been a problem in the related art, high-speed characteristics with lower power consumption are obtained. In addition, CMOS for delay
Two inverters 321 and 322 are inserted, as shown in FIG. 68, in order to keep the NMOS 317 on until the output 326 drops sufficiently. For example, if the NMOS 317 is turned off before the output 326 has fallen sufficiently, the supply of the base current to the NPN 316 will not be sufficient, causing an increase in delay time and instability of the output level. Therefore, depending on the device constant, it is necessary to further increase the number of delay inverters, or the delay inverters may not be required. When a delay inverter is required, it is effective to reduce the channel width of the MOS and to make the channel length L larger than the minimum value of the process in order to reduce the occupied area.

[0076] Further, the resistor 323 is obtained by inserting in bring to "1" level of the output 326 to V _CC level is not required if the output of the "1" level good V _CC -V _BE . If the resistor 323 is provided, the NMOS 320 may be removed. The resistor 324 sets the base potential of the NPN 316 to the GND potential when the NPN 316 is in the off state, and may use other means. For example, the NMOS may have a gate connected to the output 326 or to the base of NPN 315, a drain connected to the base of NPN 316, and a source connected to the emitter of NPN 316.

In this embodiment, the NMOS 317 is used to cut off the base current of the NPN 316, but it can be replaced with a PMOS. However, in that case, the inverted signal of the output 326 is
It must be applied to the gate of the PMOS. The same applies to the following examples.

FIG. 69 is developed into a three-input NAND circuit based on the same concept as the inverter circuit shown in FIG. The same parts are denoted by the same reference numerals. Parts having the same functions are denoted by A, B, and C after the numbers in FIG.
Having described the inverter circuit of FIG. 67 in detail,
Those skilled in the art who understand CMOS circuits will easily understand the operation. Although the present embodiment has been described by taking a three-input NAND circuit as an example, the present invention can be applied to a general k-input NAND circuit such as two-input or four-input.

FIG. 70 is expanded to a three-input NOR circuit based on the same concept as the inverter circuit shown in FIG. The same parts are denoted by the same reference numerals. Parts having the same function are denoted by A, B, and C after the numbers in FIG.
Having described the inverter circuit of FIG. 67 in detail,
Those skilled in the art who understand CMOS circuits will easily understand the operation. In the present embodiment, a three-input NOR circuit has been described as an example, but the present invention can be applied to a general k-input NOR circuit such as two-input or four-input.

FIG. 71 is developed into a three-state inverter circuit based on the same concept as the inverter circuit shown in FIG. The same parts are denoted by the same reference numerals. The increasing element is the CM connected to the enable terminal 335.
OS inverter 330, NMOS 331 connected in series with NMOSs 317 and 318, PMOS 332 connected in series with PMOS 319, NMOS 333 connected in series with NMOS 320
, A transfer gate 334 connected between the base and the emitter of the NPN 315, and an NMOS 336 connected between the base and the emitter of the NPN 316.

Next, the operation will be described.

First, when the enable terminal 335 is at the "1" level, the NMOS 331, PMOS 332, and NMOS 333 in the current path among the above-described increasing elements are all on, and the base-emitter between the NPN 315 and 316 is turned on. , The transfer gate 334 and the NMOS 336 are turned off. Accordingly, the circuit is electrically the same as the inverter of FIG. 67, and functions as an inverter circuit.

On the other hand, when the enable terminal 335 is at "0" level, the above ON / OFF state is reversed. Therefore, the base and emitter of NPN 315 and 316 are short-circuited and the base current supply path is also cut off.
6 is off. Also, from the output terminal 326, the V _CC terminal 1
Since the path to 80 or the GND terminal 181 is also cut off, a high impedance state is set.

A latch circuit can be formed using the inverter circuit of the present invention. That is, although the latch circuit is shown in FIG. 13, the Bi-CMOS inverter circuit shown in FIG.
The inverter circuit shown by 7 may be used.

As described above, the inverter circuit, NAND circuit, M
Although the explanation has been made by taking the OR circuit, the three-state circuit, and the latch circuit as an example, the NPN is an N with a Schottky barrier diode.
A PN transistor may be used. Further, as can be seen from the above, the present invention can be applied to all circuits that can be configured by CMOS. Further, since the feedback inverters 321 and 322 do not require a speed, it is possible to use a normal LDD (Lightly Doped Drain) MOS, and to use other MOSs with an asymmetric LDD structure. The circuit of the present invention can be mixed with a CMOS circuit and has high speed and low power consumption, so that it can be applied to a large-scale, high-performance gate array LSI, a data processing device, and the like. In addition, even if the power supply voltage is reduced, the reduction in speed is small, and it can be said that the circuit is suitable for a fine process. FIG. 72 shows an inverter circuit according to another embodiment of the present invention. The control of the upper NPN 315 is shown in FIG.
The control of the lower NPN 316 uses the circuit of FIG. 67.

FIG. 73 shows an inverter circuit according to another embodiment of the present invention. Figure 3 shows the control of the upper NPN 315
8 and the control of the lower NPN 316 uses the circuit of FIG.

In addition to the above, various combinations of circuits are possible, and these are also included in the scope of the present invention. It is obvious that the present invention is not limited to the inverter circuit.

Further, the base bias element shown in the present invention can be added to various circuits, for example, a circuit as shown in FIG.

An embodiment of the present invention will be described below with reference to FIGS.

FIG. 76 is obtained by adding the following elements to the circuit shown in FIG. That is, a drain connected to NMOS114 the base of NPN120, the source lower than V _DE
Connect to a fixed potential terminal 168 higher than GND, connect the gate to the input terminal 162, and connect the drain of the NMOS 119 to the NPN 12
At the base of 1, the source is connected to a fixed potential terminal 169 below V _{BE and} above GND, and the gate is connected to the output terminal 105.

FIG. 77 shows an operation time chart of the inverter logic gate according to the embodiment.

First, considering the case where the input 162 (a) changes from high to high level, the output 165, the first-stage feedback inverter 150, and the last-stage feedback inverter 152 are shown in FIG.
Outputs such as 7 (b), (c) and (d) are obtained. Here, as shown in (e), the driver NMOS 100 is turned from off to on by the fall of the input 162, and the driver NMOS 110 is (f).
The state changes from ON to OFF as shown in FIG.

In this transition period, the PMOS 103 and the NMOS 117
Is turned off at least until the output 165 becomes sufficiently high as shown in (g) and (i), and the NMOS 114 is turned off in synchronization with the input.
The leakage of the base current of No. 20 is kept small. A base bias voltage (for example, 0.4 V) set so as not to exceed the base-emitter voltage V _BE is applied to the NMOS 11 in advance.
4, the parasitic capacitance around the base is charged up to 0.4V in advance,
The time for the base potential to reach V _BE is accelerated.

On the other hand, the bipolar NPN transistor 12
With regard to 1, the NMOS 118 is turned on in advance, so that the accumulated charge in the base can be discharged. Since the NMOS 119 is off, the base bias voltage is not applied, and the bipolar transistor 121 is cut off.

Next, when the input 162 changes from low to high, the driver NMOS 110 changes from off to on, and the driver PMOS 100 changes from on to off. During this transition period, the NMOS 118 is turned off in advance, and
The NMOS 119 is turned on in advance, and the base of the NPN 121 is 0.4 V in advance. The bipolar transistor 121 is turned on when the base reaches V _BE (about 0.8 V). That is, it is usually necessary to raise the base from 0 V to 0.8 V. However, in the circuit of FIG. 76,
By providing the terminal 169, the base voltage becomes 0.4
Since the voltage is at V, the bipolar transistor can be turned on simply by raising the voltage from 0.4 V to 0.8 V. Therefore, NPN 121 can be turned on at high speed. For the bipolar transistor 120, the PMOS 103 and the NMOS 117
Is turned on in advance, and is kept on at least until the output 165 becomes sufficiently low level. NMOS114
Is turned on in synchronization with the input 162. The charge stored in the base and the charge stored in the parasitic capacitance around the base are
It is discharged via 117. Even when the NMOS 114 is turned on, the bipolar transistor 120 is not turned on because the base bias voltage does not exceed V _BE .

FIG. 78 shows another embodiment of the present invention, in which a three-input NAND gate is shown as an example of development into a multi-input logic gate. The difference from the embodiment of FIG. 76 is that driver PMOS 101 and driver
111 and 112 and switch NMOSs 115 and 116 are added in series.

FIG. 79 shows, in another embodiment of the present invention, a three-input NOR as an example of expansion to another logic function among examples of expansion to a multi-input logic gate. The difference from the embodiment of FIG. 76 is that the driver PMOSs 100, 10
1 and 102 are connected in series, and the driver NMOSs 110, 111, 1
12 and the switch NMOS 114, 115, 116 are connected in parallel.

FIG. 80 shows another embodiment of the present invention, which shows a clocked inverter (three-state inverter) among other logical functions.

The structure is the same as that of the embodiment shown in FIG. 76 (inverter).
Clock enable input 166, enable input inverting inverter 153, NMOS300, NMOS301, PMOS107, NMO
S302 and a transfer gate 240 are added. When the enable input 166 is set to the high level, this circuit performs the same operation as the inverter of FIG. On the other hand, when the enable input 166 is set to the high level, the transfer gate 240 and the NMOS 302 are turned on, and the NPNs 120 and 12 are turned on.
1 turns off. Also, the NMOS 300 turns off, and eventually the output 1
65 becomes high impedance.

[0100]

According to the present invention, since the voltage applied to the circuit is low, the withstand voltage condition of the element is satisfied. Further, since the power consumption becomes lower in proportion to the square of the voltage, several times more circuits can be integrated on one chip as compared with the related art. As a result, the delay due to the signal passing between the chips is reduced, and the speed of the system can be increased. Further, since the power consumption is small, the calorific value is small, the cooling equipment is simplified, and the cost can be reduced. In addition, all the advantages associated with the high integration can be utilized.

According to the present invention, when the output-stage bipolar is turned on, the base current extracting element is off and in a high impedance state, so that there is no leakage of the base current and the bipolar can be turned on at high speed. Can be. Therefore, the base current extraction element is designed to be large enough,
Even if the power consumption is reduced, the high-speed operation is not impaired. Further, the output voltage can be made to have the full amplitude of the power supply at a high speed via the extraction element.

According to the present invention, a high-speed, low-power-consumption, large-scale semiconductor integrated circuit device including a field-effect transistor and a bipolar transistor can be obtained.

Further, according to the present invention, the base potential of the bipolar transistor is biased in advance to a fixed voltage (for example, 0.4 V) lower than the base-emitter voltage V _{BE and} higher than the GND potential. It is possible to turn on the bipolar transistor at high speed.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of the present invention.

FIG. 2 is an operation timing chart.

FIG. 3 is a conventional circuit diagram.

FIG. 4 is an operation timing chart.

FIG. 5 is a performance graph.

FIG. 6 shows an embodiment of the first invention.

FIG. 7 shows an embodiment of the first invention.

FIG. 8 is a circuit diagram and an operation timing chart of the embodiment.

FIG. 9 is a circuit diagram and an operation timing chart of the embodiment.

FIG. 10 is a circuit diagram and an operation timing chart of the embodiment.

FIG. 11 is a circuit diagram and an operation timing chart of the embodiment.

FIG. 12 is a circuit diagram and an operation timing chart of the embodiment.

FIG. 13 is a circuit diagram and an operation timing chart of the embodiment.

FIG. 14 is a circuit diagram and an operation timing chart of an embodiment.

FIG. 15 is a circuit diagram and an operation timing chart of the embodiment.

FIG. 16 is a circuit diagram and an operation timing chart of the embodiment.

FIG. 17 is a circuit diagram and an operation timing chart of the embodiment.

FIG. 18 is a circuit diagram and an operation timing chart of the embodiment.

FIG. 19 is a circuit diagram and an operation timing diagram of an embodiment.

FIG. 20 is a circuit diagram and an operation timing chart of the embodiment.

FIG. 21 is a circuit diagram and an operation timing chart of an embodiment.

FIG. 22 is a circuit diagram and an operation timing chart of the embodiment.

FIG. 23 is a circuit diagram and an operation timing diagram of an embodiment.

FIG. 24 is a circuit diagram and an operation timing chart of an embodiment.

FIG. 25 is a circuit diagram and an operation timing chart of the embodiment.

FIG. 26 is a circuit diagram and an operation timing chart of an embodiment.

FIG. 27 is a circuit diagram and an operation timing chart of an embodiment.

FIG. 28 is a circuit diagram and an operation timing chart of an embodiment.

FIG. 29 is a circuit diagram and an operation timing chart of an embodiment.

FIG. 30 is a circuit diagram and an operation timing chart of an embodiment.

FIG. 31 is a circuit diagram and an operation timing chart of an embodiment.

FIG. 32 is a circuit diagram and an operation timing chart of an embodiment.

FIG. 33 is a circuit diagram and an operation timing chart of an embodiment.

FIG. 34 is a circuit diagram and an operation timing chart of an embodiment.

FIG. 35 is a circuit diagram and an operation timing chart of an example.

FIG. 36 is a circuit diagram and an operation timing chart of an example.

FIG. 37 is a circuit diagram and an operation timing chart of an embodiment.

FIG. 38 is a circuit diagram and an operation timing chart of an embodiment.

FIG. 39 is a circuit diagram and an operation timing chart of an embodiment.

FIG. 40 is a circuit diagram and an operation timing chart of an example.

FIG. 41 is a circuit diagram and an operation timing chart of an embodiment.

FIG. 42 is a circuit diagram and an operation timing chart of an embodiment.

FIG. 43 is a circuit diagram and an operation timing chart of an embodiment.

FIG. 44 is a circuit diagram and an operation timing chart of an embodiment.

FIG. 45 is a longitudinal sectional view of the embodiment.

FIG. 46 is a plan view of the embodiment.

FIG. 47 is a plan view of the embodiment.

FIG. 48 is a diagram illustrating an example of the present invention.

FIG. 49 illustrates an example of the present invention.

FIG. 50 illustrates an example of the present invention.

FIG. 51 illustrates an example of the present invention.

FIG. 52 illustrates an embodiment of the present invention.

FIG. 53 illustrates an embodiment of the present invention.

FIG. 54 illustrates an example of the present invention.

FIG. 55 illustrates an embodiment of the present invention.

FIG. 56 illustrates an embodiment of the present invention.

FIG. 57 illustrates an example of the present invention.

FIG. 58 illustrates an example of the present invention.

FIG. 59 illustrates an embodiment of the present invention.

FIG. 60 is a diagram illustrating an example of the present invention.

FIG. 61 is a diagram illustrating an example of the present invention.

FIG. 62 illustrates an embodiment of the present invention.

FIG. 63 shows a conventional Bi-CMOS inverter circuit.

FIG. 64 shows a conventional Bi-CMOS inverter circuit.

FIG. 65 is an explanatory diagram of the operation.

FIG. 66 is an operation explanatory view thereof.

FIG. 67 is an inverter circuit diagram according to an embodiment of the present invention.

FIG. 68 is an explanatory diagram of the operation.

FIG. 69 is a diagram showing a three-input NAND circuit according to an embodiment of the present invention.

FIG. 70 is a diagram showing a three-input NOR circuit according to an embodiment of the present invention.

FIG. 71 is a diagram showing a three-state inverter circuit according to an embodiment of the present invention.

FIG. 72 shows an inverter circuit according to another embodiment of the present invention.

FIG. 73 shows an inverter circuit according to another embodiment of the present invention.

FIG. 74 is a circuit diagram of an embodiment of the present invention.

FIG. 75 is an operation timing chart.

FIG. 76 is a circuit diagram showing an embodiment of the present invention.

FIG. 77 is a circuit diagram showing an embodiment of the present invention.

FIG. 78 is a circuit diagram showing an embodiment of the present invention.

FIG. 79 is a circuit diagram showing an embodiment of the present invention.

FIG. 80 is an operation timing chart.

[Explanation of symbols]

100 to 109... PMOS, 111 to 119, 317,
318 ... NMOS, 120, 121, 315, 316 ...
NPN transistor, 140, 141 ... resistance, 150-
154, 321, 322... CMOS inverter, 159
... Bi-CMOS inverter, 160 ... V _CC power supply, 161 ...
GND power supply, 162 to 164 input terminal, 165 output terminal, 166 enable terminal, 167 latch pulse terminal, 190, 191 current bypass element, 192,1
93: bipolar transistor, 194 to 196: FE
T, 200: first-layer metal wiring, 201: second-layer metal wiring, 204: first gate, 240, 241: transfer gate.

 ──────────────────────────────────────────────────の Continuing on the front page (72) Inventor Kozaburo Kurita 4026 Kuji-cho, Hitachi City, Ibaraki Prefecture Within Hitachi Research Laboratory, Hitachi, Ltd. (72) Kazuo Kato 4026 Kuji-machi, Hitachi City, Ibaraki Prefecture Hitachi Research, Ltd. In-house (56) References JP-A-57-212827 (JP, A) JP-A-62-5723 (JP, A) JP-A-59-11034 (JP, A) JP-A-59-25424 (JP, A)

Claims (10)

(57) [Claims] A plurality of logic circuits integrated on a single semiconductor substrate, wherein at least one of the plurality of logic circuits includes a first logic circuit having an absolute value of a potential difference of substantially less than 5V. A bipolar transistor having a second power terminal, at least one input terminal, an output terminal, a base, and a collector / emitter current path connected between the first power terminal and the output terminal; The gate is responsive to an input signal applied to the input terminal;
At least one first field effect transistor having a source / drain current path connected between the first power terminal and the base of the bipolar transistor; responsive to an input signal applied to the input terminal; The bipolar transistor performs on / off operation complementary to the on / off operation of the bipolar transistor, and a current path between a pair of main terminals is connected to a semiconductor switch element connected between the output terminal and the second power supply terminal. The base of the bipolar transistor and the output terminal
Connected between, when said bipolar transistor is on, output base and above said bipolar transistor
A second source-drain current path is formed between the
And a field-effect transistor . 2. A plurality of logic circuits are integrated on a single semiconductor substrate.
Of the plurality of logic circuits,
One of them is the first and second in which the absolute value of the potential difference is substantially less than 5V.
A power supply terminal, at least one input terminal, an output terminal, and a base;
A first bypass connected between a power supply terminal and the output terminal;
A polar transistor and a gate responsive to an input signal applied to the input terminal;
The source / drain current path is connected to the first power terminal and the first power terminal.
Connected to the base of one bipolar transistor
At least one first field effect transistor, and a base, wherein the collector-emitter current path is connected to the output terminal.
And a second power supply connected between the power supply terminal and the second power supply terminal.
A polar transistor and a gate responsive to an input signal applied to the input terminal;
The second bipolar transistor is connected to the first bipolar transistor.
The on / off operation of the transistor is complementary
Source / drain current path for
Between the terminal and the base of the second bipolar transistor
At least one second field effect transformer connected between
A transistor, a base of the first bipolar transistor, and the output
And the first bipolar transistor
When the star is on, the first bipolar transistor
Source-drain voltage between the base of the
A third field-effect transistor forming a flow path; a base of the second bipolar transistor;
Connected to the power supply terminal of the second bipolar transistor
When the transistor is on, the second bipolar tiger
Between the base of the transistor and the second power supply terminal.
.Fourth field effect transistors forming drain current paths
The semiconductor integrated circuit device, characterized in that it is composed of a motor. 3. The first power supply terminal and the second power supply terminal.
The absolute value of the potential difference between 3.3V and 0.3V is substantially
3. The semiconductor integrated circuit device according to item 1 or 2, which satisfies . 4. The first power supply terminal and the second power supply terminal.
The absolute value of the potential difference between
3. The semiconductor integrated circuit device according to item 1 or 2 . 5. The first power terminal and the second power terminal.
The absolute value of the potential difference between
3. The semiconductor integrated circuit device according to item 1 or 2 . 6. The first power supply terminal and the second power supply terminal.
The absolute value of the potential difference between
3. The semiconductor integrated circuit device according to item 1 or 2 . 7. The first power terminal and the second power terminal.
The absolute value of the difference between the potential and the potential is substantially less than 3.0 V ± 10%.
3. The semiconductor integrated circuit device according to item 1 or 2 . 8. The first power supply terminal and the second power supply terminal.
The absolute value of the potential difference between
3. The semiconductor integrated circuit device according to item 1 or 2 . 9. The first power terminal and the second power terminal.
The absolute value of the potential difference between
3. The semiconductor integrated circuit device according to item 1 or 2 . 10. The first power terminal and the second power terminal.
If the absolute value of the potential difference with the element is 4.0 V or more and less than 5.0 V
3. The semiconductor integrated circuit device according to claim 1 or 2, which is substantially satisfied .