JP2725481B2 - Circular bus - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus which realizes an extremely high data transfer throughput by dramatically increasing the data transfer period limited by the signal propagation distance by performing physical division.

[0002]

2. Description of the Related Art In a conventional computer system, generally, boards constituting the system are connected via a bus. However, there is a problem that the bus wiring length must be sufficiently shorter than the distance over which the signal propagates during the data transfer cycle, and the data transfer cycle cannot be shortened to a certain extent. This is a problem caused by the physical size of the boards that make up the system. A general system requires a bus wiring length of about several tens of centimeters, so the data transfer cycle is several Set to 10 nS.

When the main memory is shared, the performance of the system largely depends on the ability to supply data from the main memory, that is, the data transfer throughput of the bus. For example, in a bus-coupled multiprocessor system, it has been pointed out that it is necessary to increase the data transfer throughput of the bus because the bus becomes a bottleneck.

In order to increase the data throughput of the bus,
Conventionally, the following method has been proposed. Separation of control and data transfer for bus occupation.Operation of bus occupancy is performed at a low frequency that is appropriate for the physical size of the bus.When the bus can be occupied, data is transmitted at a higher frequency. This is a method for performing transfer. In this case, the distance over which the signal propagates during the data transfer cycle becomes shorter, and in some cases,
Since the length is shorter than the wiring length of the bus, a plurality of data being transferred exist on the bus. When data transfer is performed at such a high frequency, it is necessary to take a termination to suppress signal reflection, but it is difficult to take a termination because a bus has a plurality of branches when viewed as a line. Therefore, a pipeline bus divides the bus by a register, connects the transmitting end and the receiving end of a signal in a one-to-one manner, takes a terminal end, suppresses reflection, and performs data transfer at a higher frequency.

[0005]

In a conventional pipeline bus, the bus is managed as one shared resource. That is, when trying to access the main memory via the bus, first, the occupation of the bus is requested, and the transfer is started when the occupation of the bus is successful. For this reason, although the bus has a high transfer capability, it cannot exert its full power during the occupation control of the bus, and the data transfer efficiency is reduced, which is an obstacle to increasing the data transfer throughput.

[0006]

In order to avoid a reduction in data transfer efficiency, which has been a problem in the conventional pipeline bus, in the ring bus of the present invention, the units constituting the system determine the occupied state of the bus. Occupied lines, data lines,
Is connected to the annular result of the data transfer when the data transfer is done via the bus by the state line to notify the unit starts the data transfer, also cyclic data transfer
One on the transmission route or the number of units that make up the system
Data propagating on the data transfer path to fewer points than
A repeater for matching the phase of the
An annular bus constituted by a data line and the status line;
Propagation information and the result of data transfer propagate in one direction
Corresponding to the occupation signal indicating the occupation state on the occupation line.
Occupancy management for partial buses
Delay required for data phase matching and data synchronization
Minimizes high throughput and short
It is characterized by realizing a long delay at the same time.

[0007]

Next, the operation of the present invention will be described with reference to the drawings. FIG. 1 is a diagram showing components of the present invention. In FIG. 1, 1 is a requester, 2 is a server, 3 is an occupation line, 4 is a data line, 5 is a status line, 6 is a slot definer line, and 8 is a repeater.

FIG. 2 is a diagram showing the structure of a requester 1 which is a component of the present invention. FIG. 3 is a diagram showing a configuration of the server unit 2 which is a component of the present invention. 2 and 3, reference numeral 12 denotes data transfer control means, 13 denotes data reception means, and 14 denotes a directional coupler.

In the ring bus of the present invention, one or more requesters 1, one or more servers and a repeater 2 are connected by an occupation line 3, a data line 4, a status line 5 and a slot definer line 6 to form a ring. No. The signal turns in one direction on the ring-shaped signal line, and N signals are simultaneously present on the ring-shaped signal line. For this purpose, the annular bus may be physically divided by a register, or a line with low dispersion such as an optical fiber may be used. When a line such as an optical fiber is used, assuming that the length of the annular signal line is L, the signal duration T at one annular point is given by the following equation (1). In the equation (1), υ is a signal propagation speed. T = L / Nυ (1)

[0010] The duration of the signal is called a slot duration, and data transfer in the ring bus of the present invention is controlled by a slot definer having a cycle of the slot duration. When the circular bus is physically divided by the register, a clock for holding data in the register is a slot definer.

In practice, the slot definer is generated by an oscillator, and the length of a physically constituted annular signal line does not always satisfy the relationship of the equation (1). For this reason, in the ring bus of the present invention, the repeater 8 is inserted at one point of the ring. The repeater 8 can slightly delay a signal traveling in one direction on the annular signal line, and satisfies the relationship of the expression (1) regardless of the physical length of the annular signal line. Adjustments are made. The repeater 8 supplies a slot definer to the circular bus.

In the through state, the directional coupler 14 is configured to directly output the input data. In the cross state, the directional coupler 14 outputs the data to the ring-shaped signal line and at the same time, regardless of the data to be output. The input data can be read. The directional coupler 1
4 is normally in a through state.

When data to be transferred is input, the data transfer control means 12 of the requester 1 first
At the same time as outputting the occupation signal indicating the occupation state of the slot on the occupation line 3,
The signal on the occupation line 3 is checked to confirm whether the slot has been occupied. When the slot can be occupied, the directional coupler 14 of the data line 4 should be set to the cross state after the confirmation time, which is the time required to confirm that the slot can be occupied, and transferred to the data line 4. Output data.
If the slot cannot be occupied, the data transfer control means 12 repeats the data transfer procedure until the data can be transferred.

The data receiving means 13 of the server 2 always
The occupation signal on the occupation line 3 is checked, and if the slot is occupied, the data sent on the data line is checked after the occupation confirmation time to determine whether to accept the data. When receiving data, the data receiving means 13
Sets the directional coupler 14 of the state line 5 to the cross state after the state transition time, which is the time required to determine whether to accept data, and puts the unit state information, which is the result of receiving the data, on the state line. Output.

The requester 1 occupying the slot includes:
An occupancy signal indicating the occupation of the slot returns after the rotation time. The data transfer control means 12 of the requester 1 which has occupied the slot makes the directional coupler 14 of the occupied line 3 again in the cross state after the lap time has elapsed after the occupation of the slot, clears the occupied signal output by itself, To release. After the slot is released and the state transition time has elapsed, the data transfer control means 12 checks the unit state information on the state line 5 and confirms whether or not the transferred data has been received. If the transferred data is not accepted, the data transfer control means 12 performs the data transfer again.

FIG. 10 shows the slot definer and the occupied line 3.
FIG. 9 is a diagram showing a time relationship among the above occupation signal, data on the data line 4, and unit status information on the status line 5.

[0017]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 4 is a diagram showing one embodiment of the circular bus of the present invention. In FIG. 4, reference numeral 200 denotes a circular bus according to the present embodiment. 20 is a cash unit and requester 1
And the function of the server 2. A memory unit 30 also has the functions of the requester 1 and the server 2. A repeater unit 80 corresponds to the repeater 8. The circular bus 200 according to the present embodiment includes one or more cache units 20, one or more memory units 30, and one repeater unit 80. Each unit includes an occupation line 3, a data line 4, a status line 5, and a slot. They are connected in a ring shape by a definer wire 6. In this embodiment, an optical fiber is used as a signal line connecting the units. Furthermore, the cache unit 20, the memory unit 30, and the repeater unit 80
Supplies light guided from an external laser transmitter 90.

FIG. 5 is a diagram showing the configuration of the cache unit 20. In FIG. 5, 21 is a tag memory, 22 is a data memory, 23 is a tag search unit, 24 is an access control unit, and 25 is a consistency maintenance control unit. The consistency maintaining control unit 25 has a function of the data receiving unit 13. 12 is a data transfer control means, and 40 is an optical cross switch.
The optical cross switch 40 corresponds to the directional coupler 14.
The cache unit 20 has three sets of optical cross switches 40 corresponding to the occupation line 3, the data line 4, and the state line 5.

When a memory access is made from the external processor, the tag search unit 23 of the cache unit 20 searches the tag memory 21 and the data specified by the address is held in the data memory 22;
When the data status information recorded as a part of the tag is exclusively owned, that is, when the data specified by the address is owned, the data in the data memory 22 is directly accessed. If the user does not own the data specified by the address, the access control unit 24
To access the main memory via the circular bus 200.

FIG. 6 shows the structure of the memory unit 30. In FIG. 6, 31 is a memory bank, and 32 is a bank access control unit. The bank access control unit has the function of the data receiving unit 13. Further, reference numeral 40 denotes an optical cross switch corresponding to the directional coupler 14. The memory unit 30 has three sets of optical cross switches 40 corresponding to the occupation line 3, the data line 4, and the state line 5. In this embodiment, the main memory is composed of one or more memory units 30. The main storage space is divided, and each memory unit 30 implements one or more memory banks 31 corresponding to a subspace. The data specified by the address is stored in the memory bank 31 together with the state of the data.

FIG. 7 is a diagram showing the configuration of the optical cross switch 40. In FIG. 7, 41 is a global input, 42 is a global output, 43 is a local input, 44 is a local output, and 45 is a control signal input. 46 is an optical switch, 47 is a photodetector, 48 is a transmission signal input, and 49 is a reception signal output.
Further, 82 is a reference point light detector, and 83 is a reference signal output. Only the optical cross switch of the repeater unit 80 has the reference point light detector 82 and the reference point signal output.

The optical cross switch 40 has a control signal input 4
5, a switching state can be switched between a through state and a cross state.
In the through state, the global input 41 and the global output 42 are connected, and a signal input from the outside is output to the outside as it is. In the cross state, the global input 41 and the local output 44
The local input 43 and the global output 42 are respectively connected. The light supply line 7 is connected to the local input 43 via an optical switch 46, and a signal input from a transmission signal input 48 is output to the ring bus 200 as an optical signal. At the same time, the optical signal on the circular bus 200 is
And is output from the reception data output 49.
Thus, in the cross state, it is possible to output data to the outside and, at the same time, read data input from the outside irrespective of the data to be output.

FIG. 8 is a diagram showing the structure of the repeater unit 80. In FIG. 8, 81 is a variable delay element, and 84 is a slot definer oscillator. Repeater unit 8
0 has three sets of variable delay elements corresponding to the occupation line 3, the data line 4 and the state line 5. Reference numeral 40 denotes an optical cross switch. The repeater unit 80 has three sets of optical cross switches 4 corresponding to the occupied line 3, the data line 4 and the state line 5.
It has 0. The optical cross switch 40 of the repeater unit 80 has, in particular, the local output 4 after the global output 42.
The reference point light detector 82 is installed at the same distance from the light detector 4 as the light detector 47.

FIG. 9 is a diagram showing the configuration of the variable delay element 81. In FIG. 9, reference numeral 811 denotes a minute delay element, which is composed of several optical fibers having different lengths. 812 is a delay selector, and 813 is a phase control unit.

When the system is started, first, the repeater unit 80 adjusts the delay time in the variable delay element 81, and changes the round time that varies depending on the length of the optical fiber of each signal line constituting the ring to the slot duration time. Adjust to an integer multiple of.

For this purpose, first, the repeater unit 80
Sets the optical cross switch 40 of each signal line to the cross state,
The optical switch 46 repeats ON / OFF of the light every slot duration time. The phase controller 813 integrates the output difference between the photodetector 47 and the reference point photodetector 82, and selects an optical fiber having a different length of the minute delay element 811 by the delay selector 812, and the integrated value, that is, the phase difference is changed. Adjust so that it becomes the smallest.

When the adjustment of the delay time is completed, the repeater unit 80 puts the optical cross switch of each signal line into the through state, and furthermore, sets the circulating time to each cache unit 2.
0 and the memory unit 30 are notified. The notification of the circulation time causes the cache unit 20 and the memory unit 30 to start operating. For this purpose, the repeater unit further sets the optical cross switch 40 of the occupied line 3 to the cross state for one slot duration, and measures the time until the occupied signal returns in units of slot definers. When the occupancy signal returns, the repeater unit 8
Since 0 indicates the circulation time, the simplest method is to use the data transfer procedure in order to notify each unit of the circulation time. When detecting data transmission using the circulation time as data, each unit records the circulation time. This eliminates the need to externally set the circling time that varies depending on the length of the signal line that forms the ring, thereby improving the independence of the system.

First, data transfer on the circular bus 200 of the present invention will be described. In order to transfer data, occupation of a slot as a unit of transfer is requested, and data to be transferred is output to the data line 4 when the slot can be occupied.

For this purpose, first, when the slot arrives, that is, at the rise of the clock definer, the optical cross switch 40 of the occupied line is set to the cross state, and an occupation signal indicating the occupation state is output. Find out if you were in a state. If the slot is not in the occupied state, that is, if the slot has been successfully occupied, the optical cross switch 4 of the data line 4 is output after the occupation confirmation time, which is the operation time required to confirm the occupation state of the slot.
The data to be transferred is output to the data line with 0 being in the cross state. If the slot fails to be occupied, wait until the slot is successfully occupied and data can be transferred.

The occupied slot reaches the unit that has occupied the slot again after a lap time, which is a time required to make one round of the circular bus. The unit that occupies the slot makes the optical cross switch 40 of the occupied line 3 in the cross state for the duration of one slot after the circulation time elapses after occupying the slot, and clears the occupied signal set on the occupied line 3.

The unit constantly monitors the occupation line 3, and when confirming that the slot is in the occupied state, samples the data after the occupation confirmation time has elapsed.
As a result of checking the attribute of the data, if the data is received, if the data is received, after the state transition time, which is the time required for deciding to receive the data, the optical cross switch 40 of the state line 5 for one slot duration time. Is set to the cross state, and unit status information indicating the result of the data transfer is output to notify that data has been received. At the same time, the unit status information is sampled at the local output 44 of the optical cross switch 40 on the status line 5, the unit identifier which is a part of the unit status information is checked, and if the data has already been received by another unit, an error is generated. Notice. The unit that has occupied the slot and performed data transfer releases the slot after the elapse of the rotation time, and after the elapse of the state transition time, sets the optical cross switch 40 of the state line 5 to the cross state for the elapse of one slot. Simultaneously with the clearing of the line, sampling of the unit status information is performed, the unit identifier which is a part of the unit status information is checked, and it is confirmed whether or not the transferred data has been accepted. If the transferred data is not accepted, the unit performs data transfer again.

Next, a description will be given of a memory access in the circular bus 200 of this embodiment. When the cache unit 20 does not own the data accessed from the external processor, the cache unit 20 activates the access control unit 24 and performs a memory access via the circular bus 200. When the access control unit 24 is activated, the data transfer control unit 12
To perform data transfer using a set of an address and a memory access attribute as data. Thereby, a memory access is issued. The cache unit 20 that has issued the memory access releases the slot occupied after the circulation time elapses after issuing the memory access, and further sets the optical cross switch 40 of the state line 5 to 1 after the elapse of the state transition time. The cross state is set for the slot duration, and the unit state information on the state line 5 is checked. The identifier of the unit that has received the memory access is recorded as unit status information. The cache unit 20 that has issued the memory access can determine whether the issued memory access has been accepted by checking the identifier of the unit. After confirming that the issued memory access has been accepted, in the case of read access, wait for the read data to be sent back from the unit that received the memory access, and exclusively own the status information recorded as part of the tag At the same time, the read data is written to the data memory 22, and the read data is supplied to an external processor. In the case of write access, the data transfer control means 12
To transfer write data. If the issued memory access is not accepted, that is, the ownership transfer is in progress by another memory access,
The cache unit 20 is adapted to reissue the memory access.

The memory unit 30 always checks whether the slot is occupied. If the slot is occupied, the memory unit 30 further checks the data being transferred. If the data transfer is a memory access, it is checked whether the data is assigned to the data specified by the address transferred as the data. When it is in charge of the data specified by the address, a set of data and state information is read from the corresponding memory bank 31, and if the state information is exclusively occupied, acceptance of the memory access is determined. When the memory access is accepted, the optical cross switch 40 of the state line 5 is set to the cross state for the duration of one slot after the state transition time, and the state information including the unit identifier is output. When the memory access is a read access, the memory unit 3
0 indicates that it has decided to accept the memory access,
At the same time that the state information is not owned, the data transfer control means 12 is activated, and the read data is sent back to the cache unit 20 which has issued the memory access. If the memory access is a write access, confirm that the status information that is part of the word is not owned, wait for the write data to be sent, and when the write data is sent, The data state information corresponding to the data is exclusively owned, and the write data is written to the memory bank 31.

The cache unit 20 also always
Checking if a slot is occupied. When the slot is occupied, the consistency maintaining control unit 25 further examines the transferred data. When the data transfer is a memory access, the consistency maintaining control unit 25 stores the data in the tag memory 31 according to the address transferred as the data. Perform a search. As a result of the search, if the data specified by the address is held in the data memory 22 and the data status information recorded as a part of the tag indicates exclusive ownership, that is, the data specified by the address If the data is owned, the data transfer control unit 12 is activated and the read data is sent back to the cache unit that issued the memory access.

As described above, by transferring the ownership of data between the memory unit 30 and the cache unit 20, only one copy can be made for one address on the system constituted by the circular bus 200. It is enabled. In addition, data changes are made only by the unit that owns the data, which can cause problems with data coherency in systems with multiple copies of one data, such as systems with caches. Avoids sexual issues.

In the ring bus 200 of the present embodiment, in order to avoid unfair service among units, a waiting time and a bus occupancy are defined for each request. Control is performed such that slots are given priority. Each unit constantly obtains the slot occupancy by monitoring the occupied line, and when the slot occupancy exceeds a certain value, a data transfer request occurs and the slot occupancy request is issued until a certain time elapses. Do not do. In the fixed time, depending on the priority of the data transfer, a short time is assigned to a higher priority.
Longer times are set for those with lower priorities. This reduces slot occupancy,
Service inequity is avoided.

When data transfer is to be performed at an extremely high frequency as in the present embodiment, the problem of delay time between signal lines becomes remarkable. If the variation in the delay time is large, data may be destroyed. FIG. 11 is a diagram illustrating a situation in which data is destroyed due to a variation in delay time, and FIG. 12 is a diagram illustrating a relationship between a slot definer and data in the present embodiment. In this embodiment, a plurality of data are transferred during one slot duration. By taking a margin for absorbing a difference in delay time, data is prevented from being destroyed due to a variation in delay time. The data transfer period can be the highest frequency available with the technology at that time, but since the slot definer does not operate at the highest frequency because of phase control, it transfers multiple data during one slot duration. Doing is a realistic choice.

[0038]

According to the present invention, the efficiency of bus occupancy control in a pipeline bus for the purpose of improving the data transfer throughput can be improved, and the data transfer throughput can be further increased.

[Brief description of the drawings]

FIG. 1 is a diagram showing components of the present invention.

FIG. 2 is a diagram showing a configuration of a requester 1 in FIG.

FIG. 3 is a diagram showing a configuration of a server unit 2 in FIG.

FIG. 4 is a diagram showing one embodiment of a circular bus of the present invention.

FIG. 5 is a diagram showing a configuration of a cache unit 20 in FIG. 4;

6 is a diagram showing a configuration of a memory unit 30 in FIG.

FIG. 7 is a diagram illustrating a configuration of an optical cross switch 40 in FIG. 6;

FIG. 8 is a diagram showing a configuration of a repeater unit 80 in FIG.

9 is a diagram showing a configuration of a variable delay element 81 in FIG.

10 shows a slot definer, an occupation signal on an occupation line 3, data on a data line 4, and a status line 5 in the configuration of FIG.
It is a figure showing the time relation of the above-mentioned unit state information.

FIG. 11 is a diagram showing a situation in which data is destroyed due to a variation in delay time.

FIG. 12 is a diagram showing a relationship between a slot definer and data in the embodiment of FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Requester 2 Server 3 Occupation line 4 Data line 5 Status line 6 Slot definer line 8 Repeater 12 Data transfer control means 13 Data reception means 14 Directional coupler

Claims (1)

(57) [Claims] 1. A system comprising: an occupation line indicating a bus occupation state; a data line; and a unit which starts the data transfer when data is transferred via the bus. And one on the circular data transfer path.
Or a number smaller than the number of units that make up the system
Of the data propagating on the data transfer path to the point
And the repeater, and is constituted by the occupied line, the data line, and the state line.
Occupancy information and the result of data transfer on the formed circular bus
Is propagated in one direction to indicate the occupation state on the occupation line.
Occupancy management is performed for the partial bus corresponding to the occupancy signal.
Data phase matching
By minimizing the synchronization delay, high
A circular bus characterized by simultaneously realizing high throughput and short delay .