JP2724152B2 - Signal level output circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial application field) The present invention relates to a signal level output circuit used for displaying an input level of an SHF receiver, for example.

(Prior Art) In an SHF receiver, a signal level device indicating reception sensitivity is used, and is used when adjusting the direction of an antenna. The signal level output circuit is a circuit that obtains a voltage output corresponding to the signal level [dB] input to the receiver.

FIG. 4 shows a general signal level output circuit.
This signal level voltage is taken from the loop of the automatic gain control (hereinafter referred to as AGC) circuit. That is, the input signal Vin of the reception signal input terminal 11 is supplied to the AGC amplifier 12,
The gain is controlled by the gain control voltage Vcont. AGC amplifier 12
Is output to the output terminal 13 and the AGC
The signal is supplied to the detector 14.

The output of the AGC detector 14 is supplied to the gain control terminal of the AGC amplifier 12 via the amplifier 15. As a result, the output of the AGC amplifier 12 is controlled in gain in accordance with the fluctuation of the level of the input signal, and is maintained at a constant level.

By the way, since the output of the amplifier 15 changes according to the level fluctuation of the input signal Vin, this can be used as a signal level voltage. Therefore, the output of the amplifier 15 is led to the output terminal 17 via the amplifier 16.

Here, assuming that the control sensitivity of the AGC amplifier 12 is A [dB / V], the detection sensitivity of the AGC detector 14 is B [V / dB], and the gain of the amplifier 15 is C, the gain G of the AGC loop is G = A × B × C Therefore, the output Vout becomes Vout = Vin × {1 / (A + B + C)}.

 FIG. 5 shows a specific circuit of the AGC amplifier 12.

The input signal Vin is provided between the terminals 2a and 2b. Terminals 2a, 2
The signal b is supplied to the bases of the transistors Q9 and Q10. Resistors R4 and R5 are connected between the emitters of the transistors Q9 and Q10 and the ground line GND, respectively, and a resistor R6 is connected between the emitters. The differential outputs from the collectors of transistors Q9 and Q10 are the common emitter of differential pair transistors Q5 and Q6, and the differential pair transistor, respectively.
Connected to common emitter of Q7 and Q8. Transistors Q6, Q
The collectors of 7 are commonly connected to a power supply line Vcc. The collector of the transistor Q5 is connected to the power line via the load resistor R9.
Connected to Vcc and to the base of transistor Q11. The collector of transistor Q8 is a load resistor.
Connected to the power supply line Vcc via R10 and to the base of the transistor Q12. Transistor Q11,
The collector of Q12 is connected to power supply line Vcc, and each emitter is connected to ground line GND via resistors R7 and R8, and to output terminals 3a and 3b.

On the other hand, 4a and 4b are control voltage input terminals. The control voltage input terminals 4a, 4b are connected to the bases of the transistors Q3, Q4. The emitters of the transistors Q3 and Q4 are resistors R
2, connected to a common constant current source 5 via R3. The collector of transistor Q3 is a diode-connected transistor Q
1, connected to the power supply line Vcc via the resistor R1, and to the common base of the transistors Q5 and Q8. The collector of the transistor Q4 is connected to the power supply line Vcc via the diode-connected transistor Q2 and the resistor R1, and to the common base of the transistor Q6 and the transistor Q7. As a result, the input signal Vin is output to the output terminals 3a and 3b with gain control by the control voltage Vcont applied between the terminals 4a and 4b.

It is known that the block surrounded by the dashed line 2 operates at a low voltage, and the portion for controlling the gain constituted by the transistors Q5 to Q8 also functions as a cascode, and has good frequency characteristics. Further, a control portion including the transistors Q1 to Q4 compensates for a change in gain of the AGC amplifier with respect to temperature.

The equation of the gain with respect to the control voltage of the above circuit can be expressed as follows.

If the control voltage Vcont and the gain of the AGC amplifier 12 are Av, Av [dB] = 10Log [k1 / (1 + k2 × Vcont)] (1) where k1 and k2 are constants. Here, when the AGC amplifier 12 is operated as an AGC loop, the output of the AGC amplifier 12 operates so as to be constant, so that the gain of the AGC amplifier 12 and the input level correspond to 1: 1. Therefore, the AGC voltage with respect to the input level of the AGC amplifier 12 has a logarithmic relationship as can be seen from equation (1). FIG. 6 shows this relationship.

As described above, since the signal level voltage is a voltage obtained by amplifying the AGC voltage, the signal level voltage is not linearly related to the input level of the AGC amplifier 12, and when the input level is small, the voltage fluctuation is large, and the input level is large. When the level is large, the voltage fluctuation becomes small. For this reason, when adjusting the antenna direction of the SHF receiver, there is a disadvantage that the output voltage sensitivity to the input level changes and it is difficult to use.

(Problems to be Solved by the Invention) The conventional signal level output circuit has a logarithmic relationship, not a linear relationship, with respect to the change in the input level of the AGC amplifier. Was misaligned.

Therefore, an object of the present invention is to provide a signal level output circuit that changes in proportion to the input level of an AGC amplifier and is effective for antenna direction adjustment.

[Structure of the Invention] (Means for Solving the Problems) The present invention provides means for logarithmically compressing and further expanding an AGC voltage of an AGC loop to obtain a signal level output.

Embodiment An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of the present invention. In FIG.
Since the AGC loop is the same as the conventional one, it is given the same reference numeral as in FIG. In this embodiment, the output of the amplifier 15, that is, the AGC voltage Vcont is supplied to the control terminal of the AGC amplifier 12 and also to the logarithmic compression circuit 21. Here, the logarithmically compressed signal is further expanded by an expansion circuit 22 and led out to an output terminal 24 as a signal level output via an amplifier 23.

The exponential conversion circuit composed of the logarithmic compression circuit 21 and the expansion circuit 22 is specifically configured as shown in FIG. AGC voltage Vcont is applied to transistor Q23 via terminal 21.
And supplied to the base of transistor Q26. The emitter of the transistor Q23 is connected to the constant current source 31 together with the base of the transistor Q24, and the collector of the transistor Q23 is connected to the emitter of the transistor Q21. The base of the transistor Q21 is connected to the base and the emitter of the transistor Q22, and the collectors of the transistors Q21 and Q22 are connected to the power supply line Vcc via the resistors R21 and R22, respectively. Thereby, the same current as the current flowing to the collector of the transistor Q23 flows to the collector of the transistor Q24.

On the other hand, the emitters of the transistors Q26 and Q25 are connected to the constant current source 32 via resistors R26 and R25, respectively.The collector of the transistor Q26 is connected to the emitter of the transistor Q28 and the transistor Q2.
Connected to the common base of 8 and Q27. Transistor Q2
The collectors of 8 and Q27 are connected to power supply line Vcc via resistors R24 and R23, respectively. Therefore, transistor Q26
Of the transistor Q27 flows through the emitter of the transistor Q27 due to the current mirror relationship. Here, the bases of transistors Q25 and Q24 are
Connected to V B1.

The emitter of transistor Q27 is connected to the base of transistor Q29. Transistor Q29 is transistor Q30
And each emitter is connected to a constant current source 33,
Each collector is connected to a power line via resistors R29 and R30.
It is connected to Vcc and is led out as output terminals 34a and 34b. The bases of the transistors Q29 and Q30 are connected to a bias power supply VB1 via resistors R27 and R28, respectively.

In this circuit, a current caused by a voltage difference between the bias voltage VB1 and the input voltage Vcont flows into the base of the transistor Q29.

According to the above circuit configuration, the relationship between the input voltage Vi and the output voltage Vo is as follows.

Vo = Vi ^γ (2) where γ = (R27 / R25) = (R28 / R26) As is apparent from the above equation (2), the output is exponentially converted with respect to the input voltage. Therefore, the aforementioned AG
If the C voltage is input to this circuit and the output is used as the signal level voltage, the AGC voltage logarithmically proportional to the input level [dBm] is converted exponentially, and a linear output can be obtained. This relationship is shown in FIG.

[Effects of the Invention] As described above, according to the present invention, a signal level output that changes linearly with respect to the input level of a received signal can be obtained with a simple configuration. In this case, the sensitivity of the output voltage to the input level becomes constant and the adjustment becomes easy.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram showing the configuration of an embodiment of the present invention, FIG. 2 is a circuit diagram showing a specific example of the logarithmic compression / expansion circuit of FIG.
FIG. 3 is a diagram showing an example of characteristics obtained by the present invention, and FIG.
FIG. 5 is a circuit diagram showing a conventional signal level output circuit, and FIG.
FIG. 4 is a circuit diagram specifically showing the AGC amplifier of FIG. 4, and FIG. 6 is a diagram showing characteristics of a conventional signal level output circuit. 12 …… AGC amplifier, 14 …… AGC detector, 15 …… Amplifier, 21
…… Logarithmic compression circuit, 22 …… Expansion circuit, 23 …… Amplifier.

Claims (1)

(57) [Claims] An automatic gain control circuit to which an input signal received from a satellite broadcast is supplied; an automatic gain control detection circuit for detecting an output of the automatic gain control circuit; Loop gain adjusting means for amplifying the output of the automatic gain control detection circuit and applying the amplified output to the gain control terminal of the automatic gain control circuit to form an automatic gain control loop; and the output from the loop gain adjusting means. Out of the loop and convert it to an output signal having a linear characteristic, and an amplifier for amplifying the output signal of the conversion means to an appropriate level as a satellite broadcast signal level signal output and outputting the signal. A signal level output circuit, characterized in that: