JP2720470B2 - Method of manufacturing thin film transistor matrix - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to a method for manufacturing a thin film transistor matrix for driving a liquid crystal, with the object of effectively reducing the resistance of a bus line through a simple manufacturing process. Laminating a first conductive film and a second conductive film and patterning the stacked layers to form a gate bus line having a two-layer structure and a gate electrode connected to the gate bus line; An interlayer insulating film is formed, a resist film covering the gate bus line is formed on the interlayer insulating film, and the exposed portion of the interlayer insulating film is removed using the resist film as a mask. It is configured to include a step of removing the exposed second conductive layer.

The present invention relates to a method for manufacturing a thin film transistor (TFT) matrix for driving a liquid crystal.

In recent years, in the thin film transistor matrix, the display area has been increased and the image quality has been improved, and the degree of integration of the elements has further increased. As described above, in order to achieve high integration of the elements, it is necessary to lower the resistance of the bus lines in addition to the defect-free and low cost.

[Conventional technology]

A conventional method for forming a low-resistance gate substrate of a thin film transistor matrix will be described with reference to FIGS. 5 (a) to 5 (g).
(A) to (e) of FIG. 6 are cross-sectional views of the main parts, and show cross-sectional views taken along the line AA of (f) and (g) of the main part plan views.

As shown in FIGS. 5 (a) and 5 (f), a Ti film 2 is formed on a glass substrate 1 as a transparent insulating substrate, and is patterned to form a gate electrode G and a gate bus line _BG.
Is formed, and an Al film 3 is formed thereon as shown in FIG. 5 (b).

Then FIG. 5 (c), as shown in (g), a resist film 4 on the gate bus line B _G, as illustrated in FIG. 5 (d), the exposure of the Al film 3 as a mask Remove the part. Thereafter, the resist film 4 is removed and the fifth
As shown in FIG. (E), leaving the Al film 3 only on the gate bus line B _G.

This conventional method for forming a low-resistance bus line requires two photolithography steps, which complicates the manufacturing process.

Further, as shown in the cross-sectional view of the main part of FIG.
After the gate electrode G is formed as described above, a gate insulating film 5 such as a SiN (silicon nitride) film and an operating semiconductor layer 6 thereon are continuously formed by a chemical vapor deposition (P-CVD) method. Form. Therefore, in this step, the Al film 3 and the Si in the gate insulating film 5 react with each other to provide a low-resistance film.
It increases the resistance of the Al film 3, thus the resistance of the gate bus line B _G increases.

In the figure, reference numeral 7 denotes an interlayer insulating film, S denotes a source electrode, D denotes a drain electrode, and _BD denotes a drain bus line.

[Problems to be solved by the invention]

As described above, the conventional method of manufacturing a thin film transistor matrix has a problem that the process of forming a low-resistance bus line is complicated, which not only increases the manufacturing cost, but also changes the bus line resistance during the manufacturing process and increases the resistance. ,
It was hard to say that the goal of lowering the resistance of the bus line was sufficiently achieved.

An object of the present invention is to effectively reduce the resistance of a bus line by a simple manufacturing process.

[Means for solving the problem]

1 (a) to 1 (g), the principle of the present invention will be described.
FIGS. 3A to 3E are cross-sectional views of main parts, and show cross-sectional views taken along the line AA in FIGS.

Ti film 2 as first conductive film on transparent insulating substrate 1
When the Al film 3 as a second conductive film was formed in the same chamber thereon, and then a gate pattern (and the gate pattern is used as a generic term for the gate electrode G and the gate bus line B _G) to define (See FIGS. 1 (a) and 1 (f)).

As the resist film 4 mask, the exposed portions of the Al film 3 and the Ti film 2 are removed, and the resist film 4 is peeled (see FIG. 1B).

Next, an interlayer insulating film 7 is formed, and the interlayer insulating film 7 is formed thereon.
A resist film 8 for pattern definition is formed [see FIG. 1 (c)].

Using the resist film 8 as a mask, the exposed portion of the interlayer insulating film 7 is removed, and the Al film 3 on the gate electrode G is further removed (see FIG. 1 (d)).

Thereafter, the resist film 8 is removed [see FIG. 1 (e)].

As described above, the gate electrode G consisting of only the Ti film 2 and the Al film 3
A laminated film of a Ti film 2, and the gate bus line B _G coated on the interlayer insulating film 7 is formed.

Thereafter, a gate insulating film 5, an active semiconductor layer 6 are formed, a source electrode S and a drain electrode D are formed, and then, a drain bus line _BD is formed. Thus, the thin film transistor shown in FIG. 2A is obtained. .

FIG. 2B is a plan view of a main part showing one pixel, and FIG. 2A is a cross-sectional view of a main part showing a cross section taken along line AA of FIG.

(Operation)

According to the above manufacturing method, the resist film 8 for patterning the interlayer insulating film is also used when removing the Al film 3 on the gate electrode G. Since the resist film 8 is shared in this way, the manufacturing process is simplified.

After forming the interlayer insulating film 7 on the Al film 3, the P-
Since the gate insulating film is formed by the CVD method, the Al film 3 is made of Si.
Not react with, and therefore the resistance of the gate bus line B _G does not increase.

〔Example〕

Hereinafter, an embodiment of the present invention will be described with reference to FIGS. 3 (a) to 3 (j).

A Ti film (about 40 nm in thickness) 2 and an Al film (about 50 nm in thickness) 3 are formed on a glass substrate 1 as a transparent insulating substrate by a sputtering method. [FIG. 3 (a)] Next, a resist film 4 for defining a gate pattern is formed thereon.
[FIGS. 3 (b) and (i)].

Next, using the resist film 4 as a mask, the underlying Al film 3 and Ti film 2 are etched, and then the resist film 4 is removed [FIG. 3 (c)].

Next, as an interlayer insulating film, for example, a polyimide PIQ-L100 manufactured by Hitachi Chemical Co., Ltd. is applied to a thickness of 100 nm, heated and cured to form a polyimide film 7 (FIG. 3D).

Next, a resist film 8 is formed on the polyimide film 7 (FIGS. 3E and 3J).

Using the resist film 8 as a mask, the polyimide film 7 is etched by a dry etching method (FIG. 3 (f)). In this step, the exposed portion of the polyimide film 7 is removed, and the surface of the Al film 3 of the gate electrode G is exposed.

Next, using the resist film 8 as a mask, the Al film 3 whose surface is exposed is etched. As a result, the gate electrode G
Has a structure in which the Al film 3 is removed and only one Ti film 2 is formed [FIG. 3 (g)].

 The resist is stripped (FIG. 3 (h)).

Through the above steps, the low-resistance gate bus line _BG is completed.

In the above embodiment, patterning of the interlayer insulating film 7
The same resist film 8 is used for removing the Al film 3 on the gate electrode G. Thus by a simple manufacturing process, it can form a gate bus line B _G of the low resistance.

Next, a manufacturing process after this manner to form a low-resistance gate bus line B _G, illustrated by FIG. 4 (a) ~ (d).

Figure 4 (a) shows a substrate having a low resistance gate bus line B _G shown in FIG. 3 described above (h), the same state.

On these, as shown in FIG. 4 (b), an SiN film 5 as a gate insulating film, an a-Si film 6 as an active semiconductor layer, and an SiO ₂ film 9 as a channel protective film are sequentially formed by a P-CVD method. I do.

Then, as shown in FIG. 4 (c), the back exposure method using the gate electrode G as a mask, the SiO ₂ film 9 is etched, of the SiO ₂ film 9, the portion left as the channel protective film on the gate electrode G Remove the other parts. Although not required the SiO ₂ film except necessarily on the gate bus line B _G, FIG is shown an example in which also removes SiO ₂ and the a-Si film on the lower layer.

Next, as shown in FIG. 4D, a laminated film 11 of a Cr film having a thickness of about 100 nm and an Al film having a thickness of about 500 nm is formed, and is patterned to form a drain bus line _BD .

The thin film transistor of the present embodiment completed as described above is
Since the Al film 3 constituting the gate bus line B _G it is covered by the interlayer insulating film 7, when performing the P-CVD method as the gate insulating film 5 and the active semiconductor layer 6 forming step, reacting with Si without, it can also be prevented accordingly issues the resistance of the gate bus line B _G increases.

〔The invention's effect〕

As described above, according to the present invention, the photolithography process is reduced and the process is simplified, and the resistance of the gate bus line does not increase during the manufacturing process, so that the resistance of the bus line can be effectively reduced.

[Brief description of the drawings]

1 (a) to 1 (g) are diagrams illustrating the principle of the present invention, FIGS. 2 (a) and 2 (b) are diagrams illustrating the principle of the present invention, and FIGS. 3 (a) to 3 (j) are diagrams illustrating the present invention. FIGS. 4 (a) to 4 (d) are explanatory diagrams of an embodiment of the present invention, FIGS. 5 (a) to 5 (g) are explanatory diagrams of a conventional method of forming a low-resistance gate bus line, FIG. FIG. 2 is a diagram for explaining a problem of a conventional low-resistance gate bus line forming method. In the figure, 1 is a transparent insulating substrate (glass substrate), 2 is a first conductive film (Ti film), 3 is a second conductive film (Al film), 4 is a resist film, 5 is a gate insulating film (SiN). 6, a working semiconductor layer (a-Si film), 7 an interlayer insulating film (polyimide film), 8 a resist film, G a gate electrode, D a drain electrode, S a source electrode, and _BG a gate bus. Line and _BD indicate a drain bus line.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Teruhiko Ichimura 1015 Uedanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Inside Fujitsu Limited (72) Inventor Norio Nagahiro 1015, Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Fujitsu Limited (56) References JP-A-63-77086 (JP, A)

Claims (1)

(57) [Claims] A first conductive film (2) and a second conductive film (3) are laminated on a transparent insulating substrate (1), and are patterned to form a gate bus line (B) having a two-layer structure. _G ) and a step of forming a gate electrode (G) connected to the gate bus line; and forming an interlayer insulating film (7) on the gate bus line (B _G ) and the gate electrode (G); A resist (8) film for covering the gate bus line ( _BG ) is formed on the film, and the exposed portion of the interlayer insulating film (7) is removed using the resist film (8) as a mask, and a gate electrode is formed. (G)
A step of removing the second conductive layer (3) exposed at the portion.